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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org> |
07af4276 | 3 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 | 4 | * |
44854add | 5 | * This is a look-alike variation of the ICH0 PIIX4 Ultra-66, |
1da177e4 LT |
6 | * but this keeps the ISA-Bridge and slots alive. |
7 | * | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/types.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
1da177e4 LT |
13 | #include <linux/pci.h> |
14 | #include <linux/hdreg.h> | |
15 | #include <linux/ide.h> | |
1da177e4 LT |
16 | #include <linux/init.h> |
17 | ||
a482958b BZ |
18 | static DEFINE_SPINLOCK(slc90e66_lock); |
19 | ||
88b2b32b | 20 | static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 LT |
21 | { |
22 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 23 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
24e6458d | 24 | int is_slave = drive->dn & 1; |
1da177e4 LT |
25 | int master_port = hwif->channel ? 0x42 : 0x40; |
26 | int slave_port = 0x44; | |
27 | unsigned long flags; | |
28 | u16 master_data; | |
29 | u8 slave_data; | |
5749c847 | 30 | int control = 0; |
24e6458d | 31 | /* ISP RTC */ |
5749c847 | 32 | static const u8 timings[][2] = { |
24e6458d SS |
33 | { 0, 0 }, |
34 | { 0, 0 }, | |
35 | { 1, 0 }, | |
36 | { 2, 1 }, | |
37 | { 2, 3 }, }; | |
1da177e4 | 38 | |
a482958b | 39 | spin_lock_irqsave(&slc90e66_lock, flags); |
1da177e4 | 40 | pci_read_config_word(dev, master_port, &master_data); |
24e6458d SS |
41 | |
42 | if (pio > 1) | |
43 | control |= 1; /* Programmable timing on */ | |
44 | if (drive->media == ide_disk) | |
45 | control |= 4; /* Prefetch, post write */ | |
46 | if (pio > 2) | |
47 | control |= 2; /* IORDY */ | |
1da177e4 | 48 | if (is_slave) { |
24e6458d SS |
49 | master_data |= 0x4000; |
50 | master_data &= ~0x0070; | |
51 | if (pio > 1) { | |
07af4276 SS |
52 | /* Set PPE, IE and TIME */ |
53 | master_data |= control << 4; | |
24e6458d | 54 | } |
1da177e4 | 55 | pci_read_config_byte(dev, slave_port, &slave_data); |
07af4276 SS |
56 | slave_data &= hwif->channel ? 0x0f : 0xf0; |
57 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << | |
58 | (hwif->channel ? 4 : 0); | |
1da177e4 | 59 | } else { |
24e6458d SS |
60 | master_data &= ~0x3307; |
61 | if (pio > 1) { | |
1da177e4 | 62 | /* enable PPE, IE and TIME */ |
07af4276 | 63 | master_data |= control; |
24e6458d | 64 | } |
07af4276 | 65 | master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
1da177e4 LT |
66 | } |
67 | pci_write_config_word(dev, master_port, master_data); | |
68 | if (is_slave) | |
69 | pci_write_config_byte(dev, slave_port, slave_data); | |
a482958b | 70 | spin_unlock_irqrestore(&slc90e66_lock, flags); |
1da177e4 LT |
71 | } |
72 | ||
88b2b32b | 73 | static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
74 | { |
75 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 76 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 77 | u8 maslave = hwif->channel ? 0x42 : 0x40; |
1da177e4 LT |
78 | int sitre = 0, a_speed = 7 << (drive->dn * 4); |
79 | int u_speed = 0, u_flag = 1 << drive->dn; | |
80 | u16 reg4042, reg44, reg48, reg4a; | |
81 | ||
82 | pci_read_config_word(dev, maslave, ®4042); | |
83 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
84 | pci_read_config_word(dev, 0x44, ®44); | |
85 | pci_read_config_word(dev, 0x48, ®48); | |
86 | pci_read_config_word(dev, 0x4a, ®4a); | |
87 | ||
1da177e4 | 88 | if (speed >= XFER_UDMA_0) { |
4db90a14 BZ |
89 | u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4); |
90 | ||
1da177e4 LT |
91 | if (!(reg48 & u_flag)) |
92 | pci_write_config_word(dev, 0x48, reg48|u_flag); | |
93 | /* FIXME: (reg4a & a_speed) ? */ | |
94 | if ((reg4a & u_speed) != u_speed) { | |
95 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
96 | pci_read_config_word(dev, 0x4a, ®4a); | |
97 | pci_write_config_word(dev, 0x4a, reg4a|u_speed); | |
98 | } | |
99 | } else { | |
8c91abf8 | 100 | const u8 mwdma_to_pio[] = { 0, 3, 4 }; |
1c54a93d | 101 | u8 pio; |
8c91abf8 | 102 | |
1da177e4 LT |
103 | if (reg48 & u_flag) |
104 | pci_write_config_word(dev, 0x48, reg48 & ~u_flag); | |
105 | if (reg4a & a_speed) | |
106 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
8c91abf8 BZ |
107 | |
108 | if (speed >= XFER_MW_DMA_0) | |
109 | pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; | |
110 | else | |
111 | pio = 2; /* only SWDMA2 is allowed */ | |
1da177e4 | 112 | |
1c54a93d BZ |
113 | slc90e66_set_pio_mode(drive, pio); |
114 | } | |
1da177e4 LT |
115 | } |
116 | ||
bfa14b42 | 117 | static u8 __devinit slc90e66_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 118 | { |
36501650 | 119 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
bfa14b42 | 120 | u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02; |
1da177e4 | 121 | |
36501650 | 122 | pci_read_config_byte(dev, 0x47, ®47); |
1da177e4 | 123 | |
bfa14b42 BZ |
124 | /* bit[0(1)]: 0:80, 1:40 */ |
125 | return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
126 | } | |
127 | ||
ac95beed BZ |
128 | static const struct ide_port_ops slc90e66_port_ops = { |
129 | .set_pio_mode = slc90e66_set_pio_mode, | |
130 | .set_dma_mode = slc90e66_set_dma_mode, | |
131 | .cable_detect = slc90e66_cable_detect, | |
132 | }; | |
1da177e4 | 133 | |
85620436 | 134 | static const struct ide_port_info slc90e66_chipset __devinitdata = { |
1da177e4 | 135 | .name = "SLC90E66", |
5749c847 | 136 | .enablebits = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} }, |
ac95beed | 137 | .port_ops = &slc90e66_port_ops, |
5e71d9c5 | 138 | .host_flags = IDE_HFLAG_LEGACY_IRQS, |
4099d143 | 139 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
140 | .swdma_mask = ATA_SWDMA2_ONLY, |
141 | .mwdma_mask = ATA_MWDMA12_ONLY, | |
142 | .udma_mask = ATA_UDMA4, | |
1da177e4 LT |
143 | }; |
144 | ||
145 | static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
146 | { | |
147 | return ide_setup_pci_device(dev, &slc90e66_chipset); | |
148 | } | |
149 | ||
9cbcc5e3 BZ |
150 | static const struct pci_device_id slc90e66_pci_tbl[] = { |
151 | { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 }, | |
1da177e4 LT |
152 | { 0, }, |
153 | }; | |
154 | MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl); | |
155 | ||
156 | static struct pci_driver driver = { | |
157 | .name = "SLC90e66_IDE", | |
158 | .id_table = slc90e66_pci_tbl, | |
159 | .probe = slc90e66_init_one, | |
160 | }; | |
161 | ||
82ab1eec | 162 | static int __init slc90e66_ide_init(void) |
1da177e4 LT |
163 | { |
164 | return ide_pci_register_driver(&driver); | |
165 | } | |
166 | ||
167 | module_init(slc90e66_ide_init); | |
168 | ||
169 | MODULE_AUTHOR("Andre Hedrick"); | |
170 | MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE"); | |
171 | MODULE_LICENSE("GPL"); |