]>
Commit | Line | Data |
---|---|---|
33dced2e | 1 | /* |
33dced2e SS |
2 | * Copyright (C) 2002 Toshiba Corporation |
3 | * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com> | |
4 | * | |
5 | * This file is licensed under the terms of the GNU General Public | |
6 | * License version 2. This program is licensed "as is" without any | |
7 | * warranty of any kind, whether express or implied. | |
8 | */ | |
9 | ||
10 | #include <linux/types.h> | |
11 | #include <linux/pci.h> | |
12 | #include <linux/ide.h> | |
13 | ||
88b2b32b | 14 | static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed) |
33dced2e SS |
15 | { |
16 | ide_hwif_t *hwif = HWIF(drive); | |
17 | unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00); | |
31e8a465 | 18 | u16 mode, scr = inw(scr_port); |
33dced2e | 19 | |
33dced2e | 20 | switch (speed) { |
5c634bb9 PC |
21 | case XFER_UDMA_4: mode = 0x00c0; break; |
22 | case XFER_UDMA_3: mode = 0x00b0; break; | |
23 | case XFER_UDMA_2: mode = 0x00a0; break; | |
24 | case XFER_UDMA_1: mode = 0x0090; break; | |
25 | case XFER_UDMA_0: mode = 0x0080; break; | |
26 | case XFER_MW_DMA_2: mode = 0x0070; break; | |
27 | case XFER_MW_DMA_1: mode = 0x0060; break; | |
28 | case XFER_MW_DMA_0: mode = 0x0050; break; | |
29 | case XFER_PIO_4: mode = 0x0400; break; | |
30 | case XFER_PIO_3: mode = 0x0300; break; | |
31 | case XFER_PIO_2: mode = 0x0200; break; | |
32 | case XFER_PIO_1: mode = 0x0100; break; | |
33 | case XFER_PIO_0: | |
34 | default: mode = 0x0000; break; | |
33dced2e SS |
35 | } |
36 | ||
37 | scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f; | |
38 | scr |= mode; | |
0ecdca26 | 39 | outw(scr, scr_port); |
33dced2e SS |
40 | } |
41 | ||
26bcb879 | 42 | static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio) |
33dced2e | 43 | { |
88b2b32b | 44 | tc86c001_set_mode(drive, XFER_PIO_0 + pio); |
33dced2e SS |
45 | } |
46 | ||
47 | /* | |
48 | * HACKITY HACK | |
49 | * | |
50 | * This is a workaround for the limitation 5 of the TC86C001 IDE controller: | |
51 | * if a DMA transfer terminates prematurely, the controller leaves the device's | |
52 | * interrupt request (INTRQ) pending and does not generate a PCI interrupt (or | |
53 | * set the interrupt bit in the DMA status register), thus no PCI interrupt | |
54 | * will occur until a DMA transfer has been successfully completed. | |
55 | * | |
56 | * We work around this by initiating dummy, zero-length DMA transfer on | |
57 | * a DMA timeout expiration. I found no better way to do this with the current | |
58 | * IDE core than to temporarily replace a higher level driver's timer expiry | |
59 | * handler with our own backing up to that handler in case our recovery fails. | |
60 | */ | |
61 | static int tc86c001_timer_expiry(ide_drive_t *drive) | |
62 | { | |
63 | ide_hwif_t *hwif = HWIF(drive); | |
64 | ide_expiry_t *expiry = ide_get_hwifdata(hwif); | |
65 | ide_hwgroup_t *hwgroup = HWGROUP(drive); | |
31e8a465 | 66 | u8 dma_stat = inb(hwif->dma_status); |
33dced2e SS |
67 | |
68 | /* Restore a higher level driver's expiry handler first. */ | |
69 | hwgroup->expiry = expiry; | |
70 | ||
71 | if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */ | |
72 | unsigned long sc_base = hwif->config_data; | |
73 | unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04); | |
31e8a465 | 74 | u8 dma_cmd = inb(hwif->dma_command); |
33dced2e SS |
75 | |
76 | printk(KERN_WARNING "%s: DMA interrupt possibly stuck, " | |
77 | "attempting recovery...\n", drive->name); | |
78 | ||
79 | /* Stop DMA */ | |
0ecdca26 | 80 | outb(dma_cmd & ~0x01, hwif->dma_command); |
33dced2e SS |
81 | |
82 | /* Setup the dummy DMA transfer */ | |
0ecdca26 BZ |
83 | outw(0, sc_base + 0x0a); /* Sector Count */ |
84 | outw(0, twcr_port); /* Transfer Word Count 1 or 2 */ | |
33dced2e SS |
85 | |
86 | /* Start the dummy DMA transfer */ | |
0ecdca26 BZ |
87 | outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */ |
88 | outb(0x01, hwif->dma_command); /* set START_STOPBM */ | |
33dced2e SS |
89 | |
90 | /* | |
91 | * If an interrupt was pending, it should come thru shortly. | |
92 | * If not, a higher level driver's expiry handler should | |
93 | * eventually cause some kind of recovery from the DMA stall. | |
94 | */ | |
95 | return WAIT_MIN_SLEEP; | |
96 | } | |
97 | ||
98 | /* Chain to the restored expiry handler if DMA wasn't active. */ | |
99 | if (likely(expiry != NULL)) | |
100 | return expiry(drive); | |
101 | ||
102 | /* If there was no handler, "emulate" that for ide_timer_expiry()... */ | |
103 | return -1; | |
104 | } | |
105 | ||
106 | static void tc86c001_dma_start(ide_drive_t *drive) | |
107 | { | |
108 | ide_hwif_t *hwif = HWIF(drive); | |
109 | ide_hwgroup_t *hwgroup = HWGROUP(drive); | |
110 | unsigned long sc_base = hwif->config_data; | |
111 | unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04); | |
112 | unsigned long nsectors = hwgroup->rq->nr_sectors; | |
113 | ||
114 | /* | |
115 | * We have to manually load the sector count and size into | |
116 | * the appropriate system control registers for DMA to work | |
117 | * with LBA48 and ATAPI devices... | |
118 | */ | |
0ecdca26 BZ |
119 | outw(nsectors, sc_base + 0x0a); /* Sector Count */ |
120 | outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */ | |
33dced2e SS |
121 | |
122 | /* Install our timeout expiry hook, saving the current handler... */ | |
123 | ide_set_hwifdata(hwif, hwgroup->expiry); | |
124 | hwgroup->expiry = &tc86c001_timer_expiry; | |
125 | ||
126 | ide_dma_start(drive); | |
127 | } | |
128 | ||
bfa14b42 BZ |
129 | static u8 __devinit tc86c001_cable_detect(ide_hwif_t *hwif) |
130 | { | |
131 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
132 | unsigned long sc_base = pci_resource_start(dev, 5); | |
133 | u16 scr1 = inw(sc_base + 0x00); | |
134 | ||
135 | /* | |
136 | * System Control 1 Register bit 13 (PDIAGN): | |
137 | * 0=80-pin cable, 1=40-pin cable | |
138 | */ | |
139 | return (scr1 & 0x2000) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
140 | } | |
141 | ||
e8ab7f53 | 142 | static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif) |
33dced2e | 143 | { |
36501650 BZ |
144 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
145 | unsigned long sc_base = pci_resource_start(dev, 5); | |
31e8a465 | 146 | u16 scr1 = inw(sc_base + 0x00); |
33dced2e SS |
147 | |
148 | /* System Control 1 Register bit 15 (Soft Reset) set */ | |
0ecdca26 | 149 | outw(scr1 | 0x8000, sc_base + 0x00); |
33dced2e SS |
150 | |
151 | /* System Control 1 Register bit 14 (FIFO Reset) set */ | |
0ecdca26 | 152 | outw(scr1 | 0x4000, sc_base + 0x00); |
33dced2e SS |
153 | |
154 | /* System Control 1 Register: reset clear */ | |
0ecdca26 | 155 | outw(scr1 & ~0xc000, sc_base + 0x00); |
33dced2e SS |
156 | |
157 | /* Store the system control register base for convenience... */ | |
158 | hwif->config_data = sc_base; | |
159 | ||
33dced2e SS |
160 | if (!hwif->dma_base) |
161 | return; | |
162 | ||
163 | /* | |
164 | * Sector Count Control Register bits 0 and 1 set: | |
165 | * software sets Sector Count Register for master and slave device | |
166 | */ | |
0ecdca26 | 167 | outw(0x0003, sc_base + 0x0c); |
33dced2e SS |
168 | |
169 | /* Sector Count Register limit */ | |
170 | hwif->rqsize = 0xffff; | |
33dced2e SS |
171 | } |
172 | ||
ba59c4b8 AM |
173 | static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev, |
174 | const char *name) | |
33dced2e SS |
175 | { |
176 | int err = pci_request_region(dev, 5, name); | |
177 | ||
178 | if (err) | |
179 | printk(KERN_ERR "%s: system control regs already in use", name); | |
180 | return err; | |
181 | } | |
182 | ||
ac95beed BZ |
183 | static const struct ide_port_ops tc86c001_port_ops = { |
184 | .set_pio_mode = tc86c001_set_pio_mode, | |
185 | .set_dma_mode = tc86c001_set_mode, | |
186 | .cable_detect = tc86c001_cable_detect, | |
187 | }; | |
188 | ||
f37afdac BZ |
189 | static const struct ide_dma_ops tc86c001_dma_ops = { |
190 | .dma_host_set = ide_dma_host_set, | |
191 | .dma_setup = ide_dma_setup, | |
192 | .dma_exec_cmd = ide_dma_exec_cmd, | |
5e37bdc0 | 193 | .dma_start = tc86c001_dma_start, |
f37afdac BZ |
194 | .dma_end = __ide_dma_end, |
195 | .dma_test_irq = ide_dma_test_irq, | |
196 | .dma_lost_irq = ide_dma_lost_irq, | |
197 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
198 | }; |
199 | ||
85620436 | 200 | static const struct ide_port_info tc86c001_chipset __devinitdata = { |
33dced2e SS |
201 | .name = "TC86C001", |
202 | .init_chipset = init_chipset_tc86c001, | |
203 | .init_hwif = init_hwif_tc86c001, | |
ac95beed | 204 | .port_ops = &tc86c001_port_ops, |
5e37bdc0 | 205 | .dma_ops = &tc86c001_dma_ops, |
4db90a14 BZ |
206 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD | |
207 | IDE_HFLAG_ABUSE_SET_DMA_MODE, | |
4099d143 | 208 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
209 | .mwdma_mask = ATA_MWDMA2, |
210 | .udma_mask = ATA_UDMA4, | |
33dced2e SS |
211 | }; |
212 | ||
213 | static int __devinit tc86c001_init_one(struct pci_dev *dev, | |
214 | const struct pci_device_id *id) | |
215 | { | |
216 | return ide_setup_pci_device(dev, &tc86c001_chipset); | |
217 | } | |
218 | ||
9cbcc5e3 BZ |
219 | static const struct pci_device_id tc86c001_pci_tbl[] = { |
220 | { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE), 0 }, | |
33dced2e SS |
221 | { 0, } |
222 | }; | |
223 | MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl); | |
224 | ||
225 | static struct pci_driver driver = { | |
226 | .name = "TC86C001", | |
227 | .id_table = tc86c001_pci_tbl, | |
228 | .probe = tc86c001_init_one | |
229 | }; | |
230 | ||
a534b68d | 231 | static int __init tc86c001_ide_init(void) |
33dced2e SS |
232 | { |
233 | return ide_pci_register_driver(&driver); | |
234 | } | |
235 | module_init(tc86c001_ide_init); | |
236 | ||
237 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
238 | MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE"); | |
239 | MODULE_LICENSE("GPL"); |