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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (c) 1997-1998 Mark Lord |
93c0b560 | 3 | * Copyright (c) 2007 MontaVista Software, Inc. <source@mvista.com> |
58f189fc | 4 | * |
1da177e4 LT |
5 | * May be copied or modified under the terms of the GNU General Public License |
6 | * | |
7 | * June 22, 2004 - get rid of check_region | |
59904159 | 8 | * - Jesper Juhl |
1da177e4 LT |
9 | * |
10 | */ | |
11 | ||
12 | /* | |
13 | * This module provides support for the bus-master IDE DMA function | |
14 | * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards, | |
15 | * including a "Precision Instruments" board. The TRM290 pre-dates | |
16 | * the sff-8038 standard (ide-dma.c) by a few months, and differs | |
17 | * significantly enough to warrant separate routines for some functions, | |
18 | * while re-using others from ide-dma.c. | |
19 | * | |
20 | * EXPERIMENTAL! It works for me (a sample of one). | |
21 | * | |
22 | * Works reliably for me in DMA mode (READs only), | |
23 | * DMA WRITEs are disabled by default (see #define below); | |
24 | * | |
25 | * DMA is not enabled automatically for this chipset, | |
26 | * but can be turned on manually (with "hdparm -d1") at run time. | |
27 | * | |
28 | * I need volunteers with "spare" drives for further testing | |
29 | * and development, and maybe to help figure out the peculiarities. | |
30 | * Even knowing the registers (below), some things behave strangely. | |
31 | */ | |
32 | ||
33 | #define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */ | |
34 | ||
35 | /* | |
36 | * TRM-290 PCI-IDE2 Bus Master Chip | |
37 | * ================================ | |
38 | * The configuration registers are addressed in normal I/O port space | |
39 | * and are used as follows: | |
40 | * | |
41 | * trm290_base depends on jumper settings, and is probed for by ide-dma.c | |
42 | * | |
43 | * trm290_base+2 when WRITTEN: chiptest register (byte, write-only) | |
44 | * bit7 must always be written as "1" | |
45 | * bits6-2 undefined | |
46 | * bit1 1=legacy_compatible_mode, 0=native_pci_mode | |
47 | * bit0 1=test_mode, 0=normal(default) | |
48 | * | |
49 | * trm290_base+2 when READ: status register (byte, read-only) | |
50 | * bits7-2 undefined | |
51 | * bit1 channel0 busmaster interrupt status 0=none, 1=asserted | |
52 | * bit0 channel0 interrupt status 0=none, 1=asserted | |
53 | * | |
54 | * trm290_base+3 Interrupt mask register | |
55 | * bits7-5 undefined | |
56 | * bit4 legacy_header: 1=present, 0=absent | |
57 | * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only) | |
58 | * bit2 channel1 interrupt status 0=none, 1=asserted (read only) | |
59 | * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default) | |
60 | * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default) | |
61 | * | |
62 | * trm290_base+1 "CPR" Config Pointer Register (byte) | |
63 | * bit7 1=autoincrement CPR bits 2-0 after each access of CDR | |
64 | * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state | |
65 | * bit5 0=enabled master burst access (default), 1=disable (write only) | |
66 | * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast | |
67 | * bit3 0=primary IDE channel, 1=secondary IDE channel | |
68 | * bits2-0 register index for accesses through CDR port | |
69 | * | |
70 | * trm290_base+0 "CDR" Config Data Register (word) | |
71 | * two sets of seven config registers, | |
72 | * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6), | |
73 | * each index defined below: | |
74 | * | |
75 | * Index-0 Base address register for command block (word) | |
76 | * defaults: 0x1f0 for primary, 0x170 for secondary | |
77 | * | |
78 | * Index-1 general config register (byte) | |
79 | * bit7 1=DMA enable, 0=DMA disable | |
80 | * bit6 1=activate IDE_RESET, 0=no action (default) | |
81 | * bit5 1=enable IORDY, 0=disable IORDY (default) | |
82 | * bit4 0=16-bit data port(default), 1=8-bit (XT) data port | |
83 | * bit3 interrupt polarity: 1=active_low, 0=active_high(default) | |
84 | * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only) | |
85 | * bit1 bus_master_mode(?): 1=enable, 0=disable(default) | |
86 | * bit0 enable_io_ports: 1=enable(default), 0=disable | |
87 | * | |
88 | * Index-2 read-ahead counter preload bits 0-7 (byte, write only) | |
89 | * bits7-0 bits7-0 of readahead count | |
90 | * | |
91 | * Index-3 read-ahead config register (byte, write only) | |
92 | * bit7 1=enable_readahead, 0=disable_readahead(default) | |
93 | * bit6 1=clear_FIFO, 0=no_action | |
94 | * bit5 undefined | |
95 | * bit4 mode4 timing control: 1=enable, 0=disable(default) | |
96 | * bit3 undefined | |
97 | * bit2 undefined | |
98 | * bits1-0 bits9-8 of read-ahead count | |
99 | * | |
100 | * Index-4 base address register for control block (word) | |
101 | * defaults: 0x3f6 for primary, 0x376 for secondary | |
102 | * | |
103 | * Index-5 data port timings (shared by both drives) (byte) | |
104 | * standard PCI "clk" (clock) counts, default value = 0xf5 | |
105 | * | |
106 | * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk | |
107 | * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk, | |
108 | * 011=4clk, 100=5clk, 101=6clk, | |
109 | * 110=8clk, 111=12clk | |
110 | * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk, | |
111 | * 011=5clk, 100=6clk, 101=8clk, | |
112 | * 110=12clk, 111=16clk | |
113 | * | |
114 | * Index-6 command/control port timings (shared by both drives) (byte) | |
115 | * same layout as Index-5, default value = 0xde | |
116 | * | |
117 | * Suggested CDR programming for PIO mode0 (600ns): | |
118 | * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary | |
119 | * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary | |
120 | * | |
121 | * Suggested CDR programming for PIO mode3 (180ns): | |
122 | * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary | |
123 | * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary | |
124 | * | |
125 | * Suggested CDR programming for PIO mode4 (120ns): | |
126 | * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary | |
127 | * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary | |
128 | * | |
129 | */ | |
130 | ||
1da177e4 LT |
131 | #include <linux/types.h> |
132 | #include <linux/module.h> | |
133 | #include <linux/kernel.h> | |
1da177e4 LT |
134 | #include <linux/ioport.h> |
135 | #include <linux/interrupt.h> | |
136 | #include <linux/blkdev.h> | |
137 | #include <linux/init.h> | |
138 | #include <linux/hdreg.h> | |
139 | #include <linux/pci.h> | |
1da177e4 LT |
140 | #include <linux/ide.h> |
141 | ||
142 | #include <asm/io.h> | |
143 | ||
144 | static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma) | |
145 | { | |
146 | ide_hwif_t *hwif = HWIF(drive); | |
147 | u16 reg = 0; | |
148 | unsigned long flags; | |
149 | ||
150 | /* select PIO or DMA */ | |
151 | reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82); | |
152 | ||
153 | local_irq_save(flags); | |
154 | ||
155 | if (reg != hwif->select_data) { | |
156 | hwif->select_data = reg; | |
157 | /* set PIO/DMA */ | |
0ecdca26 BZ |
158 | outb(0x51 | (hwif->channel << 3), hwif->config_data + 1); |
159 | outw(reg & 0xff, hwif->config_data); | |
1da177e4 LT |
160 | } |
161 | ||
162 | /* enable IRQ if not probing */ | |
163 | if (drive->present) { | |
0ecdca26 | 164 | reg = inw(hwif->config_data + 3); |
1da177e4 LT |
165 | reg &= 0x13; |
166 | reg &= ~(1 << hwif->channel); | |
0ecdca26 | 167 | outw(reg, hwif->config_data + 3); |
1da177e4 LT |
168 | } |
169 | ||
170 | local_irq_restore(flags); | |
171 | } | |
172 | ||
173 | static void trm290_selectproc (ide_drive_t *drive) | |
174 | { | |
175 | trm290_prepare_drive(drive, drive->using_dma); | |
176 | } | |
177 | ||
93c0b560 | 178 | static void trm290_dma_exec_cmd(ide_drive_t *drive, u8 command) |
1da177e4 | 179 | { |
125e1874 | 180 | BUG_ON(HWGROUP(drive)->handler != NULL); /* paranoia check */ |
1da177e4 LT |
181 | ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL); |
182 | /* issue cmd to drive */ | |
0ecdca26 | 183 | outb(command, IDE_COMMAND_REG); |
1da177e4 LT |
184 | } |
185 | ||
93c0b560 | 186 | static int trm290_dma_setup(ide_drive_t *drive) |
1da177e4 LT |
187 | { |
188 | ide_hwif_t *hwif = drive->hwif; | |
189 | struct request *rq = hwif->hwgroup->rq; | |
190 | unsigned int count, rw; | |
191 | ||
192 | if (rq_data_dir(rq)) { | |
193 | #ifdef TRM290_NO_DMA_WRITES | |
194 | /* always use PIO for writes */ | |
195 | trm290_prepare_drive(drive, 0); /* select PIO xfer */ | |
196 | return 1; | |
197 | #endif | |
198 | rw = 1; | |
199 | } else | |
200 | rw = 2; | |
201 | ||
202 | if (!(count = ide_build_dmatable(drive, rq))) { | |
203 | /* try PIO instead of DMA */ | |
204 | trm290_prepare_drive(drive, 0); /* select PIO xfer */ | |
205 | return 1; | |
206 | } | |
207 | /* select DMA xfer */ | |
208 | trm290_prepare_drive(drive, 1); | |
4e5a68ae | 209 | outl(hwif->dmatable_dma | rw, hwif->dma_base); |
1da177e4 LT |
210 | drive->waiting_for_dma = 1; |
211 | /* start DMA */ | |
4e5a68ae | 212 | outw(count * 2 - 1, hwif->dma_base + 2); |
1da177e4 LT |
213 | return 0; |
214 | } | |
215 | ||
93c0b560 | 216 | static void trm290_dma_start(ide_drive_t *drive) |
1da177e4 LT |
217 | { |
218 | } | |
219 | ||
220 | static int trm290_ide_dma_end (ide_drive_t *drive) | |
221 | { | |
4e5a68ae | 222 | u16 status; |
1da177e4 LT |
223 | |
224 | drive->waiting_for_dma = 0; | |
225 | /* purge DMA mappings */ | |
226 | ide_destroy_dmatable(drive); | |
4e5a68ae SS |
227 | status = inw(HWIF(drive)->dma_base + 2); |
228 | return status != 0x00ff; | |
1da177e4 LT |
229 | } |
230 | ||
231 | static int trm290_ide_dma_test_irq (ide_drive_t *drive) | |
232 | { | |
4e5a68ae | 233 | u16 status; |
1da177e4 | 234 | |
4e5a68ae SS |
235 | status = inw(HWIF(drive)->dma_base + 2); |
236 | return status == 0x00ff; | |
1da177e4 | 237 | } |
1da177e4 | 238 | |
15ce926a | 239 | static void trm290_dma_host_set(ide_drive_t *drive, int on) |
93c0b560 SS |
240 | { |
241 | } | |
242 | ||
1da177e4 LT |
243 | static void __devinit init_hwif_trm290(ide_hwif_t *hwif) |
244 | { | |
36501650 | 245 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4e5a68ae | 246 | unsigned int cfg_base = pci_resource_start(dev, 4); |
1da177e4 LT |
247 | unsigned long flags; |
248 | u8 reg = 0; | |
1da177e4 | 249 | |
4e5a68ae SS |
250 | if ((dev->class & 5) && cfg_base) |
251 | printk(KERN_INFO "TRM290: chip"); | |
252 | else { | |
253 | cfg_base = 0x3df0; | |
254 | printk(KERN_INFO "TRM290: using default"); | |
255 | } | |
256 | printk(KERN_CONT " config base at 0x%04x\n", cfg_base); | |
257 | hwif->config_data = cfg_base; | |
258 | hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0); | |
259 | ||
260 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", | |
261 | hwif->name, hwif->dma_base, hwif->dma_base + 3); | |
262 | ||
263 | if (!request_region(hwif->dma_base, 4, hwif->name)) { | |
264 | printk(KERN_CONT " -- Error, ports in use.\n"); | |
265 | return; | |
266 | } | |
267 | ||
268 | hwif->dmatable_cpu = pci_alloc_consistent(dev, PRD_ENTRIES * PRD_BYTES, | |
269 | &hwif->dmatable_dma); | |
270 | if (!hwif->dmatable_cpu) { | |
271 | printk(KERN_CONT " -- Error, unable to allocate DMA table.\n"); | |
272 | release_region(hwif->dma_base, 4); | |
273 | return; | |
1da177e4 | 274 | } |
4e5a68ae | 275 | printk(KERN_CONT "\n"); |
1da177e4 LT |
276 | |
277 | local_irq_save(flags); | |
278 | /* put config reg into first byte of hwif->select_data */ | |
0ecdca26 | 279 | outb(0x51 | (hwif->channel << 3), hwif->config_data + 1); |
1da177e4 LT |
280 | /* select PIO as default */ |
281 | hwif->select_data = 0x21; | |
0ecdca26 | 282 | outb(hwif->select_data, hwif->config_data); |
1da177e4 | 283 | /* get IRQ info */ |
0ecdca26 | 284 | reg = inb(hwif->config_data + 3); |
1da177e4 LT |
285 | /* mask IRQs for both ports */ |
286 | reg = (reg & 0x10) | 0x03; | |
0ecdca26 | 287 | outb(reg, hwif->config_data + 3); |
1da177e4 LT |
288 | local_irq_restore(flags); |
289 | ||
4e5a68ae | 290 | if (reg & 0x10) |
1da177e4 LT |
291 | /* legacy mode */ |
292 | hwif->irq = hwif->channel ? 15 : 14; | |
293 | else if (!hwif->irq && hwif->mate && hwif->mate->irq) | |
294 | /* sharing IRQ with mate */ | |
295 | hwif->irq = hwif->mate->irq; | |
296 | ||
15ce926a | 297 | hwif->dma_host_set = &trm290_dma_host_set; |
93c0b560 SS |
298 | hwif->dma_setup = &trm290_dma_setup; |
299 | hwif->dma_exec_cmd = &trm290_dma_exec_cmd; | |
300 | hwif->dma_start = &trm290_dma_start; | |
301 | hwif->ide_dma_end = &trm290_ide_dma_end; | |
302 | hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq; | |
1da177e4 LT |
303 | |
304 | hwif->selectproc = &trm290_selectproc; | |
1da177e4 LT |
305 | #if 1 |
306 | { | |
307 | /* | |
308 | * My trm290-based card doesn't seem to work with all possible values | |
309 | * for the control basereg, so this kludge ensures that we use only | |
310 | * values that are known to work. Ugh. -ml | |
311 | */ | |
312 | u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4; | |
313 | static u16 next_offset = 0; | |
314 | u8 old_mask; | |
315 | ||
0ecdca26 BZ |
316 | outb(0x54 | (hwif->channel << 3), hwif->config_data + 1); |
317 | old = inw(hwif->config_data); | |
1da177e4 | 318 | old &= ~1; |
0ecdca26 | 319 | old_mask = inb(old + 2); |
1da177e4 LT |
320 | if (old != compat && old_mask == 0xff) { |
321 | /* leave lower 10 bits untouched */ | |
322 | compat += (next_offset += 0x400); | |
323 | hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2; | |
0ecdca26 BZ |
324 | outw(compat | 1, hwif->config_data); |
325 | new = inw(hwif->config_data); | |
1da177e4 LT |
326 | printk(KERN_INFO "%s: control basereg workaround: " |
327 | "old=0x%04x, new=0x%04x\n", | |
328 | hwif->name, old, new & ~1); | |
329 | } | |
330 | } | |
331 | #endif | |
332 | } | |
333 | ||
85620436 | 334 | static const struct ide_port_info trm290_chipset __devinitdata = { |
1da177e4 LT |
335 | .name = "TRM290", |
336 | .init_hwif = init_hwif_trm290, | |
528a572d | 337 | .chipset = ide_trm290, |
7cab14a7 | 338 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | |
9ff6f72f | 339 | #if 0 /* play it safe for now */ |
7cab14a7 | 340 | IDE_HFLAG_TRUST_BIOS_FOR_DMA | |
9ff6f72f | 341 | #endif |
47b68788 | 342 | IDE_HFLAG_NO_AUTODMA | |
238e4f14 BZ |
343 | IDE_HFLAG_BOOTABLE | |
344 | IDE_HFLAG_NO_LBA48, | |
1da177e4 LT |
345 | }; |
346 | ||
347 | static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
348 | { | |
349 | return ide_setup_pci_device(dev, &trm290_chipset); | |
350 | } | |
351 | ||
9cbcc5e3 BZ |
352 | static const struct pci_device_id trm290_pci_tbl[] = { |
353 | { PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 }, | |
1da177e4 LT |
354 | { 0, }, |
355 | }; | |
356 | MODULE_DEVICE_TABLE(pci, trm290_pci_tbl); | |
357 | ||
358 | static struct pci_driver driver = { | |
359 | .name = "TRM290_IDE", | |
360 | .id_table = trm290_pci_tbl, | |
361 | .probe = trm290_init_one, | |
362 | }; | |
363 | ||
82ab1eec | 364 | static int __init trm290_ide_init(void) |
1da177e4 LT |
365 | { |
366 | return ide_pci_register_driver(&driver); | |
367 | } | |
368 | ||
369 | module_init(trm290_ide_init); | |
370 | ||
371 | MODULE_AUTHOR("Mark Lord"); | |
372 | MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE"); | |
373 | MODULE_LICENSE("GPL"); |