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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Version 3.38 | |
4 | * | |
5 | * VIA IDE driver for Linux. Supported southbridges: | |
6 | * | |
7 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
8 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
9 | * vt8235, vt8237 | |
10 | * | |
11 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
12 | * | |
13 | * Based on the work of: | |
14 | * Michel Aubry | |
15 | * Jeff Garzik | |
16 | * Andre Hedrick | |
17 | * | |
18 | * Documentation: | |
19 | * Obsolete device documentation publically available from via.com.tw | |
20 | * Current device documentation available under NDA only | |
21 | */ | |
22 | ||
23 | /* | |
24 | * This program is free software; you can redistribute it and/or modify it | |
25 | * under the terms of the GNU General Public License version 2 as published by | |
26 | * the Free Software Foundation. | |
27 | */ | |
28 | ||
29 | #include <linux/config.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/blkdev.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/ide.h> | |
37 | #include <asm/io.h> | |
38 | ||
39 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
40 | #include <asm/processor.h> | |
41 | #endif | |
42 | ||
43 | #include "ide-timing.h" | |
44 | ||
45 | #define DISPLAY_VIA_TIMINGS | |
46 | ||
47 | #define VIA_IDE_ENABLE 0x40 | |
48 | #define VIA_IDE_CONFIG 0x41 | |
49 | #define VIA_FIFO_CONFIG 0x43 | |
50 | #define VIA_MISC_1 0x44 | |
51 | #define VIA_MISC_2 0x45 | |
52 | #define VIA_MISC_3 0x46 | |
53 | #define VIA_DRIVE_TIMING 0x48 | |
54 | #define VIA_8BIT_TIMING 0x4e | |
55 | #define VIA_ADDRESS_SETUP 0x4c | |
56 | #define VIA_UDMA_TIMING 0x50 | |
57 | ||
58 | #define VIA_UDMA 0x007 | |
59 | #define VIA_UDMA_NONE 0x000 | |
60 | #define VIA_UDMA_33 0x001 | |
61 | #define VIA_UDMA_66 0x002 | |
62 | #define VIA_UDMA_100 0x003 | |
63 | #define VIA_UDMA_133 0x004 | |
64 | #define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */ | |
65 | #define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */ | |
66 | #define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */ | |
67 | #define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */ | |
68 | #define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */ | |
69 | #define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */ | |
70 | ||
71 | /* | |
72 | * VIA SouthBridge chips. | |
73 | */ | |
74 | ||
75 | static struct via_isa_bridge { | |
76 | char *name; | |
77 | u16 id; | |
78 | u8 rev_min; | |
79 | u8 rev_max; | |
80 | u16 flags; | |
81 | } via_isa_bridges[] = { | |
82 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
83 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
84 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
85 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, | |
86 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, | |
87 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, | |
88 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, | |
89 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, | |
90 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, | |
91 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, | |
92 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, | |
93 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
94 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, | |
95 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
96 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
97 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, | |
98 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, | |
99 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
100 | { NULL } | |
101 | }; | |
102 | ||
103 | static struct via_isa_bridge *via_config; | |
104 | static unsigned int via_80w; | |
105 | static unsigned int via_clock; | |
106 | static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" }; | |
107 | ||
108 | /* | |
109 | * VIA /proc entry. | |
110 | */ | |
111 | ||
112 | #if defined(DISPLAY_VIA_TIMINGS) && defined(CONFIG_PROC_FS) | |
113 | ||
114 | #include <linux/stat.h> | |
115 | #include <linux/proc_fs.h> | |
116 | ||
117 | static u8 via_proc = 0; | |
118 | static unsigned long via_base; | |
119 | static struct pci_dev *bmide_dev, *isa_dev; | |
120 | ||
121 | static char *via_control3[] = { "No limit", "64", "128", "192" }; | |
122 | ||
123 | #define via_print(format, arg...) p += sprintf(p, format "\n" , ## arg) | |
124 | #define via_print_drive(name, format, arg...)\ | |
125 | p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n"); | |
126 | ||
127 | ||
128 | /** | |
129 | * via_get_info - generate via /proc file | |
130 | * @buffer: buffer for data | |
131 | * @addr: set to start of data to use | |
132 | * @offset: current file offset | |
133 | * @count: size of read | |
134 | * | |
135 | * Fills in buffer with the debugging/configuration information for | |
136 | * the VIA chipset tuning and attached drives | |
137 | */ | |
138 | ||
139 | static int via_get_info(char *buffer, char **addr, off_t offset, int count) | |
140 | { | |
141 | int speed[4], cycle[4], setup[4], active[4], recover[4], den[4], | |
142 | uen[4], udma[4], umul[4], active8b[4], recover8b[4]; | |
143 | struct pci_dev *dev = bmide_dev; | |
144 | unsigned int v, u, i; | |
145 | int len; | |
146 | u16 c, w; | |
147 | u8 t, x; | |
148 | char *p = buffer; | |
149 | ||
150 | via_print("----------VIA BusMastering IDE Configuration" | |
151 | "----------------"); | |
152 | ||
153 | via_print("Driver Version: 3.38"); | |
154 | via_print("South Bridge: VIA %s", | |
155 | via_config->name); | |
156 | ||
157 | pci_read_config_byte(isa_dev, PCI_REVISION_ID, &t); | |
158 | pci_read_config_byte(dev, PCI_REVISION_ID, &x); | |
159 | via_print("Revision: ISA %#x IDE %#x", t, x); | |
160 | via_print("Highest DMA rate: %s", | |
161 | via_dma[via_config->flags & VIA_UDMA]); | |
162 | ||
163 | via_print("BM-DMA base: %#lx", via_base); | |
164 | via_print("PCI clock: %d.%dMHz", | |
165 | via_clock / 1000, via_clock / 100 % 10); | |
166 | ||
167 | pci_read_config_byte(dev, VIA_MISC_1, &t); | |
168 | via_print("Master Read Cycle IRDY: %dws", | |
169 | (t & 64) >> 6); | |
170 | via_print("Master Write Cycle IRDY: %dws", | |
171 | (t & 32) >> 5); | |
172 | via_print("BM IDE Status Register Read Retry: %s", | |
173 | (t & 8) ? "yes" : "no"); | |
174 | ||
175 | pci_read_config_byte(dev, VIA_MISC_3, &t); | |
176 | via_print("Max DRDY Pulse Width: %s%s", | |
177 | via_control3[(t & 0x03)], (t & 0x03) ? " PCI clocks" : ""); | |
178 | ||
179 | via_print("-----------------------Primary IDE" | |
180 | "-------Secondary IDE------"); | |
181 | via_print("Read DMA FIFO flush: %10s%20s", | |
182 | (t & 0x80) ? "yes" : "no", (t & 0x40) ? "yes" : "no"); | |
183 | via_print("End Sector FIFO flush: %10s%20s", | |
184 | (t & 0x20) ? "yes" : "no", (t & 0x10) ? "yes" : "no"); | |
185 | ||
186 | pci_read_config_byte(dev, VIA_IDE_CONFIG, &t); | |
187 | via_print("Prefetch Buffer: %10s%20s", | |
188 | (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no"); | |
189 | via_print("Post Write Buffer: %10s%20s", | |
190 | (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no"); | |
191 | ||
192 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &t); | |
193 | via_print("Enabled: %10s%20s", | |
194 | (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no"); | |
195 | ||
196 | c = inb(via_base + 0x02) | (inb(via_base + 0x0a) << 8); | |
197 | via_print("Simplex only: %10s%20s", | |
198 | (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no"); | |
199 | ||
200 | via_print("Cable Type: %10s%20s", | |
201 | (via_80w & 1) ? "80w" : "40w", (via_80w & 2) ? "80w" : "40w"); | |
202 | ||
203 | via_print("-------------------drive0----drive1" | |
204 | "----drive2----drive3-----"); | |
205 | ||
206 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); | |
207 | pci_read_config_dword(dev, VIA_DRIVE_TIMING, &v); | |
208 | pci_read_config_word(dev, VIA_8BIT_TIMING, &w); | |
209 | ||
210 | if (via_config->flags & VIA_UDMA) | |
211 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); | |
212 | else u = 0; | |
213 | ||
214 | for (i = 0; i < 4; i++) { | |
215 | ||
216 | setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1; | |
217 | recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1; | |
218 | active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1; | |
219 | active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1; | |
220 | recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1; | |
221 | udma[i] = ((u >> ((3 - i) << 3)) & 0x7) + 2; | |
222 | umul[i] = ((u >> (((3 - i) & 2) << 3)) & 0x8) ? 1 : 2; | |
223 | uen[i] = ((u >> ((3 - i) << 3)) & 0x20); | |
224 | den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2)); | |
225 | ||
226 | speed[i] = 2 * via_clock / (active[i] + recover[i]); | |
227 | cycle[i] = 1000000 * (active[i] + recover[i]) / via_clock; | |
228 | ||
229 | if (!uen[i] || !den[i]) | |
230 | continue; | |
231 | ||
232 | switch (via_config->flags & VIA_UDMA) { | |
233 | ||
234 | case VIA_UDMA_33: | |
235 | speed[i] = 2 * via_clock / udma[i]; | |
236 | cycle[i] = 1000000 * udma[i] / via_clock; | |
237 | break; | |
238 | ||
239 | case VIA_UDMA_66: | |
240 | speed[i] = 4 * via_clock / (udma[i] * umul[i]); | |
241 | cycle[i] = 500000 * (udma[i] * umul[i]) / via_clock; | |
242 | break; | |
243 | ||
244 | case VIA_UDMA_100: | |
245 | speed[i] = 6 * via_clock / udma[i]; | |
246 | cycle[i] = 333333 * udma[i] / via_clock; | |
247 | break; | |
248 | ||
249 | case VIA_UDMA_133: | |
250 | speed[i] = 8 * via_clock / udma[i]; | |
251 | cycle[i] = 250000 * udma[i] / via_clock; | |
252 | break; | |
253 | } | |
254 | } | |
255 | ||
256 | via_print_drive("Transfer Mode: ", "%10s", | |
257 | den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO"); | |
258 | ||
259 | via_print_drive("Address Setup: ", "%8dns", | |
260 | 1000000 * setup[i] / via_clock); | |
261 | via_print_drive("Cmd Active: ", "%8dns", | |
262 | 1000000 * active8b[i] / via_clock); | |
263 | via_print_drive("Cmd Recovery: ", "%8dns", | |
264 | 1000000 * recover8b[i] / via_clock); | |
265 | via_print_drive("Data Active: ", "%8dns", | |
266 | 1000000 * active[i] / via_clock); | |
267 | via_print_drive("Data Recovery: ", "%8dns", | |
268 | 1000000 * recover[i] / via_clock); | |
269 | via_print_drive("Cycle Time: ", "%8dns", | |
270 | cycle[i]); | |
271 | via_print_drive("Transfer Rate: ", "%4d.%dMB/s", | |
272 | speed[i] / 1000, speed[i] / 100 % 10); | |
273 | ||
274 | /* hoping it is less than 4K... */ | |
275 | len = (p - buffer) - offset; | |
276 | *addr = buffer + offset; | |
277 | ||
278 | return len > count ? count : len; | |
279 | } | |
280 | ||
281 | #endif /* DISPLAY_VIA_TIMINGS && CONFIG_PROC_FS */ | |
282 | ||
283 | /** | |
284 | * via_set_speed - write timing registers | |
285 | * @dev: PCI device | |
286 | * @dn: device | |
287 | * @timing: IDE timing data to use | |
288 | * | |
289 | * via_set_speed writes timing values to the chipset registers | |
290 | */ | |
291 | ||
292 | static void via_set_speed(struct pci_dev *dev, u8 dn, struct ide_timing *timing) | |
293 | { | |
294 | u8 t; | |
295 | ||
296 | if (~via_config->flags & VIA_BAD_AST) { | |
297 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); | |
298 | t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); | |
299 | pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); | |
300 | } | |
301 | ||
302 | pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), | |
303 | ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1)); | |
304 | ||
305 | pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), | |
306 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); | |
307 | ||
308 | switch (via_config->flags & VIA_UDMA) { | |
309 | case VIA_UDMA_33: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; | |
310 | case VIA_UDMA_66: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break; | |
311 | case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
312 | case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break; | |
313 | default: return; | |
314 | } | |
315 | ||
316 | pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); | |
317 | } | |
318 | ||
319 | /** | |
320 | * via_set_drive - configure transfer mode | |
321 | * @drive: Drive to set up | |
322 | * @speed: desired speed | |
323 | * | |
324 | * via_set_drive() computes timing values configures the drive and | |
325 | * the chipset to a desired transfer mode. It also can be called | |
326 | * by upper layers. | |
327 | */ | |
328 | ||
329 | static int via_set_drive(ide_drive_t *drive, u8 speed) | |
330 | { | |
331 | ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1); | |
332 | struct ide_timing t, p; | |
333 | unsigned int T, UT; | |
334 | ||
335 | if (speed != XFER_PIO_SLOW) | |
336 | ide_config_drive_speed(drive, speed); | |
337 | ||
338 | T = 1000000000 / via_clock; | |
339 | ||
340 | switch (via_config->flags & VIA_UDMA) { | |
341 | case VIA_UDMA_33: UT = T; break; | |
342 | case VIA_UDMA_66: UT = T/2; break; | |
343 | case VIA_UDMA_100: UT = T/3; break; | |
344 | case VIA_UDMA_133: UT = T/4; break; | |
345 | default: UT = T; | |
346 | } | |
347 | ||
348 | ide_timing_compute(drive, speed, &t, T, UT); | |
349 | ||
350 | if (peer->present) { | |
351 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); | |
352 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
353 | } | |
354 | ||
355 | via_set_speed(HWIF(drive)->pci_dev, drive->dn, &t); | |
356 | ||
357 | if (!drive->init_speed) | |
358 | drive->init_speed = speed; | |
359 | drive->current_speed = speed; | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
364 | /** | |
365 | * via82cxxx_tune_drive - PIO setup | |
366 | * @drive: drive to set up | |
367 | * @pio: mode to use (255 for 'best possible') | |
368 | * | |
369 | * A callback from the upper layers for PIO-only tuning. | |
370 | */ | |
371 | ||
372 | static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio) | |
373 | { | |
374 | if (pio == 255) { | |
375 | via_set_drive(drive, | |
376 | ide_find_best_mode(drive, XFER_PIO | XFER_EPIO)); | |
377 | return; | |
378 | } | |
379 | ||
380 | via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5)); | |
381 | } | |
382 | ||
383 | /** | |
384 | * via82cxxx_ide_dma_check - set up for DMA if possible | |
385 | * @drive: IDE drive to set up | |
386 | * | |
387 | * Set up the drive for the highest supported speed considering the | |
388 | * driver, controller and cable | |
389 | */ | |
390 | ||
391 | static int via82cxxx_ide_dma_check (ide_drive_t *drive) | |
392 | { | |
393 | u16 w80 = HWIF(drive)->udma_four; | |
394 | ||
395 | u16 speed = ide_find_best_mode(drive, | |
396 | XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA | | |
397 | (via_config->flags & VIA_UDMA ? XFER_UDMA : 0) | | |
398 | (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) | | |
399 | (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) | | |
400 | (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0)); | |
401 | ||
402 | via_set_drive(drive, speed); | |
403 | ||
404 | if (drive->autodma && (speed & XFER_MODE) != XFER_PIO) | |
405 | return HWIF(drive)->ide_dma_on(drive); | |
406 | return HWIF(drive)->ide_dma_off_quietly(drive); | |
407 | } | |
408 | ||
409 | /** | |
410 | * init_chipset_via82cxxx - initialization handler | |
411 | * @dev: PCI device | |
412 | * @name: Name of interface | |
413 | * | |
414 | * The initialization callback. Here we determine the IDE chip type | |
415 | * and initialize its drive independent registers. | |
416 | */ | |
417 | ||
418 | static unsigned int __init init_chipset_via82cxxx(struct pci_dev *dev, const char *name) | |
419 | { | |
420 | struct pci_dev *isa = NULL; | |
421 | u8 t, v; | |
422 | unsigned int u; | |
423 | int i; | |
424 | ||
425 | /* | |
426 | * Find the ISA bridge to see how good the IDE is. | |
427 | */ | |
428 | ||
429 | for (via_config = via_isa_bridges; via_config->id; via_config++) | |
430 | if ((isa = pci_find_device(PCI_VENDOR_ID_VIA + | |
431 | !!(via_config->flags & VIA_BAD_ID), | |
432 | via_config->id, NULL))) { | |
433 | ||
434 | pci_read_config_byte(isa, PCI_REVISION_ID, &t); | |
435 | if (t >= via_config->rev_min && | |
436 | t <= via_config->rev_max) | |
437 | break; | |
438 | } | |
439 | ||
440 | if (!via_config->id) { | |
441 | printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n"); | |
442 | return -ENODEV; | |
443 | } | |
444 | ||
445 | /* | |
446 | * Check 80-wire cable presence and setup Clk66. | |
447 | */ | |
448 | ||
449 | switch (via_config->flags & VIA_UDMA) { | |
450 | ||
451 | case VIA_UDMA_66: | |
452 | /* Enable Clk66 */ | |
453 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); | |
454 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); | |
455 | for (i = 24; i >= 0; i -= 8) | |
456 | if (((u >> (i & 16)) & 8) && | |
457 | ((u >> i) & 0x20) && | |
458 | (((u >> i) & 7) < 2)) { | |
459 | /* | |
460 | * 2x PCI clock and | |
461 | * UDMA w/ < 3T/cycle | |
462 | */ | |
463 | via_80w |= (1 << (1 - (i >> 4))); | |
464 | } | |
465 | break; | |
466 | ||
467 | case VIA_UDMA_100: | |
468 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); | |
469 | for (i = 24; i >= 0; i -= 8) | |
470 | if (((u >> i) & 0x10) || | |
471 | (((u >> i) & 0x20) && | |
472 | (((u >> i) & 7) < 4))) { | |
473 | /* BIOS 80-wire bit or | |
474 | * UDMA w/ < 60ns/cycle | |
475 | */ | |
476 | via_80w |= (1 << (1 - (i >> 4))); | |
477 | } | |
478 | break; | |
479 | ||
480 | case VIA_UDMA_133: | |
481 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); | |
482 | for (i = 24; i >= 0; i -= 8) | |
483 | if (((u >> i) & 0x10) || | |
484 | (((u >> i) & 0x20) && | |
485 | (((u >> i) & 7) < 6))) { | |
486 | /* BIOS 80-wire bit or | |
487 | * UDMA w/ < 60ns/cycle | |
488 | */ | |
489 | via_80w |= (1 << (1 - (i >> 4))); | |
490 | } | |
491 | break; | |
492 | ||
493 | } | |
494 | ||
495 | /* Disable Clk66 */ | |
496 | if (via_config->flags & VIA_BAD_CLK66) { | |
497 | /* Would cause trouble on 596a and 686 */ | |
498 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); | |
499 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); | |
500 | } | |
501 | ||
502 | /* | |
503 | * Check whether interfaces are enabled. | |
504 | */ | |
505 | ||
506 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); | |
507 | ||
508 | /* | |
509 | * Set up FIFO sizes and thresholds. | |
510 | */ | |
511 | ||
512 | pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); | |
513 | ||
514 | /* Disable PREQ# till DDACK# */ | |
515 | if (via_config->flags & VIA_BAD_PREQ) { | |
516 | /* Would crash on 586b rev 41 */ | |
517 | t &= 0x7f; | |
518 | } | |
519 | ||
520 | /* Fix FIFO split between channels */ | |
521 | if (via_config->flags & VIA_SET_FIFO) { | |
522 | t &= (t & 0x9f); | |
523 | switch (v & 3) { | |
524 | case 2: t |= 0x00; break; /* 16 on primary */ | |
525 | case 1: t |= 0x60; break; /* 16 on secondary */ | |
526 | case 3: t |= 0x20; break; /* 8 pri 8 sec */ | |
527 | } | |
528 | } | |
529 | ||
530 | pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); | |
531 | ||
532 | /* | |
533 | * Determine system bus clock. | |
534 | */ | |
535 | ||
536 | via_clock = system_bus_clock() * 1000; | |
537 | ||
538 | switch (via_clock) { | |
539 | case 33000: via_clock = 33333; break; | |
540 | case 37000: via_clock = 37500; break; | |
541 | case 41000: via_clock = 41666; break; | |
542 | } | |
543 | ||
544 | if (via_clock < 20000 || via_clock > 50000) { | |
545 | printk(KERN_WARNING "VP_IDE: User given PCI clock speed " | |
546 | "impossible (%d), using 33 MHz instead.\n", via_clock); | |
547 | printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want " | |
548 | "to assume 80-wire cable.\n"); | |
549 | via_clock = 33333; | |
550 | } | |
551 | ||
552 | /* | |
553 | * Print the boot message. | |
554 | */ | |
555 | ||
556 | pci_read_config_byte(isa, PCI_REVISION_ID, &t); | |
557 | printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s " | |
558 | "controller on pci%s\n", | |
559 | via_config->name, t, | |
560 | via_dma[via_config->flags & VIA_UDMA], | |
561 | pci_name(dev)); | |
562 | ||
563 | /* | |
564 | * Setup /proc/ide/via entry. | |
565 | */ | |
566 | ||
567 | #if defined(DISPLAY_VIA_TIMINGS) && defined(CONFIG_PROC_FS) | |
568 | if (!via_proc) { | |
569 | via_base = pci_resource_start(dev, 4); | |
570 | bmide_dev = dev; | |
571 | isa_dev = isa; | |
572 | ide_pci_create_host_proc("via", via_get_info); | |
573 | via_proc = 1; | |
574 | } | |
575 | #endif /* DISPLAY_VIA_TIMINGS && CONFIG_PROC_FS */ | |
576 | return 0; | |
577 | } | |
578 | ||
579 | static void __init init_hwif_via82cxxx(ide_hwif_t *hwif) | |
580 | { | |
581 | int i; | |
582 | ||
583 | hwif->autodma = 0; | |
584 | ||
585 | hwif->tuneproc = &via82cxxx_tune_drive; | |
586 | hwif->speedproc = &via_set_drive; | |
587 | ||
588 | ||
589 | #if defined(CONFIG_PPC_MULTIPLATFORM) && defined(CONFIG_PPC32) | |
590 | if(_machine == _MACH_chrp && _chrp_type == _CHRP_Pegasos) { | |
591 | hwif->irq = hwif->channel ? 15 : 14; | |
592 | } | |
593 | #endif | |
594 | ||
595 | for (i = 0; i < 2; i++) { | |
596 | hwif->drives[i].io_32bit = 1; | |
597 | hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1; | |
598 | hwif->drives[i].autotune = 1; | |
599 | hwif->drives[i].dn = hwif->channel * 2 + i; | |
600 | } | |
601 | ||
602 | if (!hwif->dma_base) | |
603 | return; | |
604 | ||
605 | hwif->atapi_dma = 1; | |
606 | hwif->ultra_mask = 0x7f; | |
607 | hwif->mwdma_mask = 0x07; | |
608 | hwif->swdma_mask = 0x07; | |
609 | ||
610 | if (!hwif->udma_four) | |
611 | hwif->udma_four = (via_80w >> hwif->channel) & 1; | |
612 | hwif->ide_dma_check = &via82cxxx_ide_dma_check; | |
613 | if (!noautodma) | |
614 | hwif->autodma = 1; | |
615 | hwif->drives[0].autodma = hwif->autodma; | |
616 | hwif->drives[1].autodma = hwif->autodma; | |
617 | } | |
618 | ||
619 | static ide_pci_device_t via82cxxx_chipset __devinitdata = { | |
620 | .name = "VP_IDE", | |
621 | .init_chipset = init_chipset_via82cxxx, | |
622 | .init_hwif = init_hwif_via82cxxx, | |
623 | .channels = 2, | |
624 | .autodma = NOAUTODMA, | |
625 | .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, | |
626 | .bootable = ON_BOARD, | |
627 | }; | |
628 | ||
629 | static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
630 | { | |
631 | return ide_setup_pci_device(dev, &via82cxxx_chipset); | |
632 | } | |
633 | ||
634 | static struct pci_device_id via_pci_tbl[] = { | |
635 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
636 | { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
637 | { 0, }, | |
638 | }; | |
639 | MODULE_DEVICE_TABLE(pci, via_pci_tbl); | |
640 | ||
641 | static struct pci_driver driver = { | |
642 | .name = "VIA_IDE", | |
643 | .id_table = via_pci_tbl, | |
644 | .probe = via_init_one, | |
645 | }; | |
646 | ||
647 | static int via_ide_init(void) | |
648 | { | |
649 | return ide_pci_register_driver(&driver); | |
650 | } | |
651 | ||
652 | module_init(via_ide_init); | |
653 | ||
654 | MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick"); | |
655 | MODULE_DESCRIPTION("PCI driver module for VIA IDE"); | |
656 | MODULE_LICENSE("GPL"); |