]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> |
669165da | 3 | * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc. |
4fce3164 | 4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 | 5 | * |
1da177e4 LT |
6 | * Portions Copyright (C) 1999 Promise Technology, Inc. |
7 | * Author: Frank Tiernan (frankt@promise.com) | |
8 | * Released under terms of General Public License | |
9 | */ | |
10 | ||
1da177e4 LT |
11 | #include <linux/types.h> |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/delay.h> | |
1da177e4 | 15 | #include <linux/blkdev.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/ide.h> | |
19 | ||
20 | #include <asm/io.h> | |
1da177e4 | 21 | |
ced3ec8a BZ |
22 | #define DRV_NAME "pdc202xx_old" |
23 | ||
1da177e4 LT |
24 | #define PDC202XX_DEBUG_DRIVE_INFO 0 |
25 | ||
26 | static const char *pdc_quirk_drives[] = { | |
27 | "QUANTUM FIREBALLlct08 08", | |
28 | "QUANTUM FIREBALLP KA6.4", | |
29 | "QUANTUM FIREBALLP KA9.1", | |
30 | "QUANTUM FIREBALLP LM20.4", | |
31 | "QUANTUM FIREBALLP KX13.6", | |
32 | "QUANTUM FIREBALLP KX20.5", | |
33 | "QUANTUM FIREBALLP KX27.3", | |
34 | "QUANTUM FIREBALLP LM20.5", | |
35 | NULL | |
36 | }; | |
37 | ||
4fce3164 | 38 | static void pdc_old_disable_66MHz_clock(ide_hwif_t *); |
1da177e4 | 39 | |
88b2b32b | 40 | static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 41 | { |
898ec223 | 42 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 43 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 44 | u8 drive_pci = 0x60 + (drive->dn << 2); |
1da177e4 | 45 | |
4fce3164 | 46 | u8 AP = 0, BP = 0, CP = 0; |
1da177e4 LT |
47 | u8 TA = 0, TB = 0, TC = 0; |
48 | ||
4fce3164 BZ |
49 | #if PDC202XX_DEBUG_DRIVE_INFO |
50 | u32 drive_conf = 0; | |
1da177e4 | 51 | pci_read_config_dword(dev, drive_pci, &drive_conf); |
4fce3164 | 52 | #endif |
1da177e4 | 53 | |
4fce3164 BZ |
54 | /* |
55 | * TODO: do this once per channel | |
56 | */ | |
57 | if (dev->device != PCI_DEVICE_ID_PROMISE_20246) | |
58 | pdc_old_disable_66MHz_clock(hwif); | |
1da177e4 | 59 | |
4fce3164 BZ |
60 | pci_read_config_byte(dev, drive_pci, &AP); |
61 | pci_read_config_byte(dev, drive_pci + 1, &BP); | |
62 | pci_read_config_byte(dev, drive_pci + 2, &CP); | |
1da177e4 LT |
63 | |
64 | switch(speed) { | |
1da177e4 LT |
65 | case XFER_UDMA_5: |
66 | case XFER_UDMA_4: TB = 0x20; TC = 0x01; break; | |
67 | case XFER_UDMA_2: TB = 0x20; TC = 0x01; break; | |
68 | case XFER_UDMA_3: | |
69 | case XFER_UDMA_1: TB = 0x40; TC = 0x02; break; | |
70 | case XFER_UDMA_0: | |
71 | case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; | |
72 | case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; | |
4fce3164 | 73 | case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break; |
1da177e4 LT |
74 | case XFER_PIO_4: TA = 0x01; TB = 0x04; break; |
75 | case XFER_PIO_3: TA = 0x02; TB = 0x06; break; | |
76 | case XFER_PIO_2: TA = 0x03; TB = 0x08; break; | |
77 | case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; | |
78 | case XFER_PIO_0: | |
79 | default: TA = 0x09; TB = 0x13; break; | |
80 | } | |
81 | ||
82 | if (speed < XFER_SW_DMA_0) { | |
4fce3164 BZ |
83 | /* |
84 | * preserve SYNC_INT / ERDDY_EN bits while clearing | |
85 | * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A | |
86 | */ | |
87 | AP &= ~0x3f; | |
48fb2688 | 88 | if (ata_id_iordy_disable(drive->id)) |
4fce3164 BZ |
89 | AP |= 0x20; /* set IORDY_EN bit */ |
90 | if (drive->media == ide_disk) | |
91 | AP |= 0x10; /* set Prefetch_EN bit */ | |
92 | /* clear PB[4:0] bits of register B */ | |
93 | BP &= ~0x1f; | |
94 | pci_write_config_byte(dev, drive_pci, AP | TA); | |
95 | pci_write_config_byte(dev, drive_pci + 1, BP | TB); | |
1da177e4 | 96 | } else { |
4fce3164 BZ |
97 | /* clear MB[2:0] bits of register B */ |
98 | BP &= ~0xe0; | |
99 | /* clear MC[3:0] bits of register C */ | |
100 | CP &= ~0x0f; | |
101 | pci_write_config_byte(dev, drive_pci + 1, BP | TB); | |
102 | pci_write_config_byte(dev, drive_pci + 2, CP | TC); | |
1da177e4 LT |
103 | } |
104 | ||
105 | #if PDC202XX_DEBUG_DRIVE_INFO | |
106 | printk(KERN_DEBUG "%s: %s drive%d 0x%08x ", | |
107 | drive->name, ide_xfer_verbose(speed), | |
108 | drive->dn, drive_conf); | |
4fce3164 | 109 | pci_read_config_dword(dev, drive_pci, &drive_conf); |
1da177e4 | 110 | printk("0x%08x\n", drive_conf); |
4fce3164 | 111 | #endif |
1da177e4 LT |
112 | } |
113 | ||
26bcb879 | 114 | static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 115 | { |
88b2b32b | 116 | pdc202xx_set_mode(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
117 | } |
118 | ||
f454cbe8 | 119 | static u8 pdc2026x_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 120 | { |
36501650 | 121 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1bee4d1d | 122 | u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10); |
49521f97 | 123 | |
36501650 | 124 | pci_read_config_word(dev, 0x50, &CIS); |
49521f97 BZ |
125 | |
126 | return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
1da177e4 LT |
127 | } |
128 | ||
129 | /* | |
130 | * Set the control register to use the 66MHz system | |
131 | * clock for UDMA 3/4/5 mode operation when necessary. | |
132 | * | |
4fce3164 BZ |
133 | * FIXME: this register is shared by both channels, some locking is needed |
134 | * | |
1da177e4 LT |
135 | * It may also be possible to leave the 66MHz clock on |
136 | * and readjust the timing parameters. | |
137 | */ | |
138 | static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) | |
139 | { | |
1c029fd6 | 140 | unsigned long clock_reg = hwif->extra_base + 0x01; |
0ecdca26 | 141 | u8 clock = inb(clock_reg); |
1da177e4 | 142 | |
0ecdca26 | 143 | outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); |
1da177e4 LT |
144 | } |
145 | ||
146 | static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) | |
147 | { | |
1c029fd6 | 148 | unsigned long clock_reg = hwif->extra_base + 0x01; |
0ecdca26 | 149 | u8 clock = inb(clock_reg); |
1da177e4 | 150 | |
0ecdca26 | 151 | outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); |
1da177e4 LT |
152 | } |
153 | ||
f01393e4 | 154 | static void pdc202xx_quirkproc(ide_drive_t *drive) |
1da177e4 | 155 | { |
4dde4492 | 156 | const char **list, *m = (char *)&drive->id[ATA_ID_PROD]; |
d24ec426 SS |
157 | |
158 | for (list = pdc_quirk_drives; *list != NULL; list++) | |
4dde4492 | 159 | if (strstr(m, *list) != NULL) { |
f01393e4 BZ |
160 | drive->quirk_list = 2; |
161 | return; | |
162 | } | |
163 | ||
164 | drive->quirk_list = 0; | |
1da177e4 LT |
165 | } |
166 | ||
5e37bdc0 | 167 | static void pdc202xx_dma_start(ide_drive_t *drive) |
1da177e4 LT |
168 | { |
169 | if (drive->current_speed > XFER_UDMA_2) | |
170 | pdc_old_enable_66MHz_clock(drive->hwif); | |
97100fc8 | 171 | if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { |
898ec223 | 172 | ide_hwif_t *hwif = drive->hwif; |
b65fac32 | 173 | struct request *rq = hwif->rq; |
1c029fd6 | 174 | unsigned long high_16 = hwif->extra_base - 16; |
1da177e4 LT |
175 | unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); |
176 | u32 word_count = 0; | |
0ecdca26 | 177 | u8 clock = inb(high_16 + 0x11); |
1da177e4 | 178 | |
0ecdca26 | 179 | outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11); |
9780e2dd | 180 | word_count = (blk_rq_sectors(rq) << 8); |
1da177e4 LT |
181 | word_count = (rq_data_dir(rq) == READ) ? |
182 | word_count | 0x05000000 : | |
183 | word_count | 0x06000000; | |
0ecdca26 | 184 | outl(word_count, atapi_reg); |
1da177e4 LT |
185 | } |
186 | ide_dma_start(drive); | |
187 | } | |
188 | ||
5e37bdc0 | 189 | static int pdc202xx_dma_end(ide_drive_t *drive) |
1da177e4 | 190 | { |
97100fc8 | 191 | if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { |
898ec223 | 192 | ide_hwif_t *hwif = drive->hwif; |
1c029fd6 | 193 | unsigned long high_16 = hwif->extra_base - 16; |
1da177e4 LT |
194 | unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); |
195 | u8 clock = 0; | |
196 | ||
0ecdca26 BZ |
197 | outl(0, atapi_reg); /* zero out extra */ |
198 | clock = inb(high_16 + 0x11); | |
199 | outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11); | |
1da177e4 LT |
200 | } |
201 | if (drive->current_speed > XFER_UDMA_2) | |
202 | pdc_old_disable_66MHz_clock(drive->hwif); | |
653bcf52 | 203 | return ide_dma_end(drive); |
1da177e4 LT |
204 | } |
205 | ||
5e37bdc0 | 206 | static int pdc202xx_dma_test_irq(ide_drive_t *drive) |
1da177e4 | 207 | { |
898ec223 | 208 | ide_hwif_t *hwif = drive->hwif; |
1c029fd6 | 209 | unsigned long high_16 = hwif->extra_base - 16; |
cab7f8ed | 210 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
0ecdca26 | 211 | u8 sc1d = inb(high_16 + 0x001d); |
1da177e4 LT |
212 | |
213 | if (hwif->channel) { | |
214 | /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */ | |
215 | if ((sc1d & 0x50) == 0x50) | |
216 | goto somebody_else; | |
217 | else if ((sc1d & 0x40) == 0x40) | |
218 | return (dma_stat & 4) == 4; | |
219 | } else { | |
220 | /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */ | |
221 | if ((sc1d & 0x05) == 0x05) | |
222 | goto somebody_else; | |
223 | else if ((sc1d & 0x04) == 0x04) | |
224 | return (dma_stat & 4) == 4; | |
225 | } | |
226 | somebody_else: | |
227 | return (dma_stat & 4) == 4; /* return 1 if INTR asserted */ | |
228 | } | |
229 | ||
669165da | 230 | static void pdc202xx_reset(ide_drive_t *drive) |
1da177e4 | 231 | { |
669165da | 232 | ide_hwif_t *hwif = drive->hwif; |
1c029fd6 | 233 | unsigned long high_16 = hwif->extra_base - 16; |
0ecdca26 | 234 | u8 udma_speed_flag = inb(high_16 | 0x001f); |
1da177e4 | 235 | |
669165da SS |
236 | printk(KERN_WARNING "PDC202xx: software reset...\n"); |
237 | ||
0ecdca26 | 238 | outb(udma_speed_flag | 0x10, high_16 | 0x001f); |
1da177e4 | 239 | mdelay(100); |
0ecdca26 | 240 | outb(udma_speed_flag & ~0x10, high_16 | 0x001f); |
1da177e4 LT |
241 | mdelay(2000); /* 2 seconds ?! */ |
242 | ||
26bcb879 | 243 | ide_set_max_pio(drive); |
1da177e4 LT |
244 | } |
245 | ||
ac95beed BZ |
246 | static void pdc202xx_dma_lost_irq(ide_drive_t *drive) |
247 | { | |
248 | pdc202xx_reset(drive); | |
249 | ide_dma_lost_irq(drive); | |
250 | } | |
251 | ||
2ed0ef54 | 252 | static int init_chipset_pdc202xx(struct pci_dev *dev) |
1da177e4 | 253 | { |
73369d2a | 254 | unsigned long dmabase = pci_resource_start(dev, 4); |
1da177e4 LT |
255 | u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0; |
256 | ||
73369d2a BZ |
257 | if (dmabase == 0) |
258 | goto out; | |
1da177e4 | 259 | |
0ecdca26 BZ |
260 | udma_speed_flag = inb(dmabase | 0x1f); |
261 | primary_mode = inb(dmabase | 0x1a); | |
262 | secondary_mode = inb(dmabase | 0x1b); | |
1da177e4 LT |
263 | printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ |
264 | "Primary %s Mode " \ | |
5e59c236 | 265 | "Secondary %s Mode.\n", pci_name(dev), |
1da177e4 LT |
266 | (udma_speed_flag & 1) ? "EN" : "DIS", |
267 | (primary_mode & 1) ? "MASTER" : "PCI", | |
268 | (secondary_mode & 1) ? "MASTER" : "PCI" ); | |
269 | ||
1da177e4 LT |
270 | if (!(udma_speed_flag & 1)) { |
271 | printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", | |
5e59c236 | 272 | pci_name(dev), udma_speed_flag, |
1da177e4 | 273 | (udma_speed_flag|1)); |
0ecdca26 BZ |
274 | outb(udma_speed_flag | 1, dmabase | 0x1f); |
275 | printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); | |
1da177e4 | 276 | } |
73369d2a | 277 | out: |
2ed0ef54 | 278 | return 0; |
1da177e4 LT |
279 | } |
280 | ||
97f84baa BZ |
281 | static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev, |
282 | const char *name) | |
1da177e4 LT |
283 | { |
284 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) { | |
285 | u8 irq = 0, irq2 = 0; | |
286 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
287 | /* 0xbc */ | |
288 | pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); | |
289 | if (irq != irq2) { | |
290 | pci_write_config_byte(dev, | |
291 | (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */ | |
28cfd8af BZ |
292 | printk(KERN_INFO "%s %s: PCI config space interrupt " |
293 | "mirror fixed\n", name, pci_name(dev)); | |
1da177e4 LT |
294 | } |
295 | } | |
1da177e4 LT |
296 | } |
297 | ||
4db90a14 BZ |
298 | #define IDE_HFLAGS_PDC202XX \ |
299 | (IDE_HFLAG_ERROR_STOPS_FIFO | \ | |
4db90a14 BZ |
300 | IDE_HFLAG_OFF_BOARD) |
301 | ||
ac95beed BZ |
302 | static const struct ide_port_ops pdc20246_port_ops = { |
303 | .set_pio_mode = pdc202xx_set_pio_mode, | |
304 | .set_dma_mode = pdc202xx_set_mode, | |
305 | .quirkproc = pdc202xx_quirkproc, | |
306 | }; | |
307 | ||
308 | static const struct ide_port_ops pdc2026x_port_ops = { | |
309 | .set_pio_mode = pdc202xx_set_pio_mode, | |
310 | .set_dma_mode = pdc202xx_set_mode, | |
311 | .quirkproc = pdc202xx_quirkproc, | |
312 | .resetproc = pdc202xx_reset, | |
313 | .cable_detect = pdc2026x_cable_detect, | |
314 | }; | |
315 | ||
f37afdac BZ |
316 | static const struct ide_dma_ops pdc20246_dma_ops = { |
317 | .dma_host_set = ide_dma_host_set, | |
318 | .dma_setup = ide_dma_setup, | |
f37afdac | 319 | .dma_start = ide_dma_start, |
653bcf52 | 320 | .dma_end = ide_dma_end, |
5e37bdc0 | 321 | .dma_test_irq = pdc202xx_dma_test_irq, |
521a415c | 322 | .dma_lost_irq = ide_dma_lost_irq, |
22117d6e | 323 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b5315 | 324 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
325 | }; |
326 | ||
f37afdac BZ |
327 | static const struct ide_dma_ops pdc2026x_dma_ops = { |
328 | .dma_host_set = ide_dma_host_set, | |
329 | .dma_setup = ide_dma_setup, | |
5e37bdc0 BZ |
330 | .dma_start = pdc202xx_dma_start, |
331 | .dma_end = pdc202xx_dma_end, | |
332 | .dma_test_irq = pdc202xx_dma_test_irq, | |
333 | .dma_lost_irq = pdc202xx_dma_lost_irq, | |
22117d6e | 334 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
35c9b4da | 335 | .dma_clear = pdc202xx_reset, |
592b5315 | 336 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
337 | }; |
338 | ||
6b492496 | 339 | #define DECLARE_PDC2026X_DEV(udma, sectors) \ |
5ef8cb5d | 340 | { \ |
ced3ec8a | 341 | .name = DRV_NAME, \ |
5ef8cb5d | 342 | .init_chipset = init_chipset_pdc202xx, \ |
ac95beed | 343 | .port_ops = &pdc2026x_port_ops, \ |
5e37bdc0 | 344 | .dma_ops = &pdc2026x_dma_ops, \ |
6b492496 | 345 | .host_flags = IDE_HFLAGS_PDC202XX, \ |
5ef8cb5d BZ |
346 | .pio_mask = ATA_PIO4, \ |
347 | .mwdma_mask = ATA_MWDMA2, \ | |
348 | .udma_mask = udma, \ | |
6b492496 | 349 | .max_sectors = sectors, \ |
5ef8cb5d BZ |
350 | } |
351 | ||
85620436 | 352 | static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = { |
ced3ec8a BZ |
353 | { /* 0: PDC20246 */ |
354 | .name = DRV_NAME, | |
1da177e4 | 355 | .init_chipset = init_chipset_pdc202xx, |
ac95beed | 356 | .port_ops = &pdc20246_port_ops, |
5e37bdc0 | 357 | .dma_ops = &pdc20246_dma_ops, |
4db90a14 | 358 | .host_flags = IDE_HFLAGS_PDC202XX, |
4099d143 | 359 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
360 | .mwdma_mask = ATA_MWDMA2, |
361 | .udma_mask = ATA_UDMA2, | |
5ef8cb5d BZ |
362 | }, |
363 | ||
ced3ec8a BZ |
364 | /* 1: PDC2026{2,3} */ |
365 | DECLARE_PDC2026X_DEV(ATA_UDMA4, 0), | |
6b492496 BZ |
366 | /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */ |
367 | DECLARE_PDC2026X_DEV(ATA_UDMA5, 256), | |
1da177e4 LT |
368 | }; |
369 | ||
370 | /** | |
371 | * pdc202xx_init_one - called when a PDC202xx is found | |
372 | * @dev: the pdc202xx device | |
373 | * @id: the matching pci id | |
374 | * | |
375 | * Called when the PCI registration layer (or the IDE initialization) | |
376 | * finds a device matching our IDE device tables. | |
377 | */ | |
378 | ||
379 | static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
380 | { | |
85620436 | 381 | const struct ide_port_info *d; |
97f84baa BZ |
382 | u8 idx = id->driver_data; |
383 | ||
384 | d = &pdc202xx_chipsets[idx]; | |
385 | ||
ced3ec8a | 386 | if (idx < 2) |
97f84baa BZ |
387 | pdc202ata4_fixup_irq(dev, d->name); |
388 | ||
ced3ec8a | 389 | if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) { |
97f84baa | 390 | struct pci_dev *bridge = dev->bus->self; |
1da177e4 | 391 | |
97f84baa BZ |
392 | if (bridge && |
393 | bridge->vendor == PCI_VENDOR_ID_INTEL && | |
394 | (bridge->device == PCI_DEVICE_ID_INTEL_I960 || | |
395 | bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { | |
ced3ec8a | 396 | printk(KERN_INFO DRV_NAME " %s: skipping Promise " |
28cfd8af BZ |
397 | "PDC20265 attached to I2O RAID controller\n", |
398 | pci_name(dev)); | |
97f84baa BZ |
399 | return -ENODEV; |
400 | } | |
401 | } | |
402 | ||
6cdf6eb3 | 403 | return ide_pci_init_one(dev, d, NULL); |
1da177e4 LT |
404 | } |
405 | ||
9cbcc5e3 BZ |
406 | static const struct pci_device_id pdc202xx_pci_tbl[] = { |
407 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, | |
408 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, | |
ced3ec8a BZ |
409 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, |
410 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, | |
411 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, | |
1da177e4 LT |
412 | { 0, }, |
413 | }; | |
414 | MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl); | |
415 | ||
a9ab09e2 | 416 | static struct pci_driver pdc202xx_pci_driver = { |
1da177e4 LT |
417 | .name = "Promise_Old_IDE", |
418 | .id_table = pdc202xx_pci_tbl, | |
419 | .probe = pdc202xx_init_one, | |
574a1c24 | 420 | .remove = ide_pci_remove, |
feb22b7f BZ |
421 | .suspend = ide_pci_suspend, |
422 | .resume = ide_pci_resume, | |
1da177e4 LT |
423 | }; |
424 | ||
82ab1eec | 425 | static int __init pdc202xx_ide_init(void) |
1da177e4 | 426 | { |
a9ab09e2 | 427 | return ide_pci_register_driver(&pdc202xx_pci_driver); |
1da177e4 LT |
428 | } |
429 | ||
574a1c24 BZ |
430 | static void __exit pdc202xx_ide_exit(void) |
431 | { | |
a9ab09e2 | 432 | pci_unregister_driver(&pdc202xx_pci_driver); |
574a1c24 BZ |
433 | } |
434 | ||
1da177e4 | 435 | module_init(pdc202xx_ide_init); |
574a1c24 | 436 | module_exit(pdc202xx_ide_exit); |
1da177e4 LT |
437 | |
438 | MODULE_AUTHOR("Andre Hedrick, Frank Tiernan"); | |
439 | MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); | |
440 | MODULE_LICENSE("GPL"); |