[mirror_ubuntu-bionic-kernel.git] / drivers / ide / pdc202xx_old.c

/*
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007, 2009	MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#define DRV_NAME "pdc202xx_old"

#define PDC202XX_DEBUG_DRIVE_INFO	0

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 drive_pci		= 0x60 + (drive->dn << 2);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

#if PDC202XX_DEBUG_DRIVE_INFO
	u32			drive_conf = 0;
	pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}

#if PDC202XX_DEBUG_DRIVE_INFO
	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, drive_conf);
	pci_read_config_dword(dev, drive_pci, &drive_conf);
	printk("0x%08x\n", drive_conf);
#endif
}

static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
}

static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);

	pci_read_config_word(dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc202xx_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
		ide_hwif_t *hwif	= drive->hwif;
		struct request *rq	= hwif->rq;
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (blk_rq_sectors(rq) << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
		ide_hwif_t *hwif	= drive->hwif;
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return ide_dma_end(drive);
}

static int init_chipset_pdc202xx(struct pci_dev *dev)
{
	unsigned long dmabase = pci_resource_start(dev, 4);
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (dmabase == 0)
		goto out;

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", pci_name(dev),
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			pci_name(dev), udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
out:
	return 0;
}

static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
					   const char *name)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s %s: PCI config space interrupt "
				"mirror fixed\n", name, pci_name(dev));
		}
	}
}

#define IDE_HFLAGS_PDC202XX \
	(IDE_HFLAG_ERROR_STOPS_FIFO | \
	 IDE_HFLAG_OFF_BOARD)

static const struct ide_port_ops pdc20246_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
};

static const struct ide_port_ops pdc2026x_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.cable_detect		= pdc2026x_cable_detect,
};

static const struct ide_dma_ops pdc2026x_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= pdc202xx_dma_start,
	.dma_end		= pdc202xx_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

#define DECLARE_PDC2026X_DEV(udma, sectors) \
	{ \
		.name		= DRV_NAME, \
		.init_chipset	= init_chipset_pdc202xx, \
		.port_ops	= &pdc2026x_port_ops, \
		.dma_ops	= &pdc2026x_dma_ops, \
		.host_flags	= IDE_HFLAGS_PDC202XX, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
		.max_sectors	= sectors, \
	}

static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
	{	/* 0: PDC20246 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_pdc202xx,
		.port_ops	= &pdc20246_port_ops,
		.dma_ops	= &sff_dma_ops,
		.host_flags	= IDE_HFLAGS_PDC202XX,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},

	/* 1: PDC2026{2,3} */
	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
	/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
	DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	u8 idx = id->driver_data;

	d = &pdc202xx_chipsets[idx];

	if (idx < 2)
		pdc202ata4_fixup_irq(dev, d->name);

	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;

		if (bridge &&
		    bridge->vendor == PCI_VENDOR_ID_INTEL &&
		    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
		     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
			printk(KERN_INFO DRV_NAME " %s: skipping Promise "
				"PDC20265 attached to I2O RAID controller\n",
				pci_name(dev));
			return -ENODEV;
		}
	}

	return ide_pci_init_one(dev, d, NULL);
}

static const struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver pdc202xx_pci_driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&pdc202xx_pci_driver);
}

static void __exit pdc202xx_ide_exit(void)
{
	pci_unregister_driver(&pdc202xx_pci_driver);
}

module_init(pdc202xx_ide_init);
module_exit(pdc202xx_ide_exit);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
669165da	3	* Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
4fce3164	4	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4	5	*
1da177e4 LT	6	* Portions Copyright (C) 1999 Promise Technology, Inc.
	7	* Author: Frank Tiernan (frankt@promise.com)
	8	* Released under terms of General Public License
	9	*/
	10
1da177e4 LT	11	#include <linux/types.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/delay.h>
1da177e4	15	#include <linux/blkdev.h>
1da177e4 LT	16	#include <linux/pci.h>
	17	#include <linux/init.h>
	18	#include <linux/ide.h>
	19
	20	#include <asm/io.h>
1da177e4	21
ced3ec8a BZ	22	#define DRV_NAME "pdc202xx_old"
ced3ec8a BZ	23
1da177e4 LT	24	#define PDC202XX_DEBUG_DRIVE_INFO 0
1da177e4 LT	25
4fce3164	26	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
1da177e4	27
88b2b32b	28	static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4	29	{
898ec223	30	ide_hwif_t *hwif = drive->hwif;
36501650	31	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	32	u8 drive_pci = 0x60 + (drive->dn << 2);
1da177e4	33
4fce3164	34	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	35	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	36
4fce3164 BZ	37	#if PDC202XX_DEBUG_DRIVE_INFO
4fce3164 BZ	38	u32 drive_conf = 0;
1da177e4	39	pci_read_config_dword(dev, drive_pci, &drive_conf);
4fce3164	40	#endif
1da177e4	41
4fce3164 BZ	42	/*
	43	* TODO: do this once per channel
	44	*/
	45	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	46	pdc_old_disable_66MHz_clock(hwif);
1da177e4	47
4fce3164 BZ	48	pci_read_config_byte(dev, drive_pci, &AP);
	49	pci_read_config_byte(dev, drive_pci + 1, &BP);
	50	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	51
1da177e4 LT	52	switch(speed) {
1da177e4 LT	53	case XFER_UDMA_5:
	54	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	55	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	56	case XFER_UDMA_3:
	57	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	58	case XFER_UDMA_0:
	59	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	60	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	61	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	62	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	63	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	64	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	65	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	66	case XFER_PIO_0:
	67	default: TA = 0x09; TB = 0x13; break;
	68	}
	69
	70	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	71	/*
	72	* preserve SYNC_INT / ERDDY_EN bits while clearing
	73	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	74	*/
	75	AP &= ~0x3f;
c9ef59ff	76	if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
4fce3164 BZ	77	AP \|= 0x20; /* set IORDY_EN bit */
	78	if (drive->media == ide_disk)
	79	AP \|= 0x10; /* set Prefetch_EN bit */
	80	/* clear PB[4:0] bits of register B */
	81	BP &= ~0x1f;
	82	pci_write_config_byte(dev, drive_pci, AP \| TA);
	83	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	84	} else {
4fce3164 BZ	85	/* clear MB[2:0] bits of register B */
	86	BP &= ~0xe0;
	87	/* clear MC[3:0] bits of register C */
	88	CP &= ~0x0f;
	89	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	90	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4 LT	91	}
	92
	93	#if PDC202XX_DEBUG_DRIVE_INFO
	94	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
	95	drive->name, ide_xfer_verbose(speed),
	96	drive->dn, drive_conf);
4fce3164	97	pci_read_config_dword(dev, drive_pci, &drive_conf);
1da177e4	98	printk("0x%08x\n", drive_conf);
4fce3164	99	#endif
1da177e4 LT	100	}
1da177e4 LT	101
26bcb879	102	static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	103	{
88b2b32b	104	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
1da177e4 LT	105	}
1da177e4 LT	106
f454cbe8	107	static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
1da177e4	108	{
36501650	109	struct pci_dev *dev = to_pci_dev(hwif->dev);
1bee4d1d	110	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
49521f97	111
36501650	112	pci_read_config_word(dev, 0x50, &CIS);
49521f97 BZ	113
49521f97 BZ	114	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	115	}
	116
	117	/*
	118	* Set the control register to use the 66MHz system
	119	* clock for UDMA 3/4/5 mode operation when necessary.
	120	*
4fce3164 BZ	121	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	122	*
1da177e4 LT	123	* It may also be possible to leave the 66MHz clock on
	124	* and readjust the timing parameters.
	125	*/
	126	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	127	{
1c029fd6	128	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	129	u8 clock = inb(clock_reg);
1da177e4	130
0ecdca26	131	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	132	}
	133
	134	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	135	{
1c029fd6	136	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	137	u8 clock = inb(clock_reg);
1da177e4	138
0ecdca26	139	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	140	}
1da177e4 LT	141
5e37bdc0	142	static void pdc202xx_dma_start(ide_drive_t *drive)
1da177e4 LT	143	{
	144	if (drive->current_speed > XFER_UDMA_2)
	145	pdc_old_enable_66MHz_clock(drive->hwif);
97100fc8	146	if (drive->media != ide_disk \|\| (drive->dev_flags & IDE_DFLAG_LBA48)) {
898ec223	147	ide_hwif_t *hwif = drive->hwif;
b65fac32	148	struct request *rq = hwif->rq;
1c029fd6	149	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	150	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
1da177e4 LT	151	u32 word_count = 0;
0ecdca26	152	u8 clock = inb(high_16 + 0x11);
1da177e4	153
0ecdca26	154	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
9780e2dd	155	word_count = (blk_rq_sectors(rq) << 8);
1da177e4 LT	156	word_count = (rq_data_dir(rq) == READ) ?
	157	word_count \| 0x05000000 :
	158	word_count \| 0x06000000;
0ecdca26	159	outl(word_count, atapi_reg);
1da177e4 LT	160	}
	161	ide_dma_start(drive);
	162	}
	163
5e37bdc0	164	static int pdc202xx_dma_end(ide_drive_t *drive)
1da177e4	165	{
97100fc8	166	if (drive->media != ide_disk \|\| (drive->dev_flags & IDE_DFLAG_LBA48)) {
898ec223	167	ide_hwif_t *hwif = drive->hwif;
1c029fd6	168	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	169	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	170	u8 clock = 0;
	171
0ecdca26 BZ	172	outl(0, atapi_reg); /* zero out extra */
	173	clock = inb(high_16 + 0x11);
	174	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	175	}
	176	if (drive->current_speed > XFER_UDMA_2)
	177	pdc_old_disable_66MHz_clock(drive->hwif);
653bcf52	178	return ide_dma_end(drive);
1da177e4 LT	179	}
1da177e4 LT	180
2ed0ef54	181	static int init_chipset_pdc202xx(struct pci_dev *dev)
1da177e4	182	{
73369d2a	183	unsigned long dmabase = pci_resource_start(dev, 4);
1da177e4 LT	184	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
1da177e4 LT	185
73369d2a BZ	186	if (dmabase == 0)
73369d2a BZ	187	goto out;
1da177e4	188
0ecdca26 BZ	189	udma_speed_flag = inb(dmabase \| 0x1f);
	190	primary_mode = inb(dmabase \| 0x1a);
	191	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	192	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
1da177e4 LT	193	"Primary %s Mode " \
5e59c236	194	"Secondary %s Mode.\n", pci_name(dev),
1da177e4 LT	195	(udma_speed_flag & 1) ? "EN" : "DIS",
	196	(primary_mode & 1) ? "MASTER" : "PCI",
	197	(secondary_mode & 1) ? "MASTER" : "PCI" );
	198
1da177e4 LT	199	if (!(udma_speed_flag & 1)) {
1da177e4 LT	200	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
5e59c236	201	pci_name(dev), udma_speed_flag,
1da177e4	202	(udma_speed_flag\|1));
0ecdca26 BZ	203	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	204	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4	205	}
73369d2a	206	out:
2ed0ef54	207	return 0;
1da177e4 LT	208	}
1da177e4 LT	209
97f84baa BZ	210	static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
97f84baa BZ	211	const char *name)
1da177e4 LT	212	{
	213	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	214	u8 irq = 0, irq2 = 0;
	215	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	216	/* 0xbc */
	217	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	218	if (irq != irq2) {
	219	pci_write_config_byte(dev,
	220	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
28cfd8af BZ	221	printk(KERN_INFO "%s %s: PCI config space interrupt "
28cfd8af BZ	222	"mirror fixed\n", name, pci_name(dev));
1da177e4 LT	223	}
1da177e4 LT	224	}
1da177e4 LT	225	}
1da177e4 LT	226
4db90a14 BZ	227	#define IDE_HFLAGS_PDC202XX \
4db90a14 BZ	228	(IDE_HFLAG_ERROR_STOPS_FIFO \| \
4db90a14 BZ	229	IDE_HFLAG_OFF_BOARD)
4db90a14 BZ	230
ac95beed BZ	231	static const struct ide_port_ops pdc20246_port_ops = {
	232	.set_pio_mode = pdc202xx_set_pio_mode,
	233	.set_dma_mode = pdc202xx_set_mode,
ac95beed BZ	234	};
	235
	236	static const struct ide_port_ops pdc2026x_port_ops = {
	237	.set_pio_mode = pdc202xx_set_pio_mode,
	238	.set_dma_mode = pdc202xx_set_mode,
ac95beed BZ	239	.cable_detect = pdc2026x_cable_detect,
	240	};
	241
f37afdac BZ	242	static const struct ide_dma_ops pdc2026x_dma_ops = {
	243	.dma_host_set = ide_dma_host_set,
	244	.dma_setup = ide_dma_setup,
5e37bdc0 BZ	245	.dma_start = pdc202xx_dma_start,
5e37bdc0 BZ	246	.dma_end = pdc202xx_dma_end,
72b9304f	247	.dma_test_irq = ide_dma_test_irq,
1221e241	248	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	249	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	250	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	251	};
5e37bdc0 BZ	252
6b492496	253	#define DECLARE_PDC2026X_DEV(udma, sectors) \
5ef8cb5d	254	{ \
ced3ec8a	255	.name = DRV_NAME, \
5ef8cb5d	256	.init_chipset = init_chipset_pdc202xx, \
ac95beed	257	.port_ops = &pdc2026x_port_ops, \
5e37bdc0	258	.dma_ops = &pdc2026x_dma_ops, \
6b492496	259	.host_flags = IDE_HFLAGS_PDC202XX, \
5ef8cb5d BZ	260	.pio_mask = ATA_PIO4, \
	261	.mwdma_mask = ATA_MWDMA2, \
	262	.udma_mask = udma, \
6b492496	263	.max_sectors = sectors, \
5ef8cb5d BZ	264	}
5ef8cb5d BZ	265
85620436	266	static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
ced3ec8a BZ	267	{ /* 0: PDC20246 */
ced3ec8a BZ	268	.name = DRV_NAME,
1da177e4	269	.init_chipset = init_chipset_pdc202xx,
ac95beed	270	.port_ops = &pdc20246_port_ops,
72b9304f	271	.dma_ops = &sff_dma_ops,
4db90a14	272	.host_flags = IDE_HFLAGS_PDC202XX,
4099d143	273	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	274	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	275	.udma_mask = ATA_UDMA2,
5ef8cb5d BZ	276	},
5ef8cb5d BZ	277
ced3ec8a BZ	278	/* 1: PDC2026{2,3} */
ced3ec8a BZ	279	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
6b492496 BZ	280	/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
6b492496 BZ	281	DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
1da177e4 LT	282	};
	283
	284	/**
	285	* pdc202xx_init_one - called when a PDC202xx is found
	286	* @dev: the pdc202xx device
	287	* @id: the matching pci id
	288	*
	289	* Called when the PCI registration layer (or the IDE initialization)
	290	* finds a device matching our IDE device tables.
	291	*/
	292
	293	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	294	{
85620436	295	const struct ide_port_info *d;
97f84baa BZ	296	u8 idx = id->driver_data;
	297
	298	d = &pdc202xx_chipsets[idx];
	299
ced3ec8a	300	if (idx < 2)
97f84baa BZ	301	pdc202ata4_fixup_irq(dev, d->name);
97f84baa BZ	302
ced3ec8a	303	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
97f84baa	304	struct pci_dev *bridge = dev->bus->self;
1da177e4	305
97f84baa BZ	306	if (bridge &&
	307	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	308	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	309	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
ced3ec8a	310	printk(KERN_INFO DRV_NAME " %s: skipping Promise "
28cfd8af BZ	311	"PDC20265 attached to I2O RAID controller\n",
28cfd8af BZ	312	pci_name(dev));
97f84baa BZ	313	return -ENODEV;
	314	}
	315	}
	316
6cdf6eb3	317	return ide_pci_init_one(dev, d, NULL);
1da177e4 LT	318	}
1da177e4 LT	319
9cbcc5e3 BZ	320	static const struct pci_device_id pdc202xx_pci_tbl[] = {
	321	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	322	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
ced3ec8a BZ	323	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	324	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	325	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
1da177e4 LT	326	{ 0, },
	327	};
	328	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	329
a9ab09e2	330	static struct pci_driver pdc202xx_pci_driver = {
1da177e4 LT	331	.name = "Promise_Old_IDE",
	332	.id_table = pdc202xx_pci_tbl,
	333	.probe = pdc202xx_init_one,
574a1c24	334	.remove = ide_pci_remove,
feb22b7f BZ	335	.suspend = ide_pci_suspend,
feb22b7f BZ	336	.resume = ide_pci_resume,
1da177e4 LT	337	};
1da177e4 LT	338
82ab1eec	339	static int __init pdc202xx_ide_init(void)
1da177e4	340	{
a9ab09e2	341	return ide_pci_register_driver(&pdc202xx_pci_driver);
1da177e4 LT	342	}
1da177e4 LT	343
574a1c24 BZ	344	static void __exit pdc202xx_ide_exit(void)
574a1c24 BZ	345	{
a9ab09e2	346	pci_unregister_driver(&pdc202xx_pci_driver);
574a1c24 BZ	347	}
574a1c24 BZ	348
1da177e4	349	module_init(pdc202xx_ide_init);
574a1c24	350	module_exit(pdc202xx_ide_exit);
1da177e4 LT	351
	352	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	353	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	354	MODULE_LICENSE("GPL");