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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com> |
5fd216bb BZ |
3 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
4 | * | |
1da177e4 LT |
5 | * May be copied or modified under the terms of the GNU General Public License |
6 | * | |
7 | * Development of this chipset driver was funded | |
8 | * by the nice folks at National Semiconductor. | |
9 | * | |
10 | * Documentation: | |
11 | * Available from National Semiconductor | |
12 | */ | |
13 | ||
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
1da177e4 LT |
17 | #include <linux/pci.h> |
18 | #include <linux/init.h> | |
19 | #include <linux/ide.h> | |
20 | #include <linux/pm.h> | |
78829dd9 | 21 | |
1da177e4 | 22 | #include <asm/io.h> |
1da177e4 | 23 | |
ced3ec8a BZ |
24 | #define DRV_NAME "sc1200" |
25 | ||
1da177e4 LT |
26 | #define SC1200_REV_A 0x00 |
27 | #define SC1200_REV_B1 0x01 | |
28 | #define SC1200_REV_B3 0x02 | |
29 | #define SC1200_REV_C1 0x03 | |
30 | #define SC1200_REV_D1 0x04 | |
31 | ||
32 | #define PCI_CLK_33 0x00 | |
33 | #define PCI_CLK_48 0x01 | |
34 | #define PCI_CLK_66 0x02 | |
35 | #define PCI_CLK_33A 0x03 | |
36 | ||
37 | static unsigned short sc1200_get_pci_clock (void) | |
38 | { | |
39 | unsigned char chip_id, silicon_revision; | |
40 | unsigned int pci_clock; | |
41 | /* | |
42 | * Check the silicon revision, as not all versions of the chip | |
43 | * have the register with the fast PCI bus timings. | |
44 | */ | |
45 | chip_id = inb (0x903c); | |
46 | silicon_revision = inb (0x903d); | |
47 | ||
48 | // Read the fast pci clock frequency | |
49 | if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) { | |
50 | pci_clock = PCI_CLK_33; | |
51 | } else { | |
52 | // check clock generator configuration (cfcc) | |
53 | // the clock is in bits 8 and 9 of this word | |
54 | ||
55 | pci_clock = inw (0x901e); | |
56 | pci_clock >>= 8; | |
57 | pci_clock &= 0x03; | |
58 | if (pci_clock == PCI_CLK_33A) | |
59 | pci_clock = PCI_CLK_33; | |
60 | } | |
61 | return pci_clock; | |
62 | } | |
63 | ||
1da177e4 LT |
64 | /* |
65 | * Here are the standard PIO mode 0-4 timings for each "format". | |
66 | * Format-0 uses fast data reg timings, with slower command reg timings. | |
67 | * Format-1 uses fast timings for all registers, but won't work with all drives. | |
68 | */ | |
69 | static const unsigned int sc1200_pio_timings[4][5] = | |
70 | {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz | |
71 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz | |
72 | {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz | |
73 | {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz | |
74 | ||
75 | /* | |
76 | * After chip reset, the PIO timings are set to 0x00009172, which is not valid. | |
77 | */ | |
78 | //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172) | |
79 | ||
3c3f5d2c BZ |
80 | static void sc1200_tunepio(ide_drive_t *drive, u8 pio) |
81 | { | |
82 | ide_hwif_t *hwif = drive->hwif; | |
36501650 | 83 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
3c3f5d2c BZ |
84 | unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; |
85 | ||
86 | pci_read_config_dword(pdev, basereg + 4, &format); | |
87 | format = (format >> 31) & 1; | |
88 | if (format) | |
89 | format += sc1200_get_pci_clock(); | |
90 | pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3), | |
91 | sc1200_pio_timings[format][pio]); | |
92 | } | |
93 | ||
5fd216bb BZ |
94 | /* |
95 | * The SC1200 specifies that two drives sharing a cable cannot mix | |
96 | * UDMA/MDMA. It has to be one or the other, for the pair, though | |
97 | * different timings can still be chosen for each drive. We could | |
98 | * set the appropriate timing bits on the fly, but that might be | |
99 | * a bit confusing. So, for now we statically handle this requirement | |
100 | * by looking at our mate drive to see what it is capable of, before | |
101 | * choosing a mode for our own drive. | |
102 | */ | |
103 | static u8 sc1200_udma_filter(ide_drive_t *drive) | |
1da177e4 | 104 | { |
5fd216bb | 105 | ide_hwif_t *hwif = drive->hwif; |
7e59ea21 | 106 | ide_drive_t *mate = ide_get_pair_dev(drive); |
4dde4492 | 107 | u16 *mateid = mate->id; |
5fd216bb BZ |
108 | u8 mask = hwif->ultra_mask; |
109 | ||
7e59ea21 | 110 | if (mate == NULL) |
5fd216bb BZ |
111 | goto out; |
112 | ||
48fb2688 | 113 | if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) { |
4dde4492 BZ |
114 | if ((mateid[ATA_ID_FIELD_VALID] & 4) && |
115 | (mateid[ATA_ID_UDMA_MODES] & 7)) | |
5fd216bb | 116 | goto out; |
4dde4492 BZ |
117 | if ((mateid[ATA_ID_FIELD_VALID] & 2) && |
118 | (mateid[ATA_ID_MWDMA_MODES] & 7)) | |
5fd216bb | 119 | mask = 0; |
1da177e4 | 120 | } |
5fd216bb BZ |
121 | out: |
122 | return mask; | |
1da177e4 LT |
123 | } |
124 | ||
88b2b32b | 125 | static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode) |
1da177e4 LT |
126 | { |
127 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 128 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
129 | unsigned int reg, timings; |
130 | unsigned short pci_clock; | |
131 | unsigned int basereg = hwif->channel ? 0x50 : 0x40; | |
132 | ||
4eed504d BZ |
133 | static const u32 udma_timing[3][3] = { |
134 | { 0x00921250, 0x00911140, 0x00911030 }, | |
135 | { 0x00932470, 0x00922260, 0x00922140 }, | |
136 | { 0x009436a1, 0x00933481, 0x00923261 }, | |
137 | }; | |
138 | ||
139 | static const u32 mwdma_timing[3][3] = { | |
140 | { 0x00077771, 0x00012121, 0x00002020 }, | |
141 | { 0x000bbbb2, 0x00024241, 0x00013131 }, | |
142 | { 0x000ffff3, 0x00035352, 0x00015151 }, | |
143 | }; | |
144 | ||
1da177e4 LT |
145 | pci_clock = sc1200_get_pci_clock(); |
146 | ||
147 | /* | |
1da177e4 LT |
148 | * Note that each DMA mode has several timings associated with it. |
149 | * The correct timing depends on the fast PCI clock freq. | |
150 | */ | |
4eed504d BZ |
151 | |
152 | if (mode >= XFER_UDMA_0) | |
153 | timings = udma_timing[pci_clock][mode - XFER_UDMA_0]; | |
154 | else | |
155 | timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0]; | |
1da177e4 | 156 | |
123995b9 | 157 | if ((drive->dn & 1) == 0) { |
36501650 | 158 | pci_read_config_dword(dev, basereg + 4, ®); |
1da177e4 | 159 | timings |= reg & 0x80000000; /* preserve PIO format bit */ |
36501650 BZ |
160 | pci_write_config_dword(dev, basereg + 4, timings); |
161 | } else | |
162 | pci_write_config_dword(dev, basereg + 12, timings); | |
1da177e4 LT |
163 | } |
164 | ||
1da177e4 LT |
165 | /* Replacement for the standard ide_dma_end action in |
166 | * dma_proc. | |
167 | * | |
168 | * returns 1 on error, 0 otherwise | |
169 | */ | |
5e37bdc0 | 170 | static int sc1200_dma_end(ide_drive_t *drive) |
1da177e4 LT |
171 | { |
172 | ide_hwif_t *hwif = HWIF(drive); | |
173 | unsigned long dma_base = hwif->dma_base; | |
174 | byte dma_stat; | |
175 | ||
176 | dma_stat = inb(dma_base+2); /* get DMA status */ | |
177 | ||
178 | if (!(dma_stat & 4)) | |
179 | printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n", | |
180 | dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2)); | |
181 | ||
182 | outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */ | |
183 | outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */ | |
184 | ||
185 | drive->waiting_for_dma = 0; | |
186 | ide_destroy_dmatable(drive); /* purge DMA mappings */ | |
187 | ||
188 | return (dma_stat & 7) != 4; /* verify good DMA status */ | |
189 | } | |
190 | ||
191 | /* | |
26bcb879 | 192 | * sc1200_set_pio_mode() handles setting of PIO modes |
1da177e4 LT |
193 | * for both the chipset and drive. |
194 | * | |
195 | * All existing BIOSs for this chipset guarantee that all drives | |
196 | * will have valid default PIO timings set up before we get here. | |
197 | */ | |
26bcb879 BZ |
198 | |
199 | static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
1da177e4 LT |
200 | { |
201 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 LT |
202 | int mode = -1; |
203 | ||
a01ba401 | 204 | /* |
26bcb879 | 205 | * bad abuse of ->set_pio_mode interface |
a01ba401 | 206 | */ |
1da177e4 LT |
207 | switch (pio) { |
208 | case 200: mode = XFER_UDMA_0; break; | |
209 | case 201: mode = XFER_UDMA_1; break; | |
210 | case 202: mode = XFER_UDMA_2; break; | |
211 | case 100: mode = XFER_MW_DMA_0; break; | |
212 | case 101: mode = XFER_MW_DMA_1; break; | |
213 | case 102: mode = XFER_MW_DMA_2; break; | |
214 | } | |
215 | if (mode != -1) { | |
216 | printk("SC1200: %s: changing (U)DMA mode\n", drive->name); | |
4a546e04 | 217 | ide_dma_off_quietly(drive); |
97100fc8 BZ |
218 | if (ide_set_dma_mode(drive, mode) == 0 && |
219 | (drive->dev_flags & IDE_DFLAG_USING_DMA)) | |
5e37bdc0 | 220 | hwif->dma_ops->dma_host_set(drive, 1); |
1da177e4 LT |
221 | return; |
222 | } | |
223 | ||
88b2b32b | 224 | sc1200_tunepio(drive, pio); |
1da177e4 LT |
225 | } |
226 | ||
b86cc29d | 227 | #ifdef CONFIG_PM |
7c0e2666 BZ |
228 | struct sc1200_saved_state { |
229 | u32 regs[8]; | |
230 | }; | |
1da177e4 | 231 | |
3bfffd97 | 232 | static int sc1200_suspend (struct pci_dev *dev, pm_message_t state) |
1da177e4 | 233 | { |
ca078bae | 234 | printk("SC1200: suspend(%u)\n", state.event); |
1da177e4 | 235 | |
7c0e2666 BZ |
236 | /* |
237 | * we only save state when going from full power to less | |
238 | */ | |
ca078bae | 239 | if (state.event == PM_EVENT_ON) { |
96776f3b BZ |
240 | struct ide_host *host = pci_get_drvdata(dev); |
241 | struct sc1200_saved_state *ss = host->host_priv; | |
7c0e2666 BZ |
242 | unsigned int r; |
243 | ||
7c0e2666 BZ |
244 | /* |
245 | * save timing registers | |
246 | * (this may be unnecessary if BIOS also does it) | |
247 | */ | |
248 | for (r = 0; r < 8; r++) | |
249 | pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]); | |
250 | } | |
1da177e4 LT |
251 | |
252 | pci_disable_device(dev); | |
ca078bae | 253 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
1da177e4 LT |
254 | return 0; |
255 | } | |
256 | ||
257 | static int sc1200_resume (struct pci_dev *dev) | |
258 | { | |
96776f3b BZ |
259 | struct ide_host *host = pci_get_drvdata(dev); |
260 | struct sc1200_saved_state *ss = host->host_priv; | |
7c0e2666 BZ |
261 | unsigned int r; |
262 | int i; | |
9d434813 JG |
263 | |
264 | i = pci_enable_device(dev); | |
265 | if (i) | |
266 | return i; | |
1da177e4 | 267 | |
7c0e2666 BZ |
268 | /* |
269 | * restore timing registers | |
270 | * (this may be unnecessary if BIOS also does it) | |
271 | */ | |
96776f3b BZ |
272 | for (r = 0; r < 8; r++) |
273 | pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]); | |
7c0e2666 | 274 | |
1da177e4 LT |
275 | return 0; |
276 | } | |
b86cc29d | 277 | #endif |
1da177e4 | 278 | |
ac95beed BZ |
279 | static const struct ide_port_ops sc1200_port_ops = { |
280 | .set_pio_mode = sc1200_set_pio_mode, | |
281 | .set_dma_mode = sc1200_set_dma_mode, | |
282 | .udma_filter = sc1200_udma_filter, | |
283 | }; | |
284 | ||
f37afdac BZ |
285 | static const struct ide_dma_ops sc1200_dma_ops = { |
286 | .dma_host_set = ide_dma_host_set, | |
287 | .dma_setup = ide_dma_setup, | |
288 | .dma_exec_cmd = ide_dma_exec_cmd, | |
289 | .dma_start = ide_dma_start, | |
5e37bdc0 | 290 | .dma_end = sc1200_dma_end, |
f37afdac BZ |
291 | .dma_test_irq = ide_dma_test_irq, |
292 | .dma_lost_irq = ide_dma_lost_irq, | |
293 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
294 | }; |
295 | ||
85620436 | 296 | static const struct ide_port_info sc1200_chipset __devinitdata = { |
ced3ec8a | 297 | .name = DRV_NAME, |
ac95beed | 298 | .port_ops = &sc1200_port_ops, |
5e37bdc0 | 299 | .dma_ops = &sc1200_dma_ops, |
1c51361a BZ |
300 | .host_flags = IDE_HFLAG_SERIALIZE | |
301 | IDE_HFLAG_POST_SET_MODE | | |
5e71d9c5 | 302 | IDE_HFLAG_ABUSE_DMA_MODES, |
4099d143 | 303 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
304 | .mwdma_mask = ATA_MWDMA2, |
305 | .udma_mask = ATA_UDMA2, | |
1da177e4 LT |
306 | }; |
307 | ||
308 | static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
309 | { | |
96776f3b BZ |
310 | struct sc1200_saved_state *ss = NULL; |
311 | int rc; | |
312 | ||
313 | #ifdef CONFIG_PM | |
314 | ss = kmalloc(sizeof(*ss), GFP_KERNEL); | |
315 | if (ss == NULL) | |
316 | return -ENOMEM; | |
317 | #endif | |
318 | rc = ide_pci_init_one(dev, &sc1200_chipset, ss); | |
319 | if (rc) | |
320 | kfree(ss); | |
321 | ||
322 | return rc; | |
1da177e4 LT |
323 | } |
324 | ||
9cbcc5e3 BZ |
325 | static const struct pci_device_id sc1200_pci_tbl[] = { |
326 | { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0}, | |
1da177e4 LT |
327 | { 0, }, |
328 | }; | |
329 | MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl); | |
330 | ||
a9ab09e2 | 331 | static struct pci_driver sc1200_pci_driver = { |
1da177e4 LT |
332 | .name = "SC1200_IDE", |
333 | .id_table = sc1200_pci_tbl, | |
334 | .probe = sc1200_init_one, | |
991f5e69 | 335 | .remove = ide_pci_remove, |
b86cc29d | 336 | #ifdef CONFIG_PM |
1da177e4 LT |
337 | .suspend = sc1200_suspend, |
338 | .resume = sc1200_resume, | |
b86cc29d | 339 | #endif |
1da177e4 LT |
340 | }; |
341 | ||
82ab1eec | 342 | static int __init sc1200_ide_init(void) |
1da177e4 | 343 | { |
a9ab09e2 | 344 | return ide_pci_register_driver(&sc1200_pci_driver); |
1da177e4 LT |
345 | } |
346 | ||
991f5e69 BZ |
347 | static void __exit sc1200_ide_exit(void) |
348 | { | |
a9ab09e2 | 349 | pci_unregister_driver(&sc1200_pci_driver); |
991f5e69 BZ |
350 | } |
351 | ||
1da177e4 | 352 | module_init(sc1200_ide_init); |
991f5e69 | 353 | module_exit(sc1200_ide_exit); |
1da177e4 LT |
354 | |
355 | MODULE_AUTHOR("Mark Lord"); | |
356 | MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE"); | |
357 | MODULE_LICENSE("GPL"); |