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Commit | Line | Data |
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bde18a2e KI |
1 | /* |
2 | * Support for IDE interfaces on Celleb platform | |
3 | * | |
4 | * (C) Copyright 2006 TOSHIBA CORPORATION | |
5 | * | |
6 | * This code is based on drivers/ide/pci/siimage.c: | |
7 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
ccd32e22 | 8 | * Copyright (C) 2003 Red Hat |
bde18a2e KI |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, write to the Free Software Foundation, Inc., | |
22 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
23 | */ | |
24 | ||
25 | #include <linux/types.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/delay.h> | |
bde18a2e KI |
29 | #include <linux/ide.h> |
30 | #include <linux/init.h> | |
31 | ||
32 | #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 | |
33 | ||
34 | #define SCC_PATA_NAME "scc IDE" | |
35 | ||
36 | #define TDVHSEL_MASTER 0x00000001 | |
37 | #define TDVHSEL_SLAVE 0x00000004 | |
38 | ||
39 | #define MODE_JCUSFEN 0x00000080 | |
40 | ||
41 | #define CCKCTRL_ATARESET 0x00040000 | |
42 | #define CCKCTRL_BUFCNT 0x00020000 | |
43 | #define CCKCTRL_CRST 0x00010000 | |
44 | #define CCKCTRL_OCLKEN 0x00000100 | |
45 | #define CCKCTRL_ATACLKOEN 0x00000002 | |
46 | #define CCKCTRL_LCLKEN 0x00000001 | |
47 | ||
48 | #define QCHCD_IOS_SS 0x00000001 | |
49 | ||
50 | #define QCHSD_STPDIAG 0x00020000 | |
51 | ||
52 | #define INTMASK_MSK 0xD1000012 | |
53 | #define INTSTS_SERROR 0x80000000 | |
54 | #define INTSTS_PRERR 0x40000000 | |
55 | #define INTSTS_RERR 0x10000000 | |
56 | #define INTSTS_ICERR 0x01000000 | |
57 | #define INTSTS_BMSINT 0x00000010 | |
58 | #define INTSTS_BMHE 0x00000008 | |
59 | #define INTSTS_IOIRQS 0x00000004 | |
60 | #define INTSTS_INTRQ 0x00000002 | |
61 | #define INTSTS_ACTEINT 0x00000001 | |
62 | ||
63 | #define ECMODE_VALUE 0x01 | |
64 | ||
65 | static struct scc_ports { | |
66 | unsigned long ctl, dma; | |
48c3c107 | 67 | struct ide_host *host; /* for removing port from system */ |
bde18a2e KI |
68 | } scc_ports[MAX_HWIFS]; |
69 | ||
70 | /* PIO transfer mode table */ | |
71 | /* JCHST */ | |
72 | static unsigned long JCHSTtbl[2][7] = { | |
73 | {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ | |
74 | {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ | |
75 | }; | |
76 | ||
77 | /* JCHHT */ | |
78 | static unsigned long JCHHTtbl[2][7] = { | |
79 | {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ | |
80 | {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ | |
81 | }; | |
82 | ||
83 | /* JCHCT */ | |
84 | static unsigned long JCHCTtbl[2][7] = { | |
85 | {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ | |
86 | {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ | |
87 | }; | |
88 | ||
89 | ||
90 | /* DMA transfer mode table */ | |
91 | /* JCHDCTM/JCHDCTS */ | |
92 | static unsigned long JCHDCTxtbl[2][7] = { | |
93 | {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ | |
94 | {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ | |
95 | }; | |
96 | ||
97 | /* JCSTWTM/JCSTWTS */ | |
98 | static unsigned long JCSTWTxtbl[2][7] = { | |
99 | {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ | |
100 | {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
101 | }; | |
102 | ||
103 | /* JCTSS */ | |
104 | static unsigned long JCTSStbl[2][7] = { | |
105 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ | |
106 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ | |
107 | }; | |
108 | ||
109 | /* JCENVT */ | |
110 | static unsigned long JCENVTtbl[2][7] = { | |
111 | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ | |
112 | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
113 | }; | |
114 | ||
115 | /* JCACTSELS/JCACTSELM */ | |
116 | static unsigned long JCACTSELtbl[2][7] = { | |
117 | {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ | |
118 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ | |
119 | }; | |
120 | ||
121 | ||
122 | static u8 scc_ide_inb(unsigned long port) | |
123 | { | |
124 | u32 data = in_be32((void*)port); | |
125 | return (u8)data; | |
126 | } | |
127 | ||
c6dfa867 BZ |
128 | static void scc_exec_command(ide_hwif_t *hwif, u8 cmd) |
129 | { | |
130 | out_be32((void *)hwif->io_ports.command_addr, cmd); | |
131 | eieio(); | |
132 | in_be32((void *)(hwif->dma_base + 0x01c)); | |
133 | eieio(); | |
134 | } | |
135 | ||
b73c7ee2 BZ |
136 | static u8 scc_read_status(ide_hwif_t *hwif) |
137 | { | |
138 | return (u8)in_be32((void *)hwif->io_ports.status_addr); | |
139 | } | |
140 | ||
1f6d8a0f BZ |
141 | static u8 scc_read_altstatus(ide_hwif_t *hwif) |
142 | { | |
143 | return (u8)in_be32((void *)hwif->io_ports.ctl_addr); | |
144 | } | |
145 | ||
592b5315 | 146 | static u8 scc_dma_sff_read_status(ide_hwif_t *hwif) |
b2f951aa | 147 | { |
cab7f8ed | 148 | return (u8)in_be32((void *)(hwif->dma_base + 4)); |
b2f951aa BZ |
149 | } |
150 | ||
6e6afb3b BZ |
151 | static void scc_set_irq(ide_hwif_t *hwif, int on) |
152 | { | |
153 | u8 ctl = ATA_DEVCTL_OBS; | |
154 | ||
155 | if (on == 4) { /* hack for SRST */ | |
156 | ctl |= 4; | |
157 | on &= ~4; | |
158 | } | |
159 | ||
160 | ctl |= on ? 0 : 2; | |
161 | ||
162 | out_be32((void *)hwif->io_ports.ctl_addr, ctl); | |
163 | eieio(); | |
164 | in_be32((void *)(hwif->dma_base + 0x01c)); | |
165 | eieio(); | |
166 | } | |
167 | ||
bde18a2e KI |
168 | static void scc_ide_insw(unsigned long port, void *addr, u32 count) |
169 | { | |
170 | u16 *ptr = (u16 *)addr; | |
171 | while (count--) { | |
172 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
173 | } | |
174 | } | |
175 | ||
176 | static void scc_ide_insl(unsigned long port, void *addr, u32 count) | |
177 | { | |
178 | u16 *ptr = (u16 *)addr; | |
179 | while (count--) { | |
180 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
181 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
182 | } | |
183 | } | |
184 | ||
185 | static void scc_ide_outb(u8 addr, unsigned long port) | |
186 | { | |
187 | out_be32((void*)port, addr); | |
188 | } | |
189 | ||
bde18a2e KI |
190 | static void |
191 | scc_ide_outsw(unsigned long port, void *addr, u32 count) | |
192 | { | |
193 | u16 *ptr = (u16 *)addr; | |
194 | while (count--) { | |
195 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
196 | } | |
197 | } | |
198 | ||
199 | static void | |
200 | scc_ide_outsl(unsigned long port, void *addr, u32 count) | |
201 | { | |
202 | u16 *ptr = (u16 *)addr; | |
203 | while (count--) { | |
204 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
205 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
206 | } | |
207 | } | |
208 | ||
bde18a2e | 209 | /** |
88b2b32b BZ |
210 | * scc_set_pio_mode - set host controller for PIO mode |
211 | * @drive: drive | |
212 | * @pio: PIO mode number | |
bde18a2e KI |
213 | * |
214 | * Load the timing settings for this device mode into the | |
215 | * controller. | |
216 | */ | |
217 | ||
88b2b32b | 218 | static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio) |
bde18a2e | 219 | { |
898ec223 | 220 | ide_hwif_t *hwif = drive->hwif; |
bde18a2e KI |
221 | struct scc_ports *ports = ide_get_hwifdata(hwif); |
222 | unsigned long ctl_base = ports->ctl; | |
223 | unsigned long cckctrl_port = ctl_base + 0xff0; | |
224 | unsigned long piosht_port = ctl_base + 0x000; | |
225 | unsigned long pioct_port = ctl_base + 0x004; | |
226 | unsigned long reg; | |
bde18a2e KI |
227 | int offset; |
228 | ||
0ecdca26 | 229 | reg = in_be32((void __iomem *)cckctrl_port); |
bde18a2e KI |
230 | if (reg & CCKCTRL_ATACLKOEN) { |
231 | offset = 1; /* 133MHz */ | |
232 | } else { | |
233 | offset = 0; /* 100MHz */ | |
234 | } | |
3fcece66 | 235 | reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; |
0ecdca26 | 236 | out_be32((void __iomem *)piosht_port, reg); |
3fcece66 | 237 | reg = JCHCTtbl[offset][pio]; |
0ecdca26 | 238 | out_be32((void __iomem *)pioct_port, reg); |
3fcece66 | 239 | } |
bde18a2e | 240 | |
bde18a2e | 241 | /** |
88b2b32b BZ |
242 | * scc_set_dma_mode - set host controller for DMA mode |
243 | * @drive: drive | |
244 | * @speed: DMA mode | |
bde18a2e KI |
245 | * |
246 | * Load the timing settings for this device mode into the | |
247 | * controller. | |
248 | */ | |
249 | ||
88b2b32b | 250 | static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed) |
bde18a2e | 251 | { |
898ec223 | 252 | ide_hwif_t *hwif = drive->hwif; |
bde18a2e KI |
253 | struct scc_ports *ports = ide_get_hwifdata(hwif); |
254 | unsigned long ctl_base = ports->ctl; | |
255 | unsigned long cckctrl_port = ctl_base + 0xff0; | |
256 | unsigned long mdmact_port = ctl_base + 0x008; | |
257 | unsigned long mcrcst_port = ctl_base + 0x00c; | |
258 | unsigned long sdmact_port = ctl_base + 0x010; | |
259 | unsigned long scrcst_port = ctl_base + 0x014; | |
260 | unsigned long udenvt_port = ctl_base + 0x018; | |
261 | unsigned long tdvhsel_port = ctl_base + 0x020; | |
5e7f3a46 | 262 | int is_slave = drive->dn & 1; |
bde18a2e KI |
263 | int offset, idx; |
264 | unsigned long reg; | |
265 | unsigned long jcactsel; | |
266 | ||
0ecdca26 | 267 | reg = in_be32((void __iomem *)cckctrl_port); |
bde18a2e KI |
268 | if (reg & CCKCTRL_ATACLKOEN) { |
269 | offset = 1; /* 133MHz */ | |
270 | } else { | |
271 | offset = 0; /* 100MHz */ | |
272 | } | |
273 | ||
4db90a14 | 274 | idx = speed - XFER_UDMA_0; |
bde18a2e KI |
275 | |
276 | jcactsel = JCACTSELtbl[offset][idx]; | |
277 | if (is_slave) { | |
0ecdca26 BZ |
278 | out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]); |
279 | out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]); | |
280 | jcactsel = jcactsel << 2; | |
281 | out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel); | |
bde18a2e | 282 | } else { |
0ecdca26 BZ |
283 | out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]); |
284 | out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]); | |
285 | out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel); | |
bde18a2e KI |
286 | } |
287 | reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]; | |
0ecdca26 | 288 | out_be32((void __iomem *)udenvt_port, reg); |
bde18a2e KI |
289 | } |
290 | ||
669185e9 BZ |
291 | static void scc_dma_host_set(ide_drive_t *drive, int on) |
292 | { | |
293 | ide_hwif_t *hwif = drive->hwif; | |
123995b9 | 294 | u8 unit = drive->dn & 1; |
c2ce5ca0 | 295 | u8 dma_stat = scc_dma_sff_read_status(hwif); |
669185e9 BZ |
296 | |
297 | if (on) | |
298 | dma_stat |= (1 << (5 + unit)); | |
299 | else | |
300 | dma_stat &= ~(1 << (5 + unit)); | |
301 | ||
cab7f8ed | 302 | scc_ide_outb(dma_stat, hwif->dma_base + 4); |
669185e9 BZ |
303 | } |
304 | ||
0ecdca26 BZ |
305 | /** |
306 | * scc_ide_dma_setup - begin a DMA phase | |
307 | * @drive: target device | |
308 | * | |
309 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
310 | * and then set up the DMA transfer registers. | |
311 | * | |
312 | * Returns 0 on success. If a PIO fallback is required then 1 | |
313 | * is returned. | |
314 | */ | |
315 | ||
316 | static int scc_dma_setup(ide_drive_t *drive) | |
317 | { | |
318 | ide_hwif_t *hwif = drive->hwif; | |
b65fac32 | 319 | struct request *rq = hwif->rq; |
0ecdca26 BZ |
320 | unsigned int reading; |
321 | u8 dma_stat; | |
322 | ||
323 | if (rq_data_dir(rq)) | |
324 | reading = 0; | |
325 | else | |
326 | reading = 1 << 3; | |
327 | ||
328 | /* fall back to pio! */ | |
329 | if (!ide_build_dmatable(drive, rq)) { | |
330 | ide_map_sg(drive, rq); | |
331 | return 1; | |
332 | } | |
333 | ||
334 | /* PRD table */ | |
55224bc8 | 335 | out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma); |
0ecdca26 BZ |
336 | |
337 | /* specify r/w */ | |
cab7f8ed | 338 | out_be32((void __iomem *)hwif->dma_base, reading); |
0ecdca26 | 339 | |
cab7f8ed | 340 | /* read DMA status for INTR & ERROR flags */ |
c2ce5ca0 | 341 | dma_stat = scc_dma_sff_read_status(hwif); |
0ecdca26 BZ |
342 | |
343 | /* clear INTR & ERROR flags */ | |
cab7f8ed | 344 | out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6); |
0ecdca26 BZ |
345 | drive->waiting_for_dma = 1; |
346 | return 0; | |
347 | } | |
348 | ||
669185e9 BZ |
349 | static void scc_dma_start(ide_drive_t *drive) |
350 | { | |
351 | ide_hwif_t *hwif = drive->hwif; | |
cab7f8ed | 352 | u8 dma_cmd = scc_ide_inb(hwif->dma_base); |
669185e9 BZ |
353 | |
354 | /* start DMA */ | |
cab7f8ed | 355 | scc_ide_outb(dma_cmd | 1, hwif->dma_base); |
669185e9 BZ |
356 | wmb(); |
357 | } | |
358 | ||
359 | static int __scc_dma_end(ide_drive_t *drive) | |
360 | { | |
361 | ide_hwif_t *hwif = drive->hwif; | |
362 | u8 dma_stat, dma_cmd; | |
363 | ||
364 | drive->waiting_for_dma = 0; | |
365 | /* get DMA command mode */ | |
cab7f8ed | 366 | dma_cmd = scc_ide_inb(hwif->dma_base); |
669185e9 | 367 | /* stop DMA */ |
cab7f8ed | 368 | scc_ide_outb(dma_cmd & ~1, hwif->dma_base); |
669185e9 | 369 | /* get DMA status */ |
c2ce5ca0 | 370 | dma_stat = scc_dma_sff_read_status(hwif); |
669185e9 | 371 | /* clear the INTR & ERROR bits */ |
cab7f8ed | 372 | scc_ide_outb(dma_stat | 6, hwif->dma_base + 4); |
669185e9 BZ |
373 | /* purge DMA mappings */ |
374 | ide_destroy_dmatable(drive); | |
375 | /* verify good DMA status */ | |
669185e9 BZ |
376 | wmb(); |
377 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
378 | } | |
0ecdca26 | 379 | |
bde18a2e | 380 | /** |
5e37bdc0 | 381 | * scc_dma_end - Stop DMA |
bde18a2e KI |
382 | * @drive: IDE drive |
383 | * | |
384 | * Check and clear INT Status register. | |
669185e9 | 385 | * Then call __scc_dma_end(). |
bde18a2e KI |
386 | */ |
387 | ||
5e37bdc0 | 388 | static int scc_dma_end(ide_drive_t *drive) |
bde18a2e | 389 | { |
898ec223 | 390 | ide_hwif_t *hwif = drive->hwif; |
cab7f8ed | 391 | void __iomem *dma_base = (void __iomem *)hwif->dma_base; |
bde18a2e KI |
392 | unsigned long intsts_port = hwif->dma_base + 0x014; |
393 | u32 reg; | |
4ae41ff8 KI |
394 | int dma_stat, data_loss = 0; |
395 | static int retry = 0; | |
396 | ||
397 | /* errata A308 workaround: Step5 (check data loss) */ | |
398 | /* We don't check non ide_disk because it is limited to UDMA4 */ | |
4c3032d8 | 399 | if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr) |
3a7d2484 | 400 | & ATA_ERR) && |
4ae41ff8 KI |
401 | drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { |
402 | reg = in_be32((void __iomem *)intsts_port); | |
403 | if (!(reg & INTSTS_ACTEINT)) { | |
404 | printk(KERN_WARNING "%s: operation failed (transfer data loss)\n", | |
405 | drive->name); | |
406 | data_loss = 1; | |
407 | if (retry++) { | |
b65fac32 | 408 | struct request *rq = hwif->rq; |
2bd24a1c BZ |
409 | ide_drive_t *drive; |
410 | int i; | |
411 | ||
4ae41ff8 KI |
412 | /* ERROR_RESET and drive->crc_count are needed |
413 | * to reduce DMA transfer mode in retry process. | |
414 | */ | |
415 | if (rq) | |
416 | rq->errors |= ERROR_RESET; | |
5e7f3a46 | 417 | |
2bd24a1c | 418 | ide_port_for_each_dev(i, drive, hwif) |
4ae41ff8 | 419 | drive->crc_count++; |
4ae41ff8 KI |
420 | } |
421 | } | |
422 | } | |
bde18a2e KI |
423 | |
424 | while (1) { | |
0ecdca26 | 425 | reg = in_be32((void __iomem *)intsts_port); |
bde18a2e KI |
426 | |
427 | if (reg & INTSTS_SERROR) { | |
428 | printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); | |
0ecdca26 | 429 | out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); |
bde18a2e | 430 | |
cab7f8ed | 431 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
bde18a2e KI |
432 | continue; |
433 | } | |
434 | ||
435 | if (reg & INTSTS_PRERR) { | |
436 | u32 maea0, maec0; | |
437 | unsigned long ctl_base = hwif->config_data; | |
438 | ||
0ecdca26 BZ |
439 | maea0 = in_be32((void __iomem *)(ctl_base + 0xF50)); |
440 | maec0 = in_be32((void __iomem *)(ctl_base + 0xF54)); | |
bde18a2e KI |
441 | |
442 | printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0); | |
443 | ||
0ecdca26 | 444 | out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); |
bde18a2e | 445 | |
cab7f8ed | 446 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
bde18a2e KI |
447 | continue; |
448 | } | |
449 | ||
450 | if (reg & INTSTS_RERR) { | |
451 | printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); | |
0ecdca26 | 452 | out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); |
bde18a2e | 453 | |
cab7f8ed | 454 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
bde18a2e KI |
455 | continue; |
456 | } | |
457 | ||
458 | if (reg & INTSTS_ICERR) { | |
cab7f8ed | 459 | out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS); |
bde18a2e KI |
460 | |
461 | printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); | |
0ecdca26 | 462 | out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); |
bde18a2e KI |
463 | continue; |
464 | } | |
465 | ||
466 | if (reg & INTSTS_BMSINT) { | |
467 | printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME); | |
0ecdca26 | 468 | out_be32((void __iomem *)intsts_port, INTSTS_BMSINT); |
bde18a2e KI |
469 | |
470 | ide_do_reset(drive); | |
471 | continue; | |
472 | } | |
473 | ||
474 | if (reg & INTSTS_BMHE) { | |
0ecdca26 | 475 | out_be32((void __iomem *)intsts_port, INTSTS_BMHE); |
bde18a2e KI |
476 | continue; |
477 | } | |
478 | ||
479 | if (reg & INTSTS_ACTEINT) { | |
0ecdca26 | 480 | out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT); |
bde18a2e KI |
481 | continue; |
482 | } | |
483 | ||
484 | if (reg & INTSTS_IOIRQS) { | |
0ecdca26 | 485 | out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS); |
bde18a2e KI |
486 | continue; |
487 | } | |
488 | break; | |
489 | } | |
490 | ||
669185e9 | 491 | dma_stat = __scc_dma_end(drive); |
4ae41ff8 KI |
492 | if (data_loss) |
493 | dma_stat |= 2; /* emulate DMA error (to retry command) */ | |
494 | return dma_stat; | |
bde18a2e KI |
495 | } |
496 | ||
06a9952b AI |
497 | /* returns 1 if dma irq issued, 0 otherwise */ |
498 | static int scc_dma_test_irq(ide_drive_t *drive) | |
499 | { | |
898ec223 | 500 | ide_hwif_t *hwif = drive->hwif; |
4ae41ff8 | 501 | u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); |
06a9952b | 502 | |
4ae41ff8 | 503 | /* SCC errata A252,A308 workaround: Step4 */ |
4c3032d8 | 504 | if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr) |
3a7d2484 | 505 | & ATA_ERR) && |
4ae41ff8 | 506 | (int_stat & INTSTS_INTRQ)) |
06a9952b AI |
507 | return 1; |
508 | ||
4ae41ff8 KI |
509 | /* SCC errata A308 workaround: Step5 (polling IOIRQS) */ |
510 | if (int_stat & INTSTS_IOIRQS) | |
06a9952b AI |
511 | return 1; |
512 | ||
06a9952b AI |
513 | return 0; |
514 | } | |
515 | ||
4ae41ff8 KI |
516 | static u8 scc_udma_filter(ide_drive_t *drive) |
517 | { | |
518 | ide_hwif_t *hwif = drive->hwif; | |
519 | u8 mask = hwif->ultra_mask; | |
520 | ||
521 | /* errata A308 workaround: limit non ide_disk drive to UDMA4 */ | |
522 | if ((drive->media != ide_disk) && (mask & 0xE0)) { | |
523 | printk(KERN_INFO "%s: limit %s to UDMA4\n", | |
524 | SCC_PATA_NAME, drive->name); | |
5f8b6c34 | 525 | mask = ATA_UDMA4; |
4ae41ff8 KI |
526 | } |
527 | ||
528 | return mask; | |
529 | } | |
530 | ||
bde18a2e KI |
531 | /** |
532 | * setup_mmio_scc - map CTRL/BMID region | |
533 | * @dev: PCI device we are configuring | |
534 | * @name: device name | |
535 | * | |
536 | */ | |
537 | ||
538 | static int setup_mmio_scc (struct pci_dev *dev, const char *name) | |
539 | { | |
0bd8496b AV |
540 | void __iomem *ctl_addr; |
541 | void __iomem *dma_addr; | |
0d1bad21 | 542 | int i, ret; |
bde18a2e KI |
543 | |
544 | for (i = 0; i < MAX_HWIFS; i++) { | |
545 | if (scc_ports[i].ctl == 0) | |
546 | break; | |
547 | } | |
548 | if (i >= MAX_HWIFS) | |
549 | return -ENOMEM; | |
550 | ||
0d1bad21 BZ |
551 | ret = pci_request_selected_regions(dev, (1 << 2) - 1, name); |
552 | if (ret < 0) { | |
553 | printk(KERN_ERR "%s: can't reserve resources\n", name); | |
554 | return ret; | |
bde18a2e KI |
555 | } |
556 | ||
1f1ab274 AV |
557 | ctl_addr = pci_ioremap_bar(dev, 0); |
558 | if (!ctl_addr) | |
0d1bad21 | 559 | goto fail_0; |
bde18a2e | 560 | |
1f1ab274 AV |
561 | dma_addr = pci_ioremap_bar(dev, 1); |
562 | if (!dma_addr) | |
0d1bad21 | 563 | goto fail_1; |
bde18a2e KI |
564 | |
565 | pci_set_master(dev); | |
566 | scc_ports[i].ctl = (unsigned long)ctl_addr; | |
567 | scc_ports[i].dma = (unsigned long)dma_addr; | |
568 | pci_set_drvdata(dev, (void *) &scc_ports[i]); | |
569 | ||
570 | return 1; | |
571 | ||
bde18a2e | 572 | fail_1: |
0d1bad21 | 573 | iounmap(ctl_addr); |
bde18a2e KI |
574 | fail_0: |
575 | return -ENOMEM; | |
576 | } | |
577 | ||
3d53ba87 AI |
578 | static int scc_ide_setup_pci_device(struct pci_dev *dev, |
579 | const struct ide_port_info *d) | |
580 | { | |
581 | struct scc_ports *ports = pci_get_drvdata(dev); | |
48c3c107 | 582 | struct ide_host *host; |
c97c6aca | 583 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
6f904d01 | 584 | int i, rc; |
3d53ba87 | 585 | |
3d53ba87 | 586 | memset(&hw, 0, sizeof(hw)); |
4c3032d8 BZ |
587 | for (i = 0; i <= 8; i++) |
588 | hw.io_ports_array[i] = ports->dma + 0x20 + i * 4; | |
3d53ba87 AI |
589 | hw.irq = dev->irq; |
590 | hw.dev = &dev->dev; | |
591 | hw.chipset = ide_pci; | |
3d53ba87 | 592 | |
6f904d01 BZ |
593 | rc = ide_host_add(d, hws, &host); |
594 | if (rc) | |
595 | return rc; | |
48c3c107 BZ |
596 | |
597 | ports->host = host; | |
3d53ba87 AI |
598 | |
599 | return 0; | |
600 | } | |
601 | ||
bde18a2e KI |
602 | /** |
603 | * init_setup_scc - set up an SCC PATA Controller | |
604 | * @dev: PCI device | |
039788e1 | 605 | * @d: IDE port info |
bde18a2e KI |
606 | * |
607 | * Perform the initial set up for this device. | |
608 | */ | |
609 | ||
039788e1 | 610 | static int __devinit init_setup_scc(struct pci_dev *dev, |
85620436 | 611 | const struct ide_port_info *d) |
bde18a2e KI |
612 | { |
613 | unsigned long ctl_base; | |
614 | unsigned long dma_base; | |
615 | unsigned long cckctrl_port; | |
616 | unsigned long intmask_port; | |
617 | unsigned long mode_port; | |
618 | unsigned long ecmode_port; | |
bde18a2e KI |
619 | u32 reg = 0; |
620 | struct scc_ports *ports; | |
621 | int rc; | |
622 | ||
3d53ba87 AI |
623 | rc = pci_enable_device(dev); |
624 | if (rc) | |
625 | goto end; | |
626 | ||
bde18a2e | 627 | rc = setup_mmio_scc(dev, d->name); |
3d53ba87 AI |
628 | if (rc < 0) |
629 | goto end; | |
bde18a2e KI |
630 | |
631 | ports = pci_get_drvdata(dev); | |
632 | ctl_base = ports->ctl; | |
633 | dma_base = ports->dma; | |
634 | cckctrl_port = ctl_base + 0xff0; | |
635 | intmask_port = dma_base + 0x010; | |
636 | mode_port = ctl_base + 0x024; | |
637 | ecmode_port = ctl_base + 0xf00; | |
bde18a2e KI |
638 | |
639 | /* controller initialization */ | |
640 | reg = 0; | |
641 | out_be32((void*)cckctrl_port, reg); | |
642 | reg |= CCKCTRL_ATACLKOEN; | |
643 | out_be32((void*)cckctrl_port, reg); | |
644 | reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; | |
645 | out_be32((void*)cckctrl_port, reg); | |
646 | reg |= CCKCTRL_CRST; | |
647 | out_be32((void*)cckctrl_port, reg); | |
648 | ||
649 | for (;;) { | |
650 | reg = in_be32((void*)cckctrl_port); | |
651 | if (reg & CCKCTRL_CRST) | |
652 | break; | |
653 | udelay(5000); | |
654 | } | |
655 | ||
656 | reg |= CCKCTRL_ATARESET; | |
657 | out_be32((void*)cckctrl_port, reg); | |
658 | ||
659 | out_be32((void*)ecmode_port, ECMODE_VALUE); | |
660 | out_be32((void*)mode_port, MODE_JCUSFEN); | |
661 | out_be32((void*)intmask_port, INTMASK_MSK); | |
662 | ||
3d53ba87 AI |
663 | rc = scc_ide_setup_pci_device(dev, d); |
664 | ||
665 | end: | |
666 | return rc; | |
bde18a2e KI |
667 | } |
668 | ||
22aa4b32 | 669 | static void scc_tf_load(ide_drive_t *drive, struct ide_cmd *cmd) |
db2432c4 BZ |
670 | { |
671 | struct ide_io_ports *io_ports = &drive->hwif->io_ports; | |
22aa4b32 BZ |
672 | struct ide_taskfile *tf = &cmd->tf; |
673 | u8 HIHI = (cmd->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF; | |
db2432c4 | 674 | |
22aa4b32 | 675 | if (cmd->ftf_flags & IDE_FTFLAG_FLAGGED) |
db2432c4 BZ |
676 | HIHI = 0xFF; |
677 | ||
22aa4b32 | 678 | if (cmd->ftf_flags & IDE_FTFLAG_OUT_DATA) |
7c0daf26 BZ |
679 | out_be32((void *)io_ports->data_addr, |
680 | (tf->hob_data << 8) | tf->data); | |
db2432c4 | 681 | |
22aa4b32 | 682 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE) |
db2432c4 | 683 | scc_ide_outb(tf->hob_feature, io_ports->feature_addr); |
22aa4b32 | 684 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_NSECT) |
db2432c4 | 685 | scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr); |
22aa4b32 | 686 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAL) |
db2432c4 | 687 | scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr); |
22aa4b32 | 688 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAM) |
db2432c4 | 689 | scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr); |
22aa4b32 | 690 | if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAH) |
db2432c4 BZ |
691 | scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr); |
692 | ||
22aa4b32 | 693 | if (cmd->tf_flags & IDE_TFLAG_OUT_FEATURE) |
db2432c4 | 694 | scc_ide_outb(tf->feature, io_ports->feature_addr); |
22aa4b32 | 695 | if (cmd->tf_flags & IDE_TFLAG_OUT_NSECT) |
db2432c4 | 696 | scc_ide_outb(tf->nsect, io_ports->nsect_addr); |
22aa4b32 | 697 | if (cmd->tf_flags & IDE_TFLAG_OUT_LBAL) |
db2432c4 | 698 | scc_ide_outb(tf->lbal, io_ports->lbal_addr); |
22aa4b32 | 699 | if (cmd->tf_flags & IDE_TFLAG_OUT_LBAM) |
db2432c4 | 700 | scc_ide_outb(tf->lbam, io_ports->lbam_addr); |
22aa4b32 | 701 | if (cmd->tf_flags & IDE_TFLAG_OUT_LBAH) |
db2432c4 BZ |
702 | scc_ide_outb(tf->lbah, io_ports->lbah_addr); |
703 | ||
22aa4b32 | 704 | if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE) |
7f612f27 | 705 | scc_ide_outb((tf->device & HIHI) | drive->select, |
db2432c4 BZ |
706 | io_ports->device_addr); |
707 | } | |
708 | ||
22aa4b32 | 709 | static void scc_tf_read(ide_drive_t *drive, struct ide_cmd *cmd) |
db2432c4 BZ |
710 | { |
711 | struct ide_io_ports *io_ports = &drive->hwif->io_ports; | |
22aa4b32 | 712 | struct ide_taskfile *tf = &cmd->tf; |
db2432c4 | 713 | |
22aa4b32 | 714 | if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) { |
7c0daf26 | 715 | u16 data = (u16)in_be32((void *)io_ports->data_addr); |
db2432c4 BZ |
716 | |
717 | tf->data = data & 0xff; | |
718 | tf->hob_data = (data >> 8) & 0xff; | |
719 | } | |
720 | ||
721 | /* be sure we're looking at the low order bits */ | |
ff074883 | 722 | scc_ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); |
db2432c4 | 723 | |
22aa4b32 | 724 | if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE) |
92eb4380 | 725 | tf->feature = scc_ide_inb(io_ports->feature_addr); |
22aa4b32 | 726 | if (cmd->tf_flags & IDE_TFLAG_IN_NSECT) |
db2432c4 | 727 | tf->nsect = scc_ide_inb(io_ports->nsect_addr); |
22aa4b32 | 728 | if (cmd->tf_flags & IDE_TFLAG_IN_LBAL) |
db2432c4 | 729 | tf->lbal = scc_ide_inb(io_ports->lbal_addr); |
22aa4b32 | 730 | if (cmd->tf_flags & IDE_TFLAG_IN_LBAM) |
db2432c4 | 731 | tf->lbam = scc_ide_inb(io_ports->lbam_addr); |
22aa4b32 | 732 | if (cmd->tf_flags & IDE_TFLAG_IN_LBAH) |
db2432c4 | 733 | tf->lbah = scc_ide_inb(io_ports->lbah_addr); |
22aa4b32 | 734 | if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE) |
db2432c4 BZ |
735 | tf->device = scc_ide_inb(io_ports->device_addr); |
736 | ||
22aa4b32 | 737 | if (cmd->tf_flags & IDE_TFLAG_LBA48) { |
ff074883 | 738 | scc_ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr); |
db2432c4 | 739 | |
22aa4b32 | 740 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) |
db2432c4 | 741 | tf->hob_feature = scc_ide_inb(io_ports->feature_addr); |
22aa4b32 | 742 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT) |
db2432c4 | 743 | tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr); |
22aa4b32 | 744 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL) |
db2432c4 | 745 | tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr); |
22aa4b32 | 746 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM) |
db2432c4 | 747 | tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr); |
22aa4b32 | 748 | if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH) |
db2432c4 BZ |
749 | tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr); |
750 | } | |
751 | } | |
752 | ||
efa3db1b BZ |
753 | static void scc_input_data(ide_drive_t *drive, struct request *rq, |
754 | void *buf, unsigned int len) | |
755 | { | |
756 | unsigned long data_addr = drive->hwif->io_ports.data_addr; | |
757 | ||
758 | len++; | |
759 | ||
760 | if (drive->io_32bit) { | |
761 | scc_ide_insl(data_addr, buf, len / 4); | |
762 | ||
763 | if ((len & 3) >= 2) | |
764 | scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1); | |
765 | } else | |
766 | scc_ide_insw(data_addr, buf, len / 2); | |
767 | } | |
768 | ||
769 | static void scc_output_data(ide_drive_t *drive, struct request *rq, | |
770 | void *buf, unsigned int len) | |
771 | { | |
772 | unsigned long data_addr = drive->hwif->io_ports.data_addr; | |
773 | ||
774 | len++; | |
775 | ||
776 | if (drive->io_32bit) { | |
777 | scc_ide_outsl(data_addr, buf, len / 4); | |
778 | ||
779 | if ((len & 3) >= 2) | |
780 | scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1); | |
781 | } else | |
782 | scc_ide_outsw(data_addr, buf, len / 2); | |
783 | } | |
784 | ||
bde18a2e KI |
785 | /** |
786 | * init_mmio_iops_scc - set up the iops for MMIO | |
787 | * @hwif: interface to set up | |
788 | * | |
789 | */ | |
790 | ||
791 | static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif) | |
792 | { | |
36501650 | 793 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
bde18a2e KI |
794 | struct scc_ports *ports = pci_get_drvdata(dev); |
795 | unsigned long dma_base = ports->dma; | |
796 | ||
797 | ide_set_hwifdata(hwif, ports); | |
798 | ||
bde18a2e KI |
799 | hwif->dma_base = dma_base; |
800 | hwif->config_data = ports->ctl; | |
bde18a2e KI |
801 | } |
802 | ||
803 | /** | |
804 | * init_iops_scc - set up iops | |
805 | * @hwif: interface to set up | |
806 | * | |
807 | * Do the basic setup for the SCC hardware interface | |
808 | * and then do the MMIO setup. | |
809 | */ | |
810 | ||
811 | static void __devinit init_iops_scc(ide_hwif_t *hwif) | |
812 | { | |
36501650 BZ |
813 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
814 | ||
bde18a2e KI |
815 | hwif->hwif_data = NULL; |
816 | if (pci_get_drvdata(dev) == NULL) | |
817 | return; | |
818 | init_mmio_iops_scc(hwif); | |
819 | } | |
820 | ||
2bbd57ca BZ |
821 | static int __devinit scc_init_dma(ide_hwif_t *hwif, |
822 | const struct ide_port_info *d) | |
823 | { | |
824 | return ide_allocate_dma_engine(hwif); | |
825 | } | |
826 | ||
f454cbe8 | 827 | static u8 scc_cable_detect(ide_hwif_t *hwif) |
b4d1c73d BZ |
828 | { |
829 | return ATA_CBL_PATA80; | |
830 | } | |
831 | ||
bde18a2e KI |
832 | /** |
833 | * init_hwif_scc - set up hwif | |
834 | * @hwif: interface to set up | |
835 | * | |
836 | * We do the basic set up of the interface structure. The SCC | |
837 | * requires several custom handlers so we override the default | |
838 | * ide DMA handlers appropriately. | |
839 | */ | |
840 | ||
841 | static void __devinit init_hwif_scc(ide_hwif_t *hwif) | |
842 | { | |
0ecdca26 BZ |
843 | /* PTERADD */ |
844 | out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); | |
bde18a2e | 845 | |
5f8b6c34 BZ |
846 | if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) |
847 | hwif->ultra_mask = ATA_UDMA6; /* 133MHz */ | |
848 | else | |
849 | hwif->ultra_mask = ATA_UDMA5; /* 100MHz */ | |
bde18a2e KI |
850 | } |
851 | ||
374e042c BZ |
852 | static const struct ide_tp_ops scc_tp_ops = { |
853 | .exec_command = scc_exec_command, | |
854 | .read_status = scc_read_status, | |
855 | .read_altstatus = scc_read_altstatus, | |
374e042c BZ |
856 | |
857 | .set_irq = scc_set_irq, | |
858 | ||
859 | .tf_load = scc_tf_load, | |
860 | .tf_read = scc_tf_read, | |
861 | ||
862 | .input_data = scc_input_data, | |
863 | .output_data = scc_output_data, | |
864 | }; | |
865 | ||
ac95beed BZ |
866 | static const struct ide_port_ops scc_port_ops = { |
867 | .set_pio_mode = scc_set_pio_mode, | |
868 | .set_dma_mode = scc_set_dma_mode, | |
869 | .udma_filter = scc_udma_filter, | |
870 | .cable_detect = scc_cable_detect, | |
871 | }; | |
872 | ||
f37afdac | 873 | static const struct ide_dma_ops scc_dma_ops = { |
669185e9 | 874 | .dma_host_set = scc_dma_host_set, |
5e37bdc0 | 875 | .dma_setup = scc_dma_setup, |
f37afdac | 876 | .dma_exec_cmd = ide_dma_exec_cmd, |
669185e9 | 877 | .dma_start = scc_dma_start, |
5e37bdc0 BZ |
878 | .dma_end = scc_dma_end, |
879 | .dma_test_irq = scc_dma_test_irq, | |
f37afdac BZ |
880 | .dma_lost_irq = ide_dma_lost_irq, |
881 | .dma_timeout = ide_dma_timeout, | |
592b5315 | 882 | .dma_sff_read_status = scc_dma_sff_read_status, |
5e37bdc0 BZ |
883 | }; |
884 | ||
304ffd6d BZ |
885 | static const struct ide_port_info scc_chipset __devinitdata = { |
886 | .name = "sccIDE", | |
887 | .init_iops = init_iops_scc, | |
888 | .init_dma = scc_init_dma, | |
889 | .init_hwif = init_hwif_scc, | |
890 | .tp_ops = &scc_tp_ops, | |
891 | .port_ops = &scc_port_ops, | |
892 | .dma_ops = &scc_dma_ops, | |
893 | .host_flags = IDE_HFLAG_SINGLE, | |
255115fb | 894 | .irq_flags = IRQF_SHARED, |
304ffd6d | 895 | .pio_mask = ATA_PIO4, |
bde18a2e KI |
896 | }; |
897 | ||
898 | /** | |
899 | * scc_init_one - pci layer discovery entry | |
900 | * @dev: PCI device | |
901 | * @id: ident table entry | |
902 | * | |
903 | * Called by the PCI code when it finds an SCC PATA controller. | |
904 | * We then use the IDE PCI generic helper to do most of the work. | |
905 | */ | |
906 | ||
907 | static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
908 | { | |
304ffd6d | 909 | return init_setup_scc(dev, &scc_chipset); |
bde18a2e KI |
910 | } |
911 | ||
912 | /** | |
913 | * scc_remove - pci layer remove entry | |
914 | * @dev: PCI device | |
915 | * | |
916 | * Called by the PCI code when it removes an SCC PATA controller. | |
917 | */ | |
918 | ||
919 | static void __devexit scc_remove(struct pci_dev *dev) | |
920 | { | |
921 | struct scc_ports *ports = pci_get_drvdata(dev); | |
48c3c107 | 922 | struct ide_host *host = ports->host; |
bde18a2e | 923 | |
48c3c107 | 924 | ide_host_remove(host); |
bde18a2e | 925 | |
bde18a2e KI |
926 | iounmap((void*)ports->dma); |
927 | iounmap((void*)ports->ctl); | |
0d1bad21 | 928 | pci_release_selected_regions(dev, (1 << 2) - 1); |
bde18a2e KI |
929 | memset(ports, 0, sizeof(*ports)); |
930 | } | |
931 | ||
9cbcc5e3 BZ |
932 | static const struct pci_device_id scc_pci_tbl[] = { |
933 | { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 }, | |
bde18a2e KI |
934 | { 0, }, |
935 | }; | |
936 | MODULE_DEVICE_TABLE(pci, scc_pci_tbl); | |
937 | ||
a9ab09e2 | 938 | static struct pci_driver scc_pci_driver = { |
bde18a2e KI |
939 | .name = "SCC IDE", |
940 | .id_table = scc_pci_tbl, | |
941 | .probe = scc_init_one, | |
a69999e2 | 942 | .remove = __devexit_p(scc_remove), |
bde18a2e KI |
943 | }; |
944 | ||
945 | static int scc_ide_init(void) | |
946 | { | |
a9ab09e2 | 947 | return ide_pci_register_driver(&scc_pci_driver); |
bde18a2e KI |
948 | } |
949 | ||
950 | module_init(scc_ide_init); | |
951 | /* -- No exit code? | |
952 | static void scc_ide_exit(void) | |
953 | { | |
a9ab09e2 | 954 | ide_pci_unregister_driver(&scc_pci_driver); |
bde18a2e KI |
955 | } |
956 | module_exit(scc_ide_exit); | |
957 | */ | |
958 | ||
959 | ||
960 | MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE"); | |
961 | MODULE_LICENSE("GPL"); |