[mirror_ubuntu-hirsute-kernel.git] / drivers / ide / serverworks.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
 *   controller same as the CSB6. Single channel ATA100 only.
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "serverworks"

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */
static const char *svwks_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

static int check_in_drive_lists (ide_drive_t *drive, const char **list)
{
	char *m = (char *)&drive->id[ATA_ID_PROD];

	while (*list)
		if (!strcmp(*list++, m))
			return 1;
	return 0;
}

static u8 svwks_udma_filter(ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);

	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
		return 0x1f;
	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
		return 0x07;
	} else {
		u8 btr = 0, mode, mask;

		pci_read_config_byte(dev, 0x5A, &btr);
		mode = btr & 0x3;

		/* If someone decides to do UDMA133 on CSB5 the same
		   issue will bite so be inclusive */
		if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
			mode = 2;

		switch(mode) {
		case 3:	 mask = 0x3f; break;
		case 2:	 mask = 0x1f; break;
		case 1:	 mask = 0x07; break;
		default: mask = 0x00; break;
		}

		return mask;
	}
}

static u8 svwks_csb_check (struct pci_dev *dev)
{
	switch (dev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}

static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };

	struct pci_dev *dev = to_pci_dev(hwif->dev);
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	if (drive->dn >= ARRAY_SIZE(drive_pci))
		return;

	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);

	if (svwks_csb_check(dev)) {
		u16 csb_pio = 0;

		pci_read_config_word(dev, 0x4a, &csb_pio);

		csb_pio &= ~(0x0f << (4 * drive->dn));
		csb_pio |= (pio << (4 * drive->dn));

		pci_write_config_word(dev, 0x4a, csb_pio);
	}
}

static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	static const u8 udma_modes[]		= { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
	static const u8 dma_modes[]		= { 0x77, 0x21, 0x20 };
	static const u8 drive_pci2[]		= { 0x45, 0x44, 0x47, 0x46 };

	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	const u8 speed		= drive->dma_mode;
	u8 unit			= drive->dn & 1;

	u8 ultra_enable	 = 0, ultra_timing = 0, dma_timing = 0;

	if (drive->dn >= ARRAY_SIZE(drive_pci2))
		return;

	pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
	pci_read_config_byte(dev, 0x54, &ultra_enable);

	ultra_timing	&= ~(0x0F << (4*unit));
	ultra_enable	&= ~(0x01 << drive->dn);

	if (speed >= XFER_UDMA_0) {
		dma_timing   |= dma_modes[2];
		ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
		ultra_enable |= (0x01 << drive->dn);
	} else if (speed >= XFER_MW_DMA_0)
		dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];

	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
	pci_write_config_byte(dev, 0x54, ultra_enable);
}

static int init_chipset_svwks(struct pci_dev *dev)
{
	unsigned int reg;
	u8 btr;

	/* force Master Latency Timer value to 64 PCICLKs */
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);

	/* OSB4 : South Bridge and IDE */
	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		struct pci_dev *isa_dev =
			pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
					PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
		if (isa_dev) {
			pci_read_config_dword(isa_dev, 0x64, &reg);
			reg &= ~0x00002000; /* disable 600ns interrupt mask */
			if(!(reg & 0x00004000))
				printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
					"enabled.\n", pci_name(dev));
			reg |=  0x00004000; /* enable UDMA/33 support */
			pci_write_config_dword(isa_dev, 0x64, reg);
			pci_dev_put(isa_dev);
		}
	}

	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		/* Third Channel Test */
		if (!(PCI_FUNC(dev->devfn) & 1)) {
			struct pci_dev * findev = NULL;
			u32 reg4c = 0;
			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
			if (findev) {
				pci_read_config_dword(findev, 0x4C, &reg4c);
				reg4c &= ~0x000007FF;
				reg4c |=  0x00000040;
				reg4c |=  0x00000020;
				pci_write_config_dword(findev, 0x4C, reg4c);
				pci_dev_put(findev);
			}
			outb_p(0x06, 0x0c00);
			dev->irq = inb_p(0x0c01);
		} else {
			struct pci_dev * findev = NULL;
			u8 reg41 = 0;

			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
					PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
			if (findev) {
				pci_read_config_byte(findev, 0x41, &reg41);
				reg41 &= ~0x40;
				pci_write_config_byte(findev, 0x41, reg41);
				pci_dev_put(findev);
			}
			/*
			 * This is a device pin issue on CSB6.
			 * Since there will be a future raid mode,
			 * early versions of the chipset require the
			 * interrupt pin to be set, and it is a compatibility
			 * mode issue.
			 */
			if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
				dev->irq = 0;
		}
//		pci_read_config_dword(dev, 0x40, &pioreg)
//		pci_write_config_dword(dev, 0x40, 0x99999999);
//		pci_read_config_dword(dev, 0x44, &dmareg);
//		pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
		/* setup the UDMA Control register
		 *
		 * 1. clear bit 6 to enable DMA
		 * 2. enable DMA modes with bits 0-1
		 * 	00 : legacy
		 * 	01 : udma2
		 * 	10 : udma2/udma4
		 * 	11 : udma2/udma4/udma5
		 */
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		if (!(PCI_FUNC(dev->devfn) & 1))
			btr |= 0x2;
		else
			btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
		pci_write_config_byte(dev, 0x5A, btr);
	}
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		btr |= 0x3;
		pci_write_config_byte(dev, 0x5A, btr);
	}

	return 0;
}

static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
{
	return ATA_CBL_PATA80;
}

/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 * of the subsystem device ID indicate presence of an 80-pin cable.
 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 * Bit 15 set   = secondary IDE channel has 80-pin cable.
 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 * Bit 14 set   = primary IDE channel has 80-pin cable.
 */
static u8 ata66_svwks_dell(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
	     dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	return ATA_CBL_PATA40;
}

/* Sun Cobalt Alpine hardware avoids the 80-pin cable
 * detect issue by attaching the drives directly to the board.
 * This check follows the Dell precedent (how scary is that?!)
 *
 * WARNING: this only works on Alpine hardware!
 */
static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	return ATA_CBL_PATA40;
}

static u8 svwks_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	/* Server Works */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
		return ata66_svwks_svwks (hwif);
	
	/* Dell PowerEdge */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
		return ata66_svwks_dell (hwif);

	/* Cobalt Alpine */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
		return ata66_svwks_cobalt (hwif);

	/* Per Specified Design by OEM, and ASIC Architect */
	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
		return ATA_CBL_PATA80;

	return ATA_CBL_PATA40;
}

static const struct ide_port_ops osb4_port_ops = {
	.set_pio_mode		= svwks_set_pio_mode,
	.set_dma_mode		= svwks_set_dma_mode,
};

static const struct ide_port_ops svwks_port_ops = {
	.set_pio_mode		= svwks_set_pio_mode,
	.set_dma_mode		= svwks_set_dma_mode,
	.udma_filter		= svwks_udma_filter,
	.cable_detect		= svwks_cable_detect,
};

static const struct ide_port_info serverworks_chipsets[] = {
	{	/* 0: OSB4 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &osb4_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* UDMA is problematic on OSB4 */
	},
	{	/* 1: CSB5 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 2: CSB6 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 3: CSB6-2 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 4: HT1000 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

/**
 *	svwks_init_one	-	called when a OSB/CSB is found
 *	@dev: the svwks device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = serverworks_chipsets[idx];

	if (idx == 1)
		d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
	else if (idx == 2 || idx == 3) {
		if ((PCI_FUNC(dev->devfn) & 1) == 0) {
			if (pci_resource_start(dev, 0) != 0x01f1)
				d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
			d.host_flags |= IDE_HFLAG_SINGLE;
		} else
			d.host_flags &= ~IDE_HFLAG_SINGLE;
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id svwks_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);

static struct pci_driver svwks_pci_driver = {
	.name		= "Serverworks_IDE",
	.id_table	= svwks_pci_tbl,
	.probe		= svwks_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init svwks_ide_init(void)
{
	return ide_pci_register_driver(&svwks_pci_driver);
}

static void __exit svwks_ide_exit(void)
{
	pci_unregister_driver(&svwks_pci_driver);
}

module_init(svwks_ide_init);
module_exit(svwks_ide_exit);

MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4	2	/*
1da177e4 LT	3	* Copyright (C) 1998-2000 Michel Aubry
	4	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	5	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
e7593af6	6	* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
1da177e4 LT	7	* Portions copyright (c) 2001 Sun Microsystems
	8	*
	9	*
	10	* RCC/ServerWorks IDE driver for Linux
	11	*
	12	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	13	* supports UDMA mode 2 (33 MB/s)
	14	*
	15	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	16	* all revisions support UDMA mode 4 (66 MB/s)
	17	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	18	*
	19	* * The CSB5 does not provide ANY register *
	20	* * to detect 80-conductor cable presence. *
	21	*
	22	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	23	*
84f57fbc NS	24	* HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
	25	* controller same as the CSB6. Single channel ATA100 only.
	26	*
1da177e4 LT	27	* Documentation:
	28	* Available under NDA only. Errata info very hard to get.
	29	*
	30	*/
	31
1da177e4 LT	32	#include <linux/types.h>
	33	#include <linux/module.h>
	34	#include <linux/kernel.h>
1da177e4	35	#include <linux/pci.h>
1da177e4 LT	36	#include <linux/ide.h>
1da177e4 LT	37	#include <linux/init.h>
1da177e4 LT	38
	39	#include <asm/io.h>
	40
ced3ec8a BZ	41	#define DRV_NAME "serverworks"
ced3ec8a BZ	42
1da177e4 LT	43	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	44	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	45
	46	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	47	* can overrun their FIFOs when used with the CSB5 */
	48	static const char *svwks_bad_ata100[] = {
	49	"ST320011A",
	50	"ST340016A",
	51	"ST360021A",
	52	"ST380021A",
	53	NULL
	54	};
	55
1da177e4 LT	56	static int check_in_drive_lists (ide_drive_t drive, const char *list)
1da177e4 LT	57	{
4dde4492 BZ	58	char m = (char )&drive->id[ATA_ID_PROD];
4dde4492 BZ	59
1da177e4	60	while (*list)
4dde4492	61	if (!strcmp(*list++, m))
1da177e4 LT	62	return 1;
	63	return 0;
	64	}
	65
2d5eaa6d	66	static u8 svwks_udma_filter(ide_drive_t *drive)
1da177e4	67	{
36501650	68	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4	69
e7593af6	70	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
2d5eaa6d	71	return 0x1f;
44c10138	72	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
2d5eaa6d	73	return 0x07;
e7593af6 BZ	74	} else {
	75	u8 btr = 0, mode, mask;
	76
1da177e4 LT	77	pci_read_config_byte(dev, 0x5A, &btr);
1da177e4 LT	78	mode = btr & 0x3;
2d5eaa6d	79
1da177e4 LT	80	/* If someone decides to do UDMA133 on CSB5 the same
	81	issue will bite so be inclusive */
	82	if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
	83	mode = 2;
2d5eaa6d BZ	84
2d5eaa6d BZ	85	switch(mode) {
0c824b51	86	case 3: mask = 0x3f; break;
2d5eaa6d BZ	87	case 2: mask = 0x1f; break;
	88	case 1: mask = 0x07; break;
	89	default: mask = 0x00; break;
	90	}
2d5eaa6d	91
e7593af6 BZ	92	return mask;
e7593af6 BZ	93	}
1da177e4 LT	94	}
	95
	96	static u8 svwks_csb_check (struct pci_dev *dev)
	97	{
	98	switch (dev->device) {
	99	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	100	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	101	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
84f57fbc	102	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
1da177e4 LT	103	return 1;
	104	default:
	105	break;
	106	}
	107	return 0;
	108	}
1880a8d7	109
e085b3ca	110	static void svwks_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1880a8d7 BZ	111	{
	112	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	113	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
	114
e085b3ca BZ	115	struct pci_dev *dev = to_pci_dev(hwif->dev);
e085b3ca BZ	116	const u8 pio = drive->pio_mode - XFER_PIO_0;
1880a8d7	117
ce1f31b4 DC	118	if (drive->dn >= ARRAY_SIZE(drive_pci))
	119	return;
	120
1880a8d7 BZ	121	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
	122
	123	if (svwks_csb_check(dev)) {
	124	u16 csb_pio = 0;
	125
	126	pci_read_config_word(dev, 0x4a, &csb_pio);
	127
	128	csb_pio &= ~(0x0f << (4 * drive->dn));
	129	csb_pio \|= (pio << (4 * drive->dn));
	130
	131	pci_write_config_word(dev, 0x4a, csb_pio);
	132	}
	133	}
	134
8776168c	135	static void svwks_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	136	{
f201f504 AC	137	static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
f201f504 AC	138	static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
f201f504	139	static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
1da177e4	140
36501650	141	struct pci_dev *dev = to_pci_dev(hwif->dev);
8776168c	142	const u8 speed = drive->dma_mode;
123995b9	143	u8 unit = drive->dn & 1;
1880a8d7 BZ	144
	145	u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
	146
ce1f31b4 DC	147	if (drive->dn >= ARRAY_SIZE(drive_pci2))
	148	return;
	149
1da177e4	150	pci_read_config_byte(dev, (0x56\|hwif->channel), &ultra_timing);
1da177e4 LT	151	pci_read_config_byte(dev, 0x54, &ultra_enable);
1da177e4 LT	152
1da177e4 LT	153	ultra_timing &= ~(0x0F << (4*unit));
1da177e4 LT	154	ultra_enable &= ~(0x01 << drive->dn);
1da177e4	155
7b971df1 BZ	156	if (speed >= XFER_UDMA_0) {
	157	dma_timing \|= dma_modes[2];
	158	ultra_timing \|= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
	159	ultra_enable \|= (0x01 << drive->dn);
	160	} else if (speed >= XFER_MW_DMA_0)
	161	dma_timing \|= dma_modes[speed - XFER_MW_DMA_0];
1da177e4	162
1da177e4 LT	163	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	164	pci_write_config_byte(dev, (0x56\|hwif->channel), ultra_timing);
	165	pci_write_config_byte(dev, 0x54, ultra_enable);
1da177e4 LT	166	}
1da177e4 LT	167
2ed0ef54	168	static int init_chipset_svwks(struct pci_dev *dev)
1da177e4 LT	169	{
	170	unsigned int reg;
	171	u8 btr;
	172
1da177e4 LT	173	/* force Master Latency Timer value to 64 PCICLKs */
	174	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
	175
	176	/* OSB4 : South Bridge and IDE */
	177	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
e7593af6 BZ	178	struct pci_dev *isa_dev =
	179	pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	180	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
1da177e4 LT	181	if (isa_dev) {
	182	pci_read_config_dword(isa_dev, 0x64, &reg);
	183	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	184	if(!(reg & 0x00004000))
a326b02b BZ	185	printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
a326b02b BZ	186	"enabled.\n", pci_name(dev));
1da177e4 LT	187	reg \|= 0x00004000; /* enable UDMA/33 support */
1da177e4 LT	188	pci_write_config_dword(isa_dev, 0x64, reg);
cb06fc3f	189	pci_dev_put(isa_dev);
1da177e4 LT	190	}
	191	}
	192
	193	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	194	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	195	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	196	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
	197
	198	/* Third Channel Test */
	199	if (!(PCI_FUNC(dev->devfn) & 1)) {
	200	struct pci_dev * findev = NULL;
	201	u32 reg4c = 0;
970a6136	202	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	203	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	204	if (findev) {
	205	pci_read_config_dword(findev, 0x4C, &reg4c);
	206	reg4c &= ~0x000007FF;
	207	reg4c \|= 0x00000040;
	208	reg4c \|= 0x00000020;
	209	pci_write_config_dword(findev, 0x4C, reg4c);
970a6136	210	pci_dev_put(findev);
1da177e4 LT	211	}
	212	outb_p(0x06, 0x0c00);
	213	dev->irq = inb_p(0x0c01);
1da177e4 LT	214	} else {
	215	struct pci_dev * findev = NULL;
	216	u8 reg41 = 0;
	217
970a6136	218	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	219	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	220	if (findev) {
	221	pci_read_config_byte(findev, 0x41, &reg41);
	222	reg41 &= ~0x40;
	223	pci_write_config_byte(findev, 0x41, reg41);
970a6136	224	pci_dev_put(findev);
1da177e4 LT	225	}
	226	/*
	227	* This is a device pin issue on CSB6.
	228	* Since there will be a future raid mode,
	229	* early versions of the chipset require the
	230	* interrupt pin to be set, and it is a compatibility
	231	* mode issue.
	232	*/
	233	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
	234	dev->irq = 0;
	235	}
	236	// pci_read_config_dword(dev, 0x40, &pioreg)
	237	// pci_write_config_dword(dev, 0x40, 0x99999999);
	238	// pci_read_config_dword(dev, 0x44, &dmareg);
	239	// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
	240	/* setup the UDMA Control register
	241	*
	242	* 1. clear bit 6 to enable DMA
	243	* 2. enable DMA modes with bits 0-1
	244	* 00 : legacy
	245	* 01 : udma2
	246	* 10 : udma2/udma4
	247	* 11 : udma2/udma4/udma5
	248	*/
	249	pci_read_config_byte(dev, 0x5A, &btr);
	250	btr &= ~0x40;
	251	if (!(PCI_FUNC(dev->devfn) & 1))
	252	btr \|= 0x2;
	253	else
44c10138	254	btr \|= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
1da177e4 LT	255	pci_write_config_byte(dev, 0x5A, btr);
1da177e4 LT	256	}
84f57fbc NS	257	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	258	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
	259	pci_read_config_byte(dev, 0x5A, &btr);
	260	btr &= ~0x40;
	261	btr \|= 0x3;
	262	pci_write_config_byte(dev, 0x5A, btr);
	263	}
1da177e4	264
2ed0ef54	265	return 0;
1da177e4 LT	266	}
1da177e4 LT	267
f454cbe8	268	static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
1da177e4	269	{
49521f97	270	return ATA_CBL_PATA80;
1da177e4 LT	271	}
	272
	273	/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
	274	* of the subsystem device ID indicate presence of an 80-pin cable.
	275	* Bit 15 clear = secondary IDE channel does not have 80-pin cable.
	276	* Bit 15 set = secondary IDE channel has 80-pin cable.
	277	* Bit 14 clear = primary IDE channel does not have 80-pin cable.
	278	* Bit 14 set = primary IDE channel has 80-pin cable.
	279	*/
f454cbe8	280	static u8 ata66_svwks_dell(ide_hwif_t *hwif)
1da177e4	281	{
36501650 BZ	282	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	283
1da177e4 LT	284	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	285	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	286	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE \|\|
	287	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
	288	return ((1 << (hwif->channel + 14)) &
49521f97 BZ	289	dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
49521f97 BZ	290	return ATA_CBL_PATA40;
1da177e4 LT	291	}
	292
	293	/* Sun Cobalt Alpine hardware avoids the 80-pin cable
	294	* detect issue by attaching the drives directly to the board.
	295	* This check follows the Dell precedent (how scary is that?!)
	296	*
	297	* WARNING: this only works on Alpine hardware!
	298	*/
f454cbe8	299	static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
1da177e4	300	{
36501650 BZ	301	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	302
1da177e4 LT	303	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	304	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	305	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
	306	return ((1 << (hwif->channel + 14)) &
49521f97 BZ	307	dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
49521f97 BZ	308	return ATA_CBL_PATA40;
1da177e4 LT	309	}
1da177e4 LT	310
f454cbe8	311	static u8 svwks_cable_detect(ide_hwif_t *hwif)
1da177e4	312	{
36501650	313	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	314
1da177e4 LT	315	/* Server Works */
	316	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
	317	return ata66_svwks_svwks (hwif);
	318
	319	/* Dell PowerEdge */
	320	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
	321	return ata66_svwks_dell (hwif);
	322
	323	/* Cobalt Alpine */
	324	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
	325	return ata66_svwks_cobalt (hwif);
	326
f201f504 AC	327	/* Per Specified Design by OEM, and ASIC Architect */
	328	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	329	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
49521f97	330	return ATA_CBL_PATA80;
f201f504	331
49521f97	332	return ATA_CBL_PATA40;
1da177e4 LT	333	}
1da177e4 LT	334
ac95beed BZ	335	static const struct ide_port_ops osb4_port_ops = {
	336	.set_pio_mode = svwks_set_pio_mode,
	337	.set_dma_mode = svwks_set_dma_mode,
ac95beed	338	};
1da177e4	339
ac95beed BZ	340	static const struct ide_port_ops svwks_port_ops = {
	341	.set_pio_mode = svwks_set_pio_mode,
	342	.set_dma_mode = svwks_set_dma_mode,
	343	.udma_filter = svwks_udma_filter,
	344	.cable_detect = svwks_cable_detect,
	345	};
1da177e4	346
fe31edc8	347	static const struct ide_port_info serverworks_chipsets[] = {
ced3ec8a BZ	348	{ /* 0: OSB4 */
ced3ec8a BZ	349	.name = DRV_NAME,
1da177e4	350	.init_chipset = init_chipset_svwks,
ac95beed	351	.port_ops = &osb4_port_ops,
4099d143	352	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	353	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	354	.udma_mask = 0x00, /* UDMA is problematic on OSB4 */
ced3ec8a BZ	355	},
	356	{ /* 1: CSB5 */
	357	.name = DRV_NAME,
1da177e4	358	.init_chipset = init_chipset_svwks,
ac95beed	359	.port_ops = &svwks_port_ops,
4099d143	360	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	361	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	362	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	363	},
	364	{ /* 2: CSB6 */
	365	.name = DRV_NAME,
1da177e4	366	.init_chipset = init_chipset_svwks,
ac95beed	367	.port_ops = &svwks_port_ops,
4099d143	368	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	369	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	370	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	371	},
	372	{ /* 3: CSB6-2 */
	373	.name = DRV_NAME,
1da177e4	374	.init_chipset = init_chipset_svwks,
ac95beed	375	.port_ops = &svwks_port_ops,
2467922a	376	.host_flags = IDE_HFLAG_SINGLE,
4099d143	377	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	378	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	379	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	380	},
	381	{ /* 4: HT1000 */
	382	.name = DRV_NAME,
84f57fbc	383	.init_chipset = init_chipset_svwks,
ac95beed	384	.port_ops = &svwks_port_ops,
2467922a	385	.host_flags = IDE_HFLAG_SINGLE,
4099d143	386	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	387	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	388	.udma_mask = ATA_UDMA5,
1da177e4 LT	389	}
	390	};
	391
	392	/**
	393	* svwks_init_one - called when a OSB/CSB is found
	394	* @dev: the svwks device
	395	* @id: the matching pci id
	396	*
	397	* Called when the PCI registration layer (or the IDE initialization)
	398	* finds a device matching our IDE device tables.
	399	*/
	400
fe31edc8	401	static int svwks_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	402	{
039788e1	403	struct ide_port_info d;
7ed58297 BZ	404	u8 idx = id->driver_data;
	405
	406	d = serverworks_chipsets[idx];
	407
8ac2b42a BZ	408	if (idx == 1)
	409	d.host_flags \|= IDE_HFLAG_CLEAR_SIMPLEX;
	410	else if (idx == 2 \|\| idx == 3) {
7ed58297 BZ	411	if ((PCI_FUNC(dev->devfn) & 1) == 0) {
7ed58297 BZ	412	if (pci_resource_start(dev, 0) != 0x01f1)
5e71d9c5	413	d.host_flags \|= IDE_HFLAG_NON_BOOTABLE;
7ed58297 BZ	414	d.host_flags \|= IDE_HFLAG_SINGLE;
	415	} else
	416	d.host_flags &= ~IDE_HFLAG_SINGLE;
	417	}
1da177e4	418
6cdf6eb3	419	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	420	}
1da177e4 LT	421
9cbcc5e3 BZ	422	static const struct pci_device_id svwks_pci_tbl[] = {
	423	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
	424	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
	425	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
	426	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
	427	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
1da177e4 LT	428	{ 0, },
	429	};
	430	MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
	431
a9ab09e2	432	static struct pci_driver svwks_pci_driver = {
1da177e4 LT	433	.name = "Serverworks_IDE",
	434	.id_table = svwks_pci_tbl,
	435	.probe = svwks_init_one,
bc2c9a80	436	.remove = ide_pci_remove,
feb22b7f BZ	437	.suspend = ide_pci_suspend,
feb22b7f BZ	438	.resume = ide_pci_resume,
1da177e4 LT	439	};
1da177e4 LT	440
82ab1eec	441	static int __init svwks_ide_init(void)
1da177e4	442	{
a9ab09e2	443	return ide_pci_register_driver(&svwks_pci_driver);
1da177e4 LT	444	}
1da177e4 LT	445
bc2c9a80 BZ	446	static void __exit svwks_ide_exit(void)
bc2c9a80 BZ	447	{
a9ab09e2	448	pci_unregister_driver(&svwks_pci_driver);
bc2c9a80 BZ	449	}
bc2c9a80 BZ	450
1da177e4	451	module_init(svwks_ide_init);
bc2c9a80	452	module_exit(svwks_ide_exit);
1da177e4	453
e7593af6	454	MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
1da177e4 LT	455	MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
1da177e4 LT	456	MODULE_LICENSE("GPL");