]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
59bca8cc BZ |
2 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 1995-1998 Mark Lord | |
4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 5 | * |
1da177e4 | 6 | * May be copied or modified under the terms of the GNU General Public License |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/types.h> |
10 | #include <linux/kernel.h> | |
11 | #include <linux/pci.h> | |
12 | #include <linux/init.h> | |
1da177e4 LT |
13 | #include <linux/interrupt.h> |
14 | #include <linux/ide.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <asm/io.h> | |
1da177e4 | 18 | |
1da177e4 LT |
19 | /** |
20 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
21 | * @dev: PCI device of interface to switch native | |
22 | * @name: Name of interface | |
23 | * | |
24 | * We attempt to place the PCI interface into PCI native mode. If | |
25 | * we succeed the BARs are ok and the controller is in PCI mode. | |
846bb88a | 26 | * Returns 0 on success or an errno code. |
1da177e4 LT |
27 | * |
28 | * FIXME: if we program the interface and then fail to set the BARS | |
29 | * we don't switch it back to legacy mode. Do we actually care ?? | |
30 | */ | |
846bb88a PC |
31 | |
32 | static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name) | |
1da177e4 LT |
33 | { |
34 | u8 progif = 0; | |
35 | ||
36 | /* | |
37 | * Place both IDE interfaces into PCI "native" mode: | |
38 | */ | |
39 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
40 | (progif & 5) != 5) { | |
41 | if ((progif & 0xa) != 0xa) { | |
42 | printk(KERN_INFO "%s: device not capable of full " | |
43 | "native PCI mode\n", name); | |
44 | return -EOPNOTSUPP; | |
45 | } | |
46 | printk("%s: placing both ports into native PCI mode\n", name); | |
47 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
48 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
49 | (progif & 5) != 5) { | |
50 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
51 | "0x%04x, got 0x%04x\n", | |
52 | name, progif|5, progif); | |
53 | return -EOPNOTSUPP; | |
54 | } | |
55 | } | |
56 | return 0; | |
57 | } | |
58 | ||
59 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
8ac2b42a BZ |
60 | static void ide_pci_clear_simplex(unsigned long dma_base, const char *name) |
61 | { | |
62 | u8 dma_stat = inb(dma_base + 2); | |
63 | ||
64 | outb(dma_stat & 0x60, dma_base + 2); | |
65 | dma_stat = inb(dma_base + 2); | |
66 | if (dma_stat & 0x80) | |
67 | printk(KERN_INFO "%s: simplex device: DMA forced\n", name); | |
68 | } | |
69 | ||
1da177e4 | 70 | /** |
b123f56e | 71 | * ide_pci_dma_base - setup BMIBA |
039788e1 | 72 | * @hwif: IDE interface |
b123f56e | 73 | * @d: IDE port info |
1da177e4 | 74 | * |
c58e79dd | 75 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. |
1da177e4 LT |
76 | */ |
77 | ||
b123f56e | 78 | unsigned long ide_pci_dma_base(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 79 | { |
36501650 BZ |
80 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
81 | unsigned long dma_base = 0; | |
1da177e4 | 82 | |
13572144 | 83 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
1da177e4 LT |
84 | return hwif->dma_base; |
85 | ||
86 | if (hwif->mate && hwif->mate->dma_base) { | |
87 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
88 | } else { | |
9ffcf364 BZ |
89 | u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4; |
90 | ||
91 | dma_base = pci_resource_start(dev, baridx); | |
92 | ||
aea5d375 | 93 | if (dma_base == 0) { |
9ffcf364 | 94 | printk(KERN_ERR "%s: DMA base is invalid\n", d->name); |
aea5d375 BZ |
95 | return 0; |
96 | } | |
1da177e4 LT |
97 | } |
98 | ||
aea5d375 BZ |
99 | if (hwif->channel) |
100 | dma_base += 8; | |
101 | ||
ebb00fb5 BZ |
102 | return dma_base; |
103 | } | |
104 | EXPORT_SYMBOL_GPL(ide_pci_dma_base); | |
105 | ||
106 | int ide_pci_check_simplex(ide_hwif_t *hwif, const struct ide_port_info *d) | |
107 | { | |
108 | u8 dma_stat; | |
109 | ||
110 | if (d->host_flags & (IDE_HFLAG_MMIO | IDE_HFLAG_CS5520)) | |
8ac2b42a BZ |
111 | goto out; |
112 | ||
113 | if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) { | |
ebb00fb5 | 114 | ide_pci_clear_simplex(hwif->dma_base, d->name); |
8ac2b42a BZ |
115 | goto out; |
116 | } | |
117 | ||
118 | /* | |
119 | * If the device claims "simplex" DMA, this means that only one of | |
120 | * the two interfaces can be trusted with DMA at any point in time | |
121 | * (so we should enable DMA only on one of the two interfaces). | |
122 | * | |
123 | * FIXME: At this point we haven't probed the drives so we can't make | |
124 | * the appropriate decision. Really we should defer this problem until | |
125 | * we tune the drive then try to grab DMA ownership if we want to be | |
126 | * the DMA end. This has to be become dynamic to handle hot-plug. | |
127 | */ | |
374e042c | 128 | dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
8ac2b42a BZ |
129 | if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) { |
130 | printk(KERN_INFO "%s: simplex device: DMA disabled\n", d->name); | |
ebb00fb5 | 131 | return -1; |
1da177e4 | 132 | } |
8ac2b42a | 133 | out: |
ebb00fb5 | 134 | return 0; |
1da177e4 | 135 | } |
ebb00fb5 | 136 | EXPORT_SYMBOL_GPL(ide_pci_check_simplex); |
d54452fb BZ |
137 | |
138 | /* | |
139 | * Set up BM-DMA capability (PnP BIOS should have done this) | |
140 | */ | |
b123f56e | 141 | int ide_pci_set_master(struct pci_dev *dev, const char *name) |
d54452fb BZ |
142 | { |
143 | u16 pcicmd; | |
144 | ||
145 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
146 | ||
147 | if ((pcicmd & PCI_COMMAND_MASTER) == 0) { | |
148 | pci_set_master(dev); | |
149 | ||
150 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || | |
151 | (pcicmd & PCI_COMMAND_MASTER) == 0) { | |
152 | printk(KERN_ERR "%s: error updating PCICMD on %s\n", | |
153 | name, pci_name(dev)); | |
154 | return -EIO; | |
155 | } | |
156 | } | |
157 | ||
158 | return 0; | |
159 | } | |
b123f56e | 160 | EXPORT_SYMBOL_GPL(ide_pci_set_master); |
1da177e4 LT |
161 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
162 | ||
85620436 | 163 | void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 164 | { |
bde07e5e BZ |
165 | printk(KERN_INFO "%s: IDE controller (0x%04x:0x%04x rev 0x%02x) at " |
166 | " PCI slot %s\n", d->name, dev->vendor, dev->device, | |
167 | dev->revision, pci_name(dev)); | |
1da177e4 | 168 | } |
1da177e4 LT |
169 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); |
170 | ||
171 | ||
172 | /** | |
173 | * ide_pci_enable - do PCI enables | |
174 | * @dev: PCI device | |
039788e1 | 175 | * @d: IDE port info |
1da177e4 LT |
176 | * |
177 | * Enable the IDE PCI device. We attempt to enable the device in full | |
09483916 BH |
178 | * but if that fails then we only need IO space. The PCI code should |
179 | * have setup the proper resources for us already for controllers in | |
180 | * legacy mode. | |
846bb88a | 181 | * |
1da177e4 LT |
182 | * Returns zero on success or an error code |
183 | */ | |
039788e1 | 184 | |
85620436 | 185 | static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 186 | { |
0d1bad21 | 187 | int ret, bars; |
1da177e4 LT |
188 | |
189 | if (pci_enable_device(dev)) { | |
09483916 | 190 | ret = pci_enable_device_io(dev); |
1da177e4 LT |
191 | if (ret < 0) { |
192 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
193 | "Could not enable device.\n", d->name); | |
194 | goto out; | |
195 | } | |
196 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
197 | } | |
198 | ||
199 | /* | |
039788e1 BZ |
200 | * assume all devices can do 32-bit DMA for now, we can add |
201 | * a DMA mask field to the struct ide_port_info if we need it | |
202 | * (or let lower level driver set the DMA mask) | |
1da177e4 LT |
203 | */ |
204 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
205 | if (ret < 0) { | |
206 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
207 | goto out; | |
208 | } | |
209 | ||
0d1bad21 BZ |
210 | if (d->host_flags & IDE_HFLAG_SINGLE) |
211 | bars = (1 << 2) - 1; | |
212 | else | |
213 | bars = (1 << 4) - 1; | |
1da177e4 | 214 | |
0d1bad21 BZ |
215 | if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) { |
216 | if (d->host_flags & IDE_HFLAG_CS5520) | |
217 | bars |= (1 << 2); | |
218 | else | |
219 | bars |= (1 << 4); | |
220 | } | |
221 | ||
222 | ret = pci_request_selected_regions(dev, bars, d->name); | |
223 | if (ret < 0) | |
224 | printk(KERN_ERR "%s: can't reserve resources\n", d->name); | |
1da177e4 LT |
225 | out: |
226 | return ret; | |
227 | } | |
228 | ||
229 | /** | |
230 | * ide_pci_configure - configure an unconfigured device | |
231 | * @dev: PCI device | |
039788e1 | 232 | * @d: IDE port info |
1da177e4 LT |
233 | * |
234 | * Enable and configure the PCI device we have been passed. | |
235 | * Returns zero on success or an error code. | |
236 | */ | |
039788e1 | 237 | |
85620436 | 238 | static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 LT |
239 | { |
240 | u16 pcicmd = 0; | |
241 | /* | |
242 | * PnP BIOS was *supposed* to have setup this device, but we | |
243 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
244 | * (or possibly the device is using a "legacy header" for IRQs). | |
245 | * Maybe the user deliberately *disabled* the device, | |
246 | * but we'll eventually ignore it again if no drives respond. | |
247 | */ | |
846bb88a PC |
248 | if (ide_setup_pci_baseregs(dev, d->name) || |
249 | pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) { | |
1da177e4 LT |
250 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); |
251 | return -ENODEV; | |
252 | } | |
253 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
254 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
255 | return -EIO; | |
256 | } | |
257 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
258 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
259 | return -ENXIO; | |
260 | } | |
261 | return 0; | |
262 | } | |
263 | ||
264 | /** | |
265 | * ide_pci_check_iomem - check a register is I/O | |
039788e1 BZ |
266 | * @dev: PCI device |
267 | * @d: IDE port info | |
268 | * @bar: BAR number | |
1da177e4 | 269 | * |
1baccff8 SS |
270 | * Checks if a BAR is configured and points to MMIO space. If so, |
271 | * return an error code. Otherwise return 0 | |
1da177e4 | 272 | */ |
039788e1 | 273 | |
1baccff8 SS |
274 | static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d, |
275 | int bar) | |
1da177e4 LT |
276 | { |
277 | ulong flags = pci_resource_flags(dev, bar); | |
846bb88a | 278 | |
1da177e4 LT |
279 | /* Unconfigured ? */ |
280 | if (!flags || pci_resource_len(dev, bar) == 0) | |
281 | return 0; | |
282 | ||
1baccff8 SS |
283 | /* I/O space */ |
284 | if (flags & IORESOURCE_IO) | |
1da177e4 | 285 | return 0; |
846bb88a | 286 | |
1da177e4 | 287 | /* Bad */ |
1da177e4 LT |
288 | return -EINVAL; |
289 | } | |
290 | ||
291 | /** | |
48c3c107 | 292 | * ide_hw_configure - configure a hw_regs_t instance |
1da177e4 | 293 | * @dev: PCI device holding interface |
039788e1 | 294 | * @d: IDE port info |
1ebf7493 BZ |
295 | * @port: port number |
296 | * @irq: PCI IRQ | |
c97c6aca | 297 | * @hw: hw_regs_t instance corresponding to this port |
1da177e4 LT |
298 | * |
299 | * Perform the initial set up for the hardware interface structure. This | |
300 | * is done per interface port rather than per PCI device. There may be | |
301 | * more than one port per device. | |
302 | * | |
48c3c107 | 303 | * Returns zero on success or an error code. |
1da177e4 | 304 | */ |
039788e1 | 305 | |
48c3c107 BZ |
306 | static int ide_hw_configure(struct pci_dev *dev, const struct ide_port_info *d, |
307 | unsigned int port, int irq, hw_regs_t *hw) | |
1da177e4 LT |
308 | { |
309 | unsigned long ctl = 0, base = 0; | |
1da177e4 | 310 | |
a5d8c5c8 | 311 | if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { |
1baccff8 SS |
312 | if (ide_pci_check_iomem(dev, d, 2 * port) || |
313 | ide_pci_check_iomem(dev, d, 2 * port + 1)) { | |
314 | printk(KERN_ERR "%s: I/O baseregs (BIOS) are reported " | |
315 | "as MEM for port %d!\n", d->name, port); | |
48c3c107 | 316 | return -EINVAL; |
1baccff8 | 317 | } |
846bb88a | 318 | |
1da177e4 LT |
319 | ctl = pci_resource_start(dev, 2*port+1); |
320 | base = pci_resource_start(dev, 2*port); | |
c1da678b | 321 | } else { |
1da177e4 LT |
322 | /* Use default values */ |
323 | ctl = port ? 0x374 : 0x3f4; | |
324 | base = port ? 0x170 : 0x1f0; | |
325 | } | |
bad7c825 | 326 | |
c1da678b BZ |
327 | if (!base || !ctl) { |
328 | printk(KERN_ERR "%s: bad PCI BARs for port %d, skipping\n", | |
329 | d->name, port); | |
48c3c107 | 330 | return -EINVAL; |
c1da678b BZ |
331 | } |
332 | ||
c97c6aca BZ |
333 | memset(hw, 0, sizeof(*hw)); |
334 | hw->irq = irq; | |
335 | hw->dev = &dev->dev; | |
336 | hw->chipset = d->chipset ? d->chipset : ide_pci; | |
337 | ide_std_init_ports(hw, base, ctl | 2); | |
338 | ||
48c3c107 | 339 | return 0; |
1da177e4 LT |
340 | } |
341 | ||
c413b9b9 | 342 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
343 | /** |
344 | * ide_hwif_setup_dma - configure DMA interface | |
039788e1 | 345 | * @hwif: IDE interface |
c413b9b9 | 346 | * @d: IDE port info |
1da177e4 LT |
347 | * |
348 | * Set up the DMA base for the interface. Enable the master bits as | |
349 | * necessary and attempt to bring the device DMA into a ready to use | |
350 | * state | |
351 | */ | |
039788e1 | 352 | |
b123f56e | 353 | int ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 354 | { |
c413b9b9 | 355 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 356 | |
47b68788 | 357 | if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 || |
1da177e4 LT |
358 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
359 | (dev->class & 0x80))) { | |
b123f56e | 360 | unsigned long base = ide_pci_dma_base(hwif, d); |
d54452fb | 361 | |
ebb00fb5 BZ |
362 | if (base == 0) |
363 | return -1; | |
364 | ||
365 | hwif->dma_base = base; | |
366 | ||
367 | if (ide_pci_check_simplex(hwif, d) < 0) | |
368 | return -1; | |
369 | ||
370 | if (ide_pci_set_master(dev, d->name) < 0) | |
b123f56e | 371 | return -1; |
d54452fb | 372 | |
13572144 | 373 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
63158d5c BZ |
374 | printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); |
375 | else | |
376 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", | |
377 | hwif->name, base, base + 7); | |
378 | ||
379 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
380 | ||
b123f56e BZ |
381 | if (ide_allocate_dma_engine(hwif)) |
382 | return -1; | |
d54452fb | 383 | |
81e8d5a3 | 384 | hwif->dma_ops = &sff_dma_ops; |
b123f56e | 385 | } |
d54452fb | 386 | |
b123f56e | 387 | return 0; |
039788e1 | 388 | } |
c413b9b9 | 389 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
390 | |
391 | /** | |
392 | * ide_setup_pci_controller - set up IDE PCI | |
393 | * @dev: PCI device | |
039788e1 | 394 | * @d: IDE port info |
1da177e4 | 395 | * @noisy: verbose flag |
1da177e4 LT |
396 | * |
397 | * Set up the PCI and controller side of the IDE interface. This brings | |
398 | * up the PCI side of the device, checks that the device is enabled | |
399 | * and enables it if need be | |
400 | */ | |
039788e1 | 401 | |
a95925a3 BZ |
402 | static int ide_setup_pci_controller(struct pci_dev *dev, |
403 | const struct ide_port_info *d, int noisy) | |
1da177e4 LT |
404 | { |
405 | int ret; | |
1da177e4 LT |
406 | u16 pcicmd; |
407 | ||
408 | if (noisy) | |
409 | ide_setup_pci_noise(dev, d); | |
410 | ||
411 | ret = ide_pci_enable(dev, d); | |
412 | if (ret < 0) | |
413 | goto out; | |
414 | ||
415 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
416 | if (ret < 0) { | |
417 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
418 | goto out; | |
419 | } | |
420 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
421 | ret = ide_pci_configure(dev, d); | |
422 | if (ret < 0) | |
423 | goto out; | |
1da177e4 LT |
424 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); |
425 | } | |
426 | ||
1da177e4 LT |
427 | out: |
428 | return ret; | |
429 | } | |
430 | ||
431 | /** | |
432 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
433 | * @dev: PCI device | |
039788e1 | 434 | * @d: IDE port info |
1da177e4 | 435 | * @pciirq: IRQ line |
c97c6aca BZ |
436 | * @hw: hw_regs_t instances corresponding to this PCI IDE device |
437 | * @hws: hw_regs_t pointers table to update | |
1da177e4 LT |
438 | * |
439 | * Scan the interfaces attached to this device and do any | |
440 | * necessary per port setup. Attach the devices and ask the | |
441 | * generic DMA layer to do its work for us. | |
442 | * | |
443 | * Normally called automaticall from do_ide_pci_setup_device, | |
444 | * but is also used directly as a helper function by some controllers | |
445 | * where the chipset setup is not the default PCI IDE one. | |
446 | */ | |
8447d9d5 | 447 | |
c97c6aca | 448 | void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d, |
48c3c107 | 449 | int pciirq, hw_regs_t *hw, hw_regs_t **hws) |
1da177e4 | 450 | { |
a5d8c5c8 | 451 | int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; |
1da177e4 LT |
452 | u8 tmp; |
453 | ||
1da177e4 LT |
454 | /* |
455 | * Set up the IDE ports | |
456 | */ | |
cf6e854e | 457 | |
a5d8c5c8 | 458 | for (port = 0; port < channels; ++port) { |
85620436 BZ |
459 | const ide_pci_enablebit_t *e = &(d->enablebits[port]); |
460 | ||
1da177e4 | 461 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || |
cf6e854e BZ |
462 | (tmp & e->mask) != e->val)) { |
463 | printk(KERN_INFO "%s: IDE port disabled\n", d->name); | |
1da177e4 | 464 | continue; /* port not enabled */ |
cf6e854e | 465 | } |
1da177e4 | 466 | |
48c3c107 | 467 | if (ide_hw_configure(dev, d, port, pciirq, hw + port)) |
1da177e4 LT |
468 | continue; |
469 | ||
c97c6aca | 470 | *(hws + port) = hw + port; |
1ebf7493 | 471 | } |
1da177e4 | 472 | } |
1da177e4 LT |
473 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); |
474 | ||
475 | /* | |
476 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
477 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
478 | * for use with them. This generic code works for most PCI chipsets. | |
479 | * | |
480 | * One thing that is not standardized is the location of the | |
481 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
039788e1 | 482 | * we "know" about, this information is in the struct ide_port_info; |
1da177e4 LT |
483 | * for all other chipsets, we just assume both interfaces are enabled. |
484 | */ | |
039788e1 | 485 | static int do_ide_setup_pci_device(struct pci_dev *dev, |
85620436 | 486 | const struct ide_port_info *d, |
51d87ed0 | 487 | u8 noisy) |
1da177e4 | 488 | { |
1da177e4 LT |
489 | int pciirq, ret; |
490 | ||
1da177e4 LT |
491 | /* |
492 | * Can we trust the reported IRQ? | |
493 | */ | |
494 | pciirq = dev->irq; | |
495 | ||
708e5f9e BZ |
496 | /* |
497 | * This allows offboard ide-pci cards the enable a BIOS, | |
498 | * verify interrupt settings of split-mirror pci-config | |
499 | * space, place chipset into init-mode, and/or preserve | |
500 | * an interrupt if the card is not native ide support. | |
501 | */ | |
502 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
503 | if (ret < 0) | |
504 | goto out; | |
505 | ||
1da177e4 LT |
506 | /* Is it an "IDE storage" device in non-PCI mode? */ |
507 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
508 | if (noisy) | |
509 | printk(KERN_INFO "%s: not 100%% native mode: " | |
510 | "will probe irqs later\n", d->name); | |
1da177e4 | 511 | pciirq = ret; |
1da177e4 LT |
512 | } else if (!pciirq) { |
513 | if (noisy) | |
514 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
515 | d->name, pciirq); | |
516 | pciirq = 0; | |
517 | } else { | |
1da177e4 | 518 | if (noisy) |
1da177e4 LT |
519 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", |
520 | d->name, pciirq); | |
1da177e4 LT |
521 | } |
522 | ||
51d87ed0 | 523 | ret = pciirq; |
1da177e4 LT |
524 | out: |
525 | return ret; | |
526 | } | |
527 | ||
85620436 | 528 | int ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 529 | { |
c97c6aca | 530 | hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL }; |
1da177e4 LT |
531 | int ret; |
532 | ||
a742d6cf BZ |
533 | ret = ide_setup_pci_controller(dev, d, 1); |
534 | if (ret < 0) | |
535 | goto out; | |
536 | ||
8c2eece5 BZ |
537 | ide_pci_setup_ports(dev, d, 0, &hw[0], &hws[0]); |
538 | ||
51d87ed0 | 539 | ret = do_ide_setup_pci_device(dev, d, 1); |
8c2eece5 BZ |
540 | if (ret < 0) |
541 | goto out; | |
51d87ed0 | 542 | |
8c2eece5 BZ |
543 | /* fixup IRQ */ |
544 | hw[1].irq = hw[0].irq = ret; | |
1da177e4 | 545 | |
8c2eece5 | 546 | ret = ide_host_add(d, hws, NULL); |
a742d6cf | 547 | out: |
1da177e4 LT |
548 | return ret; |
549 | } | |
1da177e4 LT |
550 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); |
551 | ||
552 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
85620436 | 553 | const struct ide_port_info *d) |
1da177e4 LT |
554 | { |
555 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
1da177e4 | 556 | int ret, i; |
c97c6aca | 557 | hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL }; |
1da177e4 LT |
558 | |
559 | for (i = 0; i < 2; i++) { | |
a742d6cf BZ |
560 | ret = ide_setup_pci_controller(pdev[i], d, !i); |
561 | if (ret < 0) | |
562 | goto out; | |
563 | ||
8c2eece5 BZ |
564 | ide_pci_setup_ports(pdev[i], d, 0, &hw[i*2], &hws[i*2]); |
565 | ||
51d87ed0 BZ |
566 | ret = do_ide_setup_pci_device(pdev[i], d, !i); |
567 | ||
1da177e4 LT |
568 | /* |
569 | * FIXME: Mom, mom, they stole me the helper function to undo | |
570 | * do_ide_setup_pci_device() on the first device! | |
571 | */ | |
572 | if (ret < 0) | |
573 | goto out; | |
51d87ed0 | 574 | |
8c2eece5 BZ |
575 | /* fixup IRQ */ |
576 | hw[i*2 + 1].irq = hw[i*2].irq = ret; | |
1da177e4 LT |
577 | } |
578 | ||
6f904d01 | 579 | ret = ide_host_add(d, hws, NULL); |
1da177e4 LT |
580 | out: |
581 | return ret; | |
582 | } | |
1da177e4 | 583 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); |