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Commit | Line | Data |
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1da177e4 | 1 | /* |
59bca8cc BZ |
2 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 1995-1998 Mark Lord | |
4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 5 | * |
1da177e4 | 6 | * May be copied or modified under the terms of the GNU General Public License |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/types.h> |
10 | #include <linux/kernel.h> | |
11 | #include <linux/pci.h> | |
12 | #include <linux/init.h> | |
1da177e4 LT |
13 | #include <linux/interrupt.h> |
14 | #include <linux/ide.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <asm/io.h> | |
1da177e4 | 18 | |
1da177e4 LT |
19 | /** |
20 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
21 | * @dev: PCI device of interface to switch native | |
22 | * @name: Name of interface | |
23 | * | |
24 | * We attempt to place the PCI interface into PCI native mode. If | |
25 | * we succeed the BARs are ok and the controller is in PCI mode. | |
846bb88a | 26 | * Returns 0 on success or an errno code. |
1da177e4 LT |
27 | * |
28 | * FIXME: if we program the interface and then fail to set the BARS | |
29 | * we don't switch it back to legacy mode. Do we actually care ?? | |
30 | */ | |
846bb88a PC |
31 | |
32 | static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name) | |
1da177e4 LT |
33 | { |
34 | u8 progif = 0; | |
35 | ||
36 | /* | |
37 | * Place both IDE interfaces into PCI "native" mode: | |
38 | */ | |
39 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
40 | (progif & 5) != 5) { | |
41 | if ((progif & 0xa) != 0xa) { | |
42 | printk(KERN_INFO "%s: device not capable of full " | |
43 | "native PCI mode\n", name); | |
44 | return -EOPNOTSUPP; | |
45 | } | |
46 | printk("%s: placing both ports into native PCI mode\n", name); | |
47 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
48 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
49 | (progif & 5) != 5) { | |
50 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
51 | "0x%04x, got 0x%04x\n", | |
52 | name, progif|5, progif); | |
53 | return -EOPNOTSUPP; | |
54 | } | |
55 | } | |
56 | return 0; | |
57 | } | |
58 | ||
59 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
8ac2b42a BZ |
60 | static void ide_pci_clear_simplex(unsigned long dma_base, const char *name) |
61 | { | |
62 | u8 dma_stat = inb(dma_base + 2); | |
63 | ||
64 | outb(dma_stat & 0x60, dma_base + 2); | |
65 | dma_stat = inb(dma_base + 2); | |
66 | if (dma_stat & 0x80) | |
67 | printk(KERN_INFO "%s: simplex device: DMA forced\n", name); | |
68 | } | |
69 | ||
1da177e4 | 70 | /** |
b123f56e | 71 | * ide_pci_dma_base - setup BMIBA |
039788e1 | 72 | * @hwif: IDE interface |
b123f56e | 73 | * @d: IDE port info |
1da177e4 | 74 | * |
c58e79dd BZ |
75 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. |
76 | * Where a device has a partner that is already in DMA mode we check | |
77 | * and enforce IDE simplex rules. | |
1da177e4 LT |
78 | */ |
79 | ||
b123f56e | 80 | unsigned long ide_pci_dma_base(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 81 | { |
36501650 BZ |
82 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
83 | unsigned long dma_base = 0; | |
8ac2b42a | 84 | u8 dma_stat = 0; |
1da177e4 | 85 | |
13572144 | 86 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
1da177e4 LT |
87 | return hwif->dma_base; |
88 | ||
89 | if (hwif->mate && hwif->mate->dma_base) { | |
90 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
91 | } else { | |
9ffcf364 BZ |
92 | u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4; |
93 | ||
94 | dma_base = pci_resource_start(dev, baridx); | |
95 | ||
aea5d375 | 96 | if (dma_base == 0) { |
9ffcf364 | 97 | printk(KERN_ERR "%s: DMA base is invalid\n", d->name); |
aea5d375 BZ |
98 | return 0; |
99 | } | |
1da177e4 LT |
100 | } |
101 | ||
aea5d375 BZ |
102 | if (hwif->channel) |
103 | dma_base += 8; | |
104 | ||
8ac2b42a BZ |
105 | if (d->host_flags & IDE_HFLAG_CS5520) |
106 | goto out; | |
107 | ||
108 | if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) { | |
109 | ide_pci_clear_simplex(dma_base, d->name); | |
110 | goto out; | |
111 | } | |
112 | ||
113 | /* | |
114 | * If the device claims "simplex" DMA, this means that only one of | |
115 | * the two interfaces can be trusted with DMA at any point in time | |
116 | * (so we should enable DMA only on one of the two interfaces). | |
117 | * | |
118 | * FIXME: At this point we haven't probed the drives so we can't make | |
119 | * the appropriate decision. Really we should defer this problem until | |
120 | * we tune the drive then try to grab DMA ownership if we want to be | |
121 | * the DMA end. This has to be become dynamic to handle hot-plug. | |
122 | */ | |
123 | dma_stat = hwif->INB(dma_base + 2); | |
124 | if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) { | |
125 | printk(KERN_INFO "%s: simplex device: DMA disabled\n", d->name); | |
126 | dma_base = 0; | |
1da177e4 | 127 | } |
8ac2b42a | 128 | out: |
1da177e4 LT |
129 | return dma_base; |
130 | } | |
b123f56e | 131 | EXPORT_SYMBOL_GPL(ide_pci_dma_base); |
d54452fb BZ |
132 | |
133 | /* | |
134 | * Set up BM-DMA capability (PnP BIOS should have done this) | |
135 | */ | |
b123f56e | 136 | int ide_pci_set_master(struct pci_dev *dev, const char *name) |
d54452fb BZ |
137 | { |
138 | u16 pcicmd; | |
139 | ||
140 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
141 | ||
142 | if ((pcicmd & PCI_COMMAND_MASTER) == 0) { | |
143 | pci_set_master(dev); | |
144 | ||
145 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || | |
146 | (pcicmd & PCI_COMMAND_MASTER) == 0) { | |
147 | printk(KERN_ERR "%s: error updating PCICMD on %s\n", | |
148 | name, pci_name(dev)); | |
149 | return -EIO; | |
150 | } | |
151 | } | |
152 | ||
153 | return 0; | |
154 | } | |
b123f56e | 155 | EXPORT_SYMBOL_GPL(ide_pci_set_master); |
1da177e4 LT |
156 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
157 | ||
85620436 | 158 | void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 159 | { |
bde07e5e BZ |
160 | printk(KERN_INFO "%s: IDE controller (0x%04x:0x%04x rev 0x%02x) at " |
161 | " PCI slot %s\n", d->name, dev->vendor, dev->device, | |
162 | dev->revision, pci_name(dev)); | |
1da177e4 | 163 | } |
1da177e4 LT |
164 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); |
165 | ||
166 | ||
167 | /** | |
168 | * ide_pci_enable - do PCI enables | |
169 | * @dev: PCI device | |
039788e1 | 170 | * @d: IDE port info |
1da177e4 LT |
171 | * |
172 | * Enable the IDE PCI device. We attempt to enable the device in full | |
09483916 BH |
173 | * but if that fails then we only need IO space. The PCI code should |
174 | * have setup the proper resources for us already for controllers in | |
175 | * legacy mode. | |
846bb88a | 176 | * |
1da177e4 LT |
177 | * Returns zero on success or an error code |
178 | */ | |
039788e1 | 179 | |
85620436 | 180 | static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 181 | { |
0d1bad21 | 182 | int ret, bars; |
1da177e4 LT |
183 | |
184 | if (pci_enable_device(dev)) { | |
09483916 | 185 | ret = pci_enable_device_io(dev); |
1da177e4 LT |
186 | if (ret < 0) { |
187 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
188 | "Could not enable device.\n", d->name); | |
189 | goto out; | |
190 | } | |
191 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
192 | } | |
193 | ||
194 | /* | |
039788e1 BZ |
195 | * assume all devices can do 32-bit DMA for now, we can add |
196 | * a DMA mask field to the struct ide_port_info if we need it | |
197 | * (or let lower level driver set the DMA mask) | |
1da177e4 LT |
198 | */ |
199 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
200 | if (ret < 0) { | |
201 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
202 | goto out; | |
203 | } | |
204 | ||
0d1bad21 BZ |
205 | if (d->host_flags & IDE_HFLAG_SINGLE) |
206 | bars = (1 << 2) - 1; | |
207 | else | |
208 | bars = (1 << 4) - 1; | |
1da177e4 | 209 | |
0d1bad21 BZ |
210 | if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) { |
211 | if (d->host_flags & IDE_HFLAG_CS5520) | |
212 | bars |= (1 << 2); | |
213 | else | |
214 | bars |= (1 << 4); | |
215 | } | |
216 | ||
217 | ret = pci_request_selected_regions(dev, bars, d->name); | |
218 | if (ret < 0) | |
219 | printk(KERN_ERR "%s: can't reserve resources\n", d->name); | |
1da177e4 LT |
220 | out: |
221 | return ret; | |
222 | } | |
223 | ||
224 | /** | |
225 | * ide_pci_configure - configure an unconfigured device | |
226 | * @dev: PCI device | |
039788e1 | 227 | * @d: IDE port info |
1da177e4 LT |
228 | * |
229 | * Enable and configure the PCI device we have been passed. | |
230 | * Returns zero on success or an error code. | |
231 | */ | |
039788e1 | 232 | |
85620436 | 233 | static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 LT |
234 | { |
235 | u16 pcicmd = 0; | |
236 | /* | |
237 | * PnP BIOS was *supposed* to have setup this device, but we | |
238 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
239 | * (or possibly the device is using a "legacy header" for IRQs). | |
240 | * Maybe the user deliberately *disabled* the device, | |
241 | * but we'll eventually ignore it again if no drives respond. | |
242 | */ | |
846bb88a PC |
243 | if (ide_setup_pci_baseregs(dev, d->name) || |
244 | pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) { | |
1da177e4 LT |
245 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); |
246 | return -ENODEV; | |
247 | } | |
248 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
249 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
250 | return -EIO; | |
251 | } | |
252 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
253 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
254 | return -ENXIO; | |
255 | } | |
256 | return 0; | |
257 | } | |
258 | ||
259 | /** | |
260 | * ide_pci_check_iomem - check a register is I/O | |
039788e1 BZ |
261 | * @dev: PCI device |
262 | * @d: IDE port info | |
263 | * @bar: BAR number | |
1da177e4 | 264 | * |
1baccff8 SS |
265 | * Checks if a BAR is configured and points to MMIO space. If so, |
266 | * return an error code. Otherwise return 0 | |
1da177e4 | 267 | */ |
039788e1 | 268 | |
1baccff8 SS |
269 | static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d, |
270 | int bar) | |
1da177e4 LT |
271 | { |
272 | ulong flags = pci_resource_flags(dev, bar); | |
846bb88a | 273 | |
1da177e4 LT |
274 | /* Unconfigured ? */ |
275 | if (!flags || pci_resource_len(dev, bar) == 0) | |
276 | return 0; | |
277 | ||
1baccff8 SS |
278 | /* I/O space */ |
279 | if (flags & IORESOURCE_IO) | |
1da177e4 | 280 | return 0; |
846bb88a | 281 | |
1da177e4 | 282 | /* Bad */ |
1da177e4 LT |
283 | return -EINVAL; |
284 | } | |
285 | ||
286 | /** | |
287 | * ide_hwif_configure - configure an IDE interface | |
288 | * @dev: PCI device holding interface | |
039788e1 | 289 | * @d: IDE port info |
1ebf7493 BZ |
290 | * @port: port number |
291 | * @irq: PCI IRQ | |
1da177e4 LT |
292 | * |
293 | * Perform the initial set up for the hardware interface structure. This | |
294 | * is done per interface port rather than per PCI device. There may be | |
295 | * more than one port per device. | |
296 | * | |
297 | * Returns the new hardware interface structure, or NULL on a failure | |
298 | */ | |
039788e1 | 299 | |
1ebf7493 BZ |
300 | static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, |
301 | const struct ide_port_info *d, | |
302 | unsigned int port, int irq) | |
1da177e4 LT |
303 | { |
304 | unsigned long ctl = 0, base = 0; | |
305 | ide_hwif_t *hwif; | |
79127c37 | 306 | struct hw_regs_s hw; |
1da177e4 | 307 | |
a5d8c5c8 | 308 | if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { |
1baccff8 SS |
309 | if (ide_pci_check_iomem(dev, d, 2 * port) || |
310 | ide_pci_check_iomem(dev, d, 2 * port + 1)) { | |
311 | printk(KERN_ERR "%s: I/O baseregs (BIOS) are reported " | |
312 | "as MEM for port %d!\n", d->name, port); | |
313 | return NULL; | |
314 | } | |
846bb88a | 315 | |
1da177e4 LT |
316 | ctl = pci_resource_start(dev, 2*port+1); |
317 | base = pci_resource_start(dev, 2*port); | |
c1da678b | 318 | } else { |
1da177e4 LT |
319 | /* Use default values */ |
320 | ctl = port ? 0x374 : 0x3f4; | |
321 | base = port ? 0x170 : 0x1f0; | |
322 | } | |
bad7c825 | 323 | |
c1da678b BZ |
324 | if (!base || !ctl) { |
325 | printk(KERN_ERR "%s: bad PCI BARs for port %d, skipping\n", | |
326 | d->name, port); | |
327 | return NULL; | |
328 | } | |
329 | ||
fe80b937 | 330 | hwif = ide_find_port_slot(d); |
eb3aff55 | 331 | if (hwif == NULL) |
bad7c825 | 332 | return NULL; |
79127c37 BZ |
333 | |
334 | memset(&hw, 0, sizeof(hw)); | |
aab8ad9e | 335 | hw.irq = irq; |
79127c37 BZ |
336 | hw.dev = &dev->dev; |
337 | hw.chipset = d->chipset ? d->chipset : ide_pci; | |
338 | ide_std_init_ports(&hw, base, ctl | 2); | |
339 | ||
79127c37 BZ |
340 | ide_init_port_hw(hwif, &hw); |
341 | ||
1da177e4 LT |
342 | return hwif; |
343 | } | |
344 | ||
c413b9b9 | 345 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
346 | /** |
347 | * ide_hwif_setup_dma - configure DMA interface | |
039788e1 | 348 | * @hwif: IDE interface |
c413b9b9 | 349 | * @d: IDE port info |
1da177e4 LT |
350 | * |
351 | * Set up the DMA base for the interface. Enable the master bits as | |
352 | * necessary and attempt to bring the device DMA into a ready to use | |
353 | * state | |
354 | */ | |
039788e1 | 355 | |
b123f56e | 356 | int ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 357 | { |
c413b9b9 | 358 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 359 | |
47b68788 | 360 | if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 || |
1da177e4 LT |
361 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
362 | (dev->class & 0x80))) { | |
b123f56e | 363 | unsigned long base = ide_pci_dma_base(hwif, d); |
d54452fb | 364 | |
63158d5c | 365 | if (base == 0 || ide_pci_set_master(dev, d->name) < 0) |
b123f56e | 366 | return -1; |
d54452fb | 367 | |
13572144 | 368 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
63158d5c BZ |
369 | printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); |
370 | else | |
371 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", | |
372 | hwif->name, base, base + 7); | |
373 | ||
374 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
375 | ||
b123f56e BZ |
376 | if (ide_allocate_dma_engine(hwif)) |
377 | return -1; | |
d54452fb | 378 | |
f37afdac | 379 | ide_setup_dma(hwif, base); |
b123f56e | 380 | } |
d54452fb | 381 | |
b123f56e | 382 | return 0; |
039788e1 | 383 | } |
c413b9b9 | 384 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
385 | |
386 | /** | |
387 | * ide_setup_pci_controller - set up IDE PCI | |
388 | * @dev: PCI device | |
039788e1 | 389 | * @d: IDE port info |
1da177e4 LT |
390 | * @noisy: verbose flag |
391 | * @config: returned as 1 if we configured the hardware | |
392 | * | |
393 | * Set up the PCI and controller side of the IDE interface. This brings | |
394 | * up the PCI side of the device, checks that the device is enabled | |
395 | * and enables it if need be | |
396 | */ | |
039788e1 | 397 | |
85620436 | 398 | static int ide_setup_pci_controller(struct pci_dev *dev, const struct ide_port_info *d, int noisy, int *config) |
1da177e4 LT |
399 | { |
400 | int ret; | |
1da177e4 LT |
401 | u16 pcicmd; |
402 | ||
403 | if (noisy) | |
404 | ide_setup_pci_noise(dev, d); | |
405 | ||
406 | ret = ide_pci_enable(dev, d); | |
407 | if (ret < 0) | |
408 | goto out; | |
409 | ||
410 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
411 | if (ret < 0) { | |
412 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
413 | goto out; | |
414 | } | |
415 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
416 | ret = ide_pci_configure(dev, d); | |
417 | if (ret < 0) | |
418 | goto out; | |
419 | *config = 1; | |
420 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); | |
421 | } | |
422 | ||
1da177e4 LT |
423 | out: |
424 | return ret; | |
425 | } | |
426 | ||
427 | /** | |
428 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
429 | * @dev: PCI device | |
039788e1 | 430 | * @d: IDE port info |
1da177e4 | 431 | * @pciirq: IRQ line |
8447d9d5 | 432 | * @idx: ATA index table to update |
1da177e4 LT |
433 | * |
434 | * Scan the interfaces attached to this device and do any | |
435 | * necessary per port setup. Attach the devices and ask the | |
436 | * generic DMA layer to do its work for us. | |
437 | * | |
438 | * Normally called automaticall from do_ide_pci_setup_device, | |
439 | * but is also used directly as a helper function by some controllers | |
440 | * where the chipset setup is not the default PCI IDE one. | |
441 | */ | |
8447d9d5 | 442 | |
85620436 | 443 | void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d, int pciirq, u8 *idx) |
1da177e4 | 444 | { |
a5d8c5c8 | 445 | int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; |
c413b9b9 | 446 | ide_hwif_t *hwif; |
1da177e4 LT |
447 | u8 tmp; |
448 | ||
1da177e4 LT |
449 | /* |
450 | * Set up the IDE ports | |
451 | */ | |
cf6e854e | 452 | |
a5d8c5c8 | 453 | for (port = 0; port < channels; ++port) { |
85620436 BZ |
454 | const ide_pci_enablebit_t *e = &(d->enablebits[port]); |
455 | ||
1da177e4 | 456 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || |
cf6e854e BZ |
457 | (tmp & e->mask) != e->val)) { |
458 | printk(KERN_INFO "%s: IDE port disabled\n", d->name); | |
1da177e4 | 459 | continue; /* port not enabled */ |
cf6e854e | 460 | } |
1da177e4 | 461 | |
1ebf7493 BZ |
462 | hwif = ide_hwif_configure(dev, d, port, pciirq); |
463 | if (hwif == NULL) | |
1da177e4 LT |
464 | continue; |
465 | ||
8447d9d5 | 466 | *(idx + port) = hwif->index; |
1ebf7493 | 467 | } |
1da177e4 | 468 | } |
1da177e4 LT |
469 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); |
470 | ||
471 | /* | |
472 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
473 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
474 | * for use with them. This generic code works for most PCI chipsets. | |
475 | * | |
476 | * One thing that is not standardized is the location of the | |
477 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
039788e1 | 478 | * we "know" about, this information is in the struct ide_port_info; |
1da177e4 LT |
479 | * for all other chipsets, we just assume both interfaces are enabled. |
480 | */ | |
039788e1 | 481 | static int do_ide_setup_pci_device(struct pci_dev *dev, |
85620436 | 482 | const struct ide_port_info *d, |
8447d9d5 | 483 | u8 *idx, u8 noisy) |
1da177e4 | 484 | { |
1da177e4 LT |
485 | int tried_config = 0; |
486 | int pciirq, ret; | |
487 | ||
488 | ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); | |
489 | if (ret < 0) | |
490 | goto out; | |
491 | ||
492 | /* | |
493 | * Can we trust the reported IRQ? | |
494 | */ | |
495 | pciirq = dev->irq; | |
496 | ||
497 | /* Is it an "IDE storage" device in non-PCI mode? */ | |
498 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
499 | if (noisy) | |
500 | printk(KERN_INFO "%s: not 100%% native mode: " | |
501 | "will probe irqs later\n", d->name); | |
502 | /* | |
503 | * This allows offboard ide-pci cards the enable a BIOS, | |
504 | * verify interrupt settings of split-mirror pci-config | |
505 | * space, place chipset into init-mode, and/or preserve | |
506 | * an interrupt if the card is not native ide support. | |
507 | */ | |
508 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
509 | if (ret < 0) | |
510 | goto out; | |
511 | pciirq = ret; | |
512 | } else if (tried_config) { | |
513 | if (noisy) | |
514 | printk(KERN_INFO "%s: will probe irqs later\n", d->name); | |
515 | pciirq = 0; | |
516 | } else if (!pciirq) { | |
517 | if (noisy) | |
518 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
519 | d->name, pciirq); | |
520 | pciirq = 0; | |
521 | } else { | |
522 | if (d->init_chipset) { | |
523 | ret = d->init_chipset(dev, d->name); | |
524 | if (ret < 0) | |
525 | goto out; | |
526 | } | |
527 | if (noisy) | |
1da177e4 LT |
528 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", |
529 | d->name, pciirq); | |
1da177e4 LT |
530 | } |
531 | ||
532 | /* FIXME: silent failure can happen */ | |
533 | ||
8447d9d5 | 534 | ide_pci_setup_ports(dev, d, pciirq, idx); |
1da177e4 LT |
535 | out: |
536 | return ret; | |
537 | } | |
538 | ||
85620436 | 539 | int ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 540 | { |
8447d9d5 | 541 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
542 | int ret; |
543 | ||
8447d9d5 | 544 | ret = do_ide_setup_pci_device(dev, d, &idx[0], 1); |
1da177e4 | 545 | |
8447d9d5 | 546 | if (ret >= 0) |
c413b9b9 | 547 | ide_device_add(idx, d); |
1da177e4 | 548 | |
1da177e4 LT |
549 | return ret; |
550 | } | |
1da177e4 LT |
551 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); |
552 | ||
553 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
85620436 | 554 | const struct ide_port_info *d) |
1da177e4 LT |
555 | { |
556 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
1da177e4 | 557 | int ret, i; |
8447d9d5 | 558 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
559 | |
560 | for (i = 0; i < 2; i++) { | |
8447d9d5 | 561 | ret = do_ide_setup_pci_device(pdev[i], d, &idx[i*2], !i); |
1da177e4 LT |
562 | /* |
563 | * FIXME: Mom, mom, they stole me the helper function to undo | |
564 | * do_ide_setup_pci_device() on the first device! | |
565 | */ | |
566 | if (ret < 0) | |
567 | goto out; | |
568 | } | |
569 | ||
c413b9b9 | 570 | ide_device_add(idx, d); |
1da177e4 LT |
571 | out: |
572 | return ret; | |
573 | } | |
1da177e4 | 574 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); |