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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/setup-pci.c Version 1.10 2002/08/19 | |
3 | * | |
4 | * Copyright (c) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * | |
6 | * Copyright (c) 1995-1998 Mark Lord | |
7 | * May be copied or modified under the terms of the GNU General Public License | |
1da177e4 LT |
8 | */ |
9 | ||
10 | /* | |
11 | * This module provides support for automatic detection and | |
12 | * configuration of all PCI IDE interfaces present in a system. | |
13 | */ | |
14 | ||
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/timer.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/ide.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | ||
26 | #include <asm/io.h> | |
27 | #include <asm/irq.h> | |
28 | ||
29 | ||
30 | /** | |
31 | * ide_match_hwif - match a PCI IDE against an ide_hwif | |
32 | * @io_base: I/O base of device | |
33 | * @bootable: set if its bootable | |
34 | * @name: name of device | |
35 | * | |
36 | * Match a PCI IDE port against an entry in ide_hwifs[], | |
37 | * based on io_base port if possible. Return the matching hwif, | |
38 | * or a new hwif. If we find an error (clashing, out of devices, etc) | |
39 | * return NULL | |
40 | * | |
41 | * FIXME: we need to handle mmio matches here too | |
42 | */ | |
43 | ||
44 | static ide_hwif_t *ide_match_hwif(unsigned long io_base, u8 bootable, const char *name) | |
45 | { | |
46 | int h; | |
47 | ide_hwif_t *hwif; | |
48 | ||
49 | /* | |
50 | * Look for a hwif with matching io_base specified using | |
51 | * parameters to ide_setup(). | |
52 | */ | |
53 | for (h = 0; h < MAX_HWIFS; ++h) { | |
54 | hwif = &ide_hwifs[h]; | |
55 | if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { | |
56 | if (hwif->chipset == ide_forced) | |
57 | return hwif; /* a perfect match */ | |
58 | } | |
59 | } | |
60 | /* | |
61 | * Look for a hwif with matching io_base default value. | |
62 | * If chipset is "ide_unknown", then claim that hwif slot. | |
63 | * Otherwise, some other chipset has already claimed it.. :( | |
64 | */ | |
65 | for (h = 0; h < MAX_HWIFS; ++h) { | |
66 | hwif = &ide_hwifs[h]; | |
67 | if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { | |
68 | if (hwif->chipset == ide_unknown) | |
69 | return hwif; /* match */ | |
70 | printk(KERN_ERR "%s: port 0x%04lx already claimed by %s\n", | |
71 | name, io_base, hwif->name); | |
72 | return NULL; /* already claimed */ | |
73 | } | |
74 | } | |
75 | /* | |
76 | * Okay, there is no hwif matching our io_base, | |
77 | * so we'll just claim an unassigned slot. | |
78 | * Give preference to claiming other slots before claiming ide0/ide1, | |
79 | * just in case there's another interface yet-to-be-scanned | |
80 | * which uses ports 1f0/170 (the ide0/ide1 defaults). | |
81 | * | |
82 | * Unless there is a bootable card that does not use the standard | |
83 | * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag. | |
84 | */ | |
85 | if (bootable) { | |
86 | for (h = 0; h < MAX_HWIFS; ++h) { | |
87 | hwif = &ide_hwifs[h]; | |
88 | if (hwif->chipset == ide_unknown) | |
89 | return hwif; /* pick an unused entry */ | |
90 | } | |
91 | } else { | |
92 | for (h = 2; h < MAX_HWIFS; ++h) { | |
93 | hwif = ide_hwifs + h; | |
94 | if (hwif->chipset == ide_unknown) | |
95 | return hwif; /* pick an unused entry */ | |
96 | } | |
97 | } | |
83d7dbc4 | 98 | for (h = 0; h < 2 && h < MAX_HWIFS; ++h) { |
1da177e4 LT |
99 | hwif = ide_hwifs + h; |
100 | if (hwif->chipset == ide_unknown) | |
101 | return hwif; /* pick an unused entry */ | |
102 | } | |
103 | printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", name); | |
104 | return NULL; | |
105 | } | |
106 | ||
107 | /** | |
108 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
109 | * @dev: PCI device of interface to switch native | |
110 | * @name: Name of interface | |
111 | * | |
112 | * We attempt to place the PCI interface into PCI native mode. If | |
113 | * we succeed the BARs are ok and the controller is in PCI mode. | |
114 | * Returns 0 on success or an errno code. | |
115 | * | |
116 | * FIXME: if we program the interface and then fail to set the BARS | |
117 | * we don't switch it back to legacy mode. Do we actually care ?? | |
118 | */ | |
119 | ||
120 | static int ide_setup_pci_baseregs (struct pci_dev *dev, const char *name) | |
121 | { | |
122 | u8 progif = 0; | |
123 | ||
124 | /* | |
125 | * Place both IDE interfaces into PCI "native" mode: | |
126 | */ | |
127 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
128 | (progif & 5) != 5) { | |
129 | if ((progif & 0xa) != 0xa) { | |
130 | printk(KERN_INFO "%s: device not capable of full " | |
131 | "native PCI mode\n", name); | |
132 | return -EOPNOTSUPP; | |
133 | } | |
134 | printk("%s: placing both ports into native PCI mode\n", name); | |
135 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
136 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
137 | (progif & 5) != 5) { | |
138 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
139 | "0x%04x, got 0x%04x\n", | |
140 | name, progif|5, progif); | |
141 | return -EOPNOTSUPP; | |
142 | } | |
143 | } | |
144 | return 0; | |
145 | } | |
146 | ||
147 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
1da177e4 LT |
148 | /** |
149 | * ide_get_or_set_dma_base - setup BMIBA | |
150 | * @hwif: Interface | |
151 | * | |
c58e79dd BZ |
152 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. |
153 | * Where a device has a partner that is already in DMA mode we check | |
154 | * and enforce IDE simplex rules. | |
1da177e4 LT |
155 | */ |
156 | ||
157 | static unsigned long ide_get_or_set_dma_base (ide_hwif_t *hwif) | |
158 | { | |
159 | unsigned long dma_base = 0; | |
160 | struct pci_dev *dev = hwif->pci_dev; | |
161 | ||
1da177e4 LT |
162 | if (hwif->mmio) |
163 | return hwif->dma_base; | |
164 | ||
165 | if (hwif->mate && hwif->mate->dma_base) { | |
166 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
167 | } else { | |
168 | dma_base = pci_resource_start(dev, 4); | |
169 | if (!dma_base) { | |
170 | printk(KERN_ERR "%s: dma_base is invalid\n", | |
171 | hwif->cds->name); | |
172 | } | |
173 | } | |
174 | ||
1da177e4 LT |
175 | if (dma_base) { |
176 | u8 simplex_stat = 0; | |
177 | dma_base += hwif->channel ? 8 : 0; | |
178 | ||
179 | switch(dev->device) { | |
180 | case PCI_DEVICE_ID_AL_M5219: | |
181 | case PCI_DEVICE_ID_AL_M5229: | |
182 | case PCI_DEVICE_ID_AMD_VIPER_7409: | |
183 | case PCI_DEVICE_ID_CMD_643: | |
184 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
2f09a7f4 | 185 | case PCI_DEVICE_ID_REVOLUTION: |
1da177e4 LT |
186 | simplex_stat = hwif->INB(dma_base + 2); |
187 | hwif->OUTB((simplex_stat&0x60),(dma_base + 2)); | |
188 | simplex_stat = hwif->INB(dma_base + 2); | |
189 | if (simplex_stat & 0x80) { | |
190 | printk(KERN_INFO "%s: simplex device: " | |
191 | "DMA forced\n", | |
192 | hwif->cds->name); | |
193 | } | |
194 | break; | |
195 | default: | |
196 | /* | |
197 | * If the device claims "simplex" DMA, | |
198 | * this means only one of the two interfaces | |
199 | * can be trusted with DMA at any point in time. | |
200 | * So we should enable DMA only on one of the | |
201 | * two interfaces. | |
202 | */ | |
203 | simplex_stat = hwif->INB(dma_base + 2); | |
204 | if (simplex_stat & 0x80) { | |
205 | /* simplex device? */ | |
206 | /* | |
207 | * At this point we haven't probed the drives so we can't make the | |
208 | * appropriate decision. Really we should defer this problem | |
209 | * until we tune the drive then try to grab DMA ownership if we want | |
210 | * to be the DMA end. This has to be become dynamic to handle hot | |
211 | * plug. | |
212 | */ | |
213 | if (hwif->mate && hwif->mate->dma_base) { | |
214 | printk(KERN_INFO "%s: simplex device: " | |
215 | "DMA disabled\n", | |
216 | hwif->cds->name); | |
217 | dma_base = 0; | |
218 | } | |
219 | } | |
220 | } | |
221 | } | |
222 | return dma_base; | |
223 | } | |
224 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
225 | ||
226 | void ide_setup_pci_noise (struct pci_dev *dev, ide_pci_device_t *d) | |
227 | { | |
228 | printk(KERN_INFO "%s: IDE controller at PCI slot %s\n", | |
229 | d->name, pci_name(dev)); | |
230 | } | |
231 | ||
232 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); | |
233 | ||
234 | ||
235 | /** | |
236 | * ide_pci_enable - do PCI enables | |
237 | * @dev: PCI device | |
238 | * @d: IDE pci device data | |
239 | * | |
240 | * Enable the IDE PCI device. We attempt to enable the device in full | |
241 | * but if that fails then we only need BAR4 so we will enable that. | |
242 | * | |
243 | * Returns zero on success or an error code | |
244 | */ | |
245 | ||
246 | static int ide_pci_enable(struct pci_dev *dev, ide_pci_device_t *d) | |
247 | { | |
248 | int ret; | |
249 | ||
250 | if (pci_enable_device(dev)) { | |
251 | ret = pci_enable_device_bars(dev, 1 << 4); | |
252 | if (ret < 0) { | |
253 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
254 | "Could not enable device.\n", d->name); | |
255 | goto out; | |
256 | } | |
257 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
258 | } | |
259 | ||
260 | /* | |
261 | * assume all devices can do 32-bit dma for now. we can add a | |
262 | * dma mask field to the ide_pci_device_t if we need it (or let | |
263 | * lower level driver set the dma mask) | |
264 | */ | |
265 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
266 | if (ret < 0) { | |
267 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
268 | goto out; | |
269 | } | |
270 | ||
271 | /* FIXME: Temporary - until we put in the hotplug interface logic | |
272 | Check that the bits we want are not in use by someone else. */ | |
273 | ret = pci_request_region(dev, 4, "ide_tmp"); | |
274 | if (ret < 0) | |
275 | goto out; | |
276 | ||
277 | pci_release_region(dev, 4); | |
278 | out: | |
279 | return ret; | |
280 | } | |
281 | ||
282 | /** | |
283 | * ide_pci_configure - configure an unconfigured device | |
284 | * @dev: PCI device | |
285 | * @d: IDE pci device data | |
286 | * | |
287 | * Enable and configure the PCI device we have been passed. | |
288 | * Returns zero on success or an error code. | |
289 | */ | |
290 | ||
291 | static int ide_pci_configure(struct pci_dev *dev, ide_pci_device_t *d) | |
292 | { | |
293 | u16 pcicmd = 0; | |
294 | /* | |
295 | * PnP BIOS was *supposed* to have setup this device, but we | |
296 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
297 | * (or possibly the device is using a "legacy header" for IRQs). | |
298 | * Maybe the user deliberately *disabled* the device, | |
299 | * but we'll eventually ignore it again if no drives respond. | |
300 | */ | |
301 | if (ide_setup_pci_baseregs(dev, d->name) || pci_write_config_word(dev, PCI_COMMAND, pcicmd|PCI_COMMAND_IO)) | |
302 | { | |
303 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); | |
304 | return -ENODEV; | |
305 | } | |
306 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
307 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
308 | return -EIO; | |
309 | } | |
310 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
311 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
312 | return -ENXIO; | |
313 | } | |
314 | return 0; | |
315 | } | |
316 | ||
317 | /** | |
318 | * ide_pci_check_iomem - check a register is I/O | |
319 | * @dev: pci device | |
320 | * @d: ide_pci_device | |
321 | * @bar: bar number | |
322 | * | |
323 | * Checks if a BAR is configured and points to MMIO space. If so | |
324 | * print an error and return an error code. Otherwise return 0 | |
325 | */ | |
326 | ||
327 | static int ide_pci_check_iomem(struct pci_dev *dev, ide_pci_device_t *d, int bar) | |
328 | { | |
329 | ulong flags = pci_resource_flags(dev, bar); | |
330 | ||
331 | /* Unconfigured ? */ | |
332 | if (!flags || pci_resource_len(dev, bar) == 0) | |
333 | return 0; | |
334 | ||
335 | /* I/O space */ | |
336 | if(flags & PCI_BASE_ADDRESS_IO_MASK) | |
337 | return 0; | |
338 | ||
339 | /* Bad */ | |
340 | printk(KERN_ERR "%s: IO baseregs (BIOS) are reported " | |
341 | "as MEM, report to " | |
342 | "<andre@linux-ide.org>.\n", d->name); | |
343 | return -EINVAL; | |
344 | } | |
345 | ||
346 | /** | |
347 | * ide_hwif_configure - configure an IDE interface | |
348 | * @dev: PCI device holding interface | |
349 | * @d: IDE pci data | |
350 | * @mate: Paired interface if any | |
351 | * | |
352 | * Perform the initial set up for the hardware interface structure. This | |
353 | * is done per interface port rather than per PCI device. There may be | |
354 | * more than one port per device. | |
355 | * | |
356 | * Returns the new hardware interface structure, or NULL on a failure | |
357 | */ | |
358 | ||
359 | static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *mate, int port, int irq) | |
360 | { | |
361 | unsigned long ctl = 0, base = 0; | |
362 | ide_hwif_t *hwif; | |
363 | ||
a5d8c5c8 | 364 | if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { |
1da177e4 LT |
365 | /* Possibly we should fail if these checks report true */ |
366 | ide_pci_check_iomem(dev, d, 2*port); | |
367 | ide_pci_check_iomem(dev, d, 2*port+1); | |
368 | ||
369 | ctl = pci_resource_start(dev, 2*port+1); | |
370 | base = pci_resource_start(dev, 2*port); | |
371 | if ((ctl && !base) || (base && !ctl)) { | |
372 | printk(KERN_ERR "%s: inconsistent baseregs (BIOS) " | |
373 | "for port %d, skipping\n", d->name, port); | |
374 | return NULL; | |
375 | } | |
376 | } | |
377 | if (!ctl) | |
378 | { | |
379 | /* Use default values */ | |
380 | ctl = port ? 0x374 : 0x3f4; | |
381 | base = port ? 0x170 : 0x1f0; | |
382 | } | |
383 | if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL) | |
384 | return NULL; /* no room in ide_hwifs[] */ | |
385 | if (hwif->io_ports[IDE_DATA_OFFSET] != base || | |
386 | hwif->io_ports[IDE_CONTROL_OFFSET] != (ctl | 2)) { | |
387 | memset(&hwif->hw, 0, sizeof(hwif->hw)); | |
388 | #ifndef IDE_ARCH_OBSOLETE_INIT | |
389 | ide_std_init_ports(&hwif->hw, base, (ctl | 2)); | |
390 | hwif->hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
391 | #else | |
392 | ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL); | |
393 | #endif | |
394 | memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports)); | |
395 | hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET]; | |
396 | } | |
397 | hwif->chipset = ide_pci; | |
398 | hwif->pci_dev = dev; | |
399 | hwif->cds = (struct ide_pci_device_s *) d; | |
400 | hwif->channel = port; | |
401 | ||
402 | if (!hwif->irq) | |
403 | hwif->irq = irq; | |
404 | if (mate) { | |
405 | hwif->mate = mate; | |
406 | mate->mate = hwif; | |
407 | } | |
408 | return hwif; | |
409 | } | |
410 | ||
411 | /** | |
412 | * ide_hwif_setup_dma - configure DMA interface | |
413 | * @dev: PCI device | |
414 | * @d: IDE pci data | |
415 | * @hwif: Hardware interface we are configuring | |
416 | * | |
417 | * Set up the DMA base for the interface. Enable the master bits as | |
418 | * necessary and attempt to bring the device DMA into a ready to use | |
419 | * state | |
420 | */ | |
421 | ||
422 | #ifndef CONFIG_BLK_DEV_IDEDMA_PCI | |
423 | static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif) | |
424 | { | |
425 | } | |
426 | #else | |
427 | static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif) | |
428 | { | |
429 | u16 pcicmd; | |
430 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
431 | ||
432 | if ((d->autodma == AUTODMA) || | |
433 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && | |
434 | (dev->class & 0x80))) { | |
435 | unsigned long dma_base = ide_get_or_set_dma_base(hwif); | |
436 | if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) { | |
437 | /* | |
438 | * Set up BM-DMA capability | |
439 | * (PnP BIOS should have done this) | |
440 | */ | |
441 | /* default DMA off if we had to configure it here */ | |
442 | hwif->autodma = 0; | |
443 | pci_set_master(dev); | |
444 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) { | |
445 | printk(KERN_ERR "%s: %s error updating PCICMD\n", | |
446 | hwif->name, d->name); | |
447 | dma_base = 0; | |
448 | } | |
449 | } | |
450 | if (dma_base) { | |
451 | if (d->init_dma) { | |
452 | d->init_dma(hwif, dma_base); | |
453 | } else { | |
454 | ide_setup_dma(hwif, dma_base, 8); | |
455 | } | |
456 | } else { | |
457 | printk(KERN_INFO "%s: %s Bus-Master DMA disabled " | |
458 | "(BIOS)\n", hwif->name, d->name); | |
459 | } | |
460 | } | |
461 | } | |
1da177e4 LT |
462 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI*/ |
463 | ||
464 | /** | |
465 | * ide_setup_pci_controller - set up IDE PCI | |
466 | * @dev: PCI device | |
467 | * @d: IDE PCI data | |
468 | * @noisy: verbose flag | |
469 | * @config: returned as 1 if we configured the hardware | |
470 | * | |
471 | * Set up the PCI and controller side of the IDE interface. This brings | |
472 | * up the PCI side of the device, checks that the device is enabled | |
473 | * and enables it if need be | |
474 | */ | |
475 | ||
476 | static int ide_setup_pci_controller(struct pci_dev *dev, ide_pci_device_t *d, int noisy, int *config) | |
477 | { | |
478 | int ret; | |
479 | u32 class_rev; | |
480 | u16 pcicmd; | |
481 | ||
482 | if (noisy) | |
483 | ide_setup_pci_noise(dev, d); | |
484 | ||
485 | ret = ide_pci_enable(dev, d); | |
486 | if (ret < 0) | |
487 | goto out; | |
488 | ||
489 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
490 | if (ret < 0) { | |
491 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
492 | goto out; | |
493 | } | |
494 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
495 | ret = ide_pci_configure(dev, d); | |
496 | if (ret < 0) | |
497 | goto out; | |
498 | *config = 1; | |
499 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); | |
500 | } | |
501 | ||
502 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
503 | class_rev &= 0xff; | |
504 | if (noisy) | |
505 | printk(KERN_INFO "%s: chipset revision %d\n", d->name, class_rev); | |
506 | out: | |
507 | return ret; | |
508 | } | |
509 | ||
510 | /** | |
511 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
512 | * @dev: PCI device | |
513 | * @d: IDE pci device info | |
514 | * @pciirq: IRQ line | |
515 | * @index: ata index to update | |
516 | * | |
517 | * Scan the interfaces attached to this device and do any | |
518 | * necessary per port setup. Attach the devices and ask the | |
519 | * generic DMA layer to do its work for us. | |
520 | * | |
521 | * Normally called automaticall from do_ide_pci_setup_device, | |
522 | * but is also used directly as a helper function by some controllers | |
523 | * where the chipset setup is not the default PCI IDE one. | |
524 | */ | |
525 | ||
526 | void ide_pci_setup_ports(struct pci_dev *dev, ide_pci_device_t *d, int pciirq, ata_index_t *index) | |
527 | { | |
a5d8c5c8 | 528 | int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; |
1da177e4 LT |
529 | int at_least_one_hwif_enabled = 0; |
530 | ide_hwif_t *hwif, *mate = NULL; | |
1da177e4 LT |
531 | u8 tmp; |
532 | ||
533 | index->all = 0xf0f0; | |
534 | ||
535 | /* | |
536 | * Set up the IDE ports | |
537 | */ | |
538 | ||
a5d8c5c8 | 539 | for (port = 0; port < channels; ++port) { |
1da177e4 LT |
540 | ide_pci_enablebit_t *e = &(d->enablebits[port]); |
541 | ||
1da177e4 LT |
542 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || |
543 | (tmp & e->mask) != e->val)) | |
544 | continue; /* port not enabled */ | |
1da177e4 | 545 | |
1da177e4 LT |
546 | if ((hwif = ide_hwif_configure(dev, d, mate, port, pciirq)) == NULL) |
547 | continue; | |
548 | ||
549 | /* setup proper ancestral information */ | |
550 | hwif->gendev.parent = &dev->dev; | |
551 | ||
552 | if (hwif->channel) { | |
553 | index->b.high = hwif->index; | |
554 | } else { | |
555 | index->b.low = hwif->index; | |
556 | } | |
557 | ||
558 | ||
559 | if (d->init_iops) | |
560 | d->init_iops(hwif); | |
561 | ||
562 | if (d->autodma == NODMA) | |
563 | goto bypass_legacy_dma; | |
564 | ||
565 | if(d->init_setup_dma) | |
566 | d->init_setup_dma(dev, d, hwif); | |
567 | else | |
568 | ide_hwif_setup_dma(dev, d, hwif); | |
569 | bypass_legacy_dma: | |
6a824c92 | 570 | hwif->host_flags = d->host_flags; |
4099d143 | 571 | hwif->pio_mask = d->pio_mask; |
6a824c92 | 572 | |
1da177e4 LT |
573 | if (d->init_hwif) |
574 | /* Call chipset-specific routine | |
575 | * for each enabled hwif | |
576 | */ | |
577 | d->init_hwif(hwif); | |
578 | ||
579 | mate = hwif; | |
580 | at_least_one_hwif_enabled = 1; | |
581 | } | |
582 | if (!at_least_one_hwif_enabled) | |
583 | printk(KERN_INFO "%s: neither IDE port enabled (BIOS)\n", d->name); | |
584 | } | |
585 | ||
586 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); | |
587 | ||
588 | /* | |
589 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
590 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
591 | * for use with them. This generic code works for most PCI chipsets. | |
592 | * | |
593 | * One thing that is not standardized is the location of the | |
594 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
595 | * we "know" about, this information is in the ide_pci_device_t struct; | |
596 | * for all other chipsets, we just assume both interfaces are enabled. | |
597 | */ | |
598 | static int do_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d, | |
599 | ata_index_t *index, u8 noisy) | |
600 | { | |
601 | static ata_index_t ata_index = { .b = { .low = 0xff, .high = 0xff } }; | |
602 | int tried_config = 0; | |
603 | int pciirq, ret; | |
604 | ||
605 | ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); | |
606 | if (ret < 0) | |
607 | goto out; | |
608 | ||
609 | /* | |
610 | * Can we trust the reported IRQ? | |
611 | */ | |
612 | pciirq = dev->irq; | |
613 | ||
614 | /* Is it an "IDE storage" device in non-PCI mode? */ | |
615 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
616 | if (noisy) | |
617 | printk(KERN_INFO "%s: not 100%% native mode: " | |
618 | "will probe irqs later\n", d->name); | |
619 | /* | |
620 | * This allows offboard ide-pci cards the enable a BIOS, | |
621 | * verify interrupt settings of split-mirror pci-config | |
622 | * space, place chipset into init-mode, and/or preserve | |
623 | * an interrupt if the card is not native ide support. | |
624 | */ | |
625 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
626 | if (ret < 0) | |
627 | goto out; | |
628 | pciirq = ret; | |
629 | } else if (tried_config) { | |
630 | if (noisy) | |
631 | printk(KERN_INFO "%s: will probe irqs later\n", d->name); | |
632 | pciirq = 0; | |
633 | } else if (!pciirq) { | |
634 | if (noisy) | |
635 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
636 | d->name, pciirq); | |
637 | pciirq = 0; | |
638 | } else { | |
639 | if (d->init_chipset) { | |
640 | ret = d->init_chipset(dev, d->name); | |
641 | if (ret < 0) | |
642 | goto out; | |
643 | } | |
644 | if (noisy) | |
1da177e4 LT |
645 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", |
646 | d->name, pciirq); | |
1da177e4 LT |
647 | } |
648 | ||
649 | /* FIXME: silent failure can happen */ | |
650 | ||
651 | *index = ata_index; | |
652 | ide_pci_setup_ports(dev, d, pciirq, index); | |
653 | out: | |
654 | return ret; | |
655 | } | |
656 | ||
657 | int ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d) | |
658 | { | |
5cbf79cd | 659 | ide_hwif_t *hwif = NULL, *mate = NULL; |
1da177e4 LT |
660 | ata_index_t index_list; |
661 | int ret; | |
662 | ||
663 | ret = do_ide_setup_pci_device(dev, d, &index_list, 1); | |
664 | if (ret < 0) | |
665 | goto out; | |
666 | ||
667 | if ((index_list.b.low & 0xf0) != 0xf0) | |
5cbf79cd | 668 | hwif = &ide_hwifs[index_list.b.low]; |
1da177e4 | 669 | if ((index_list.b.high & 0xf0) != 0xf0) |
5cbf79cd | 670 | mate = &ide_hwifs[index_list.b.high]; |
1da177e4 | 671 | |
5cbf79cd BZ |
672 | if (hwif) |
673 | probe_hwif_init_with_fixup(hwif, d->fixup); | |
674 | if (mate) | |
675 | probe_hwif_init_with_fixup(mate, d->fixup); | |
676 | ||
677 | if (hwif) | |
678 | ide_proc_register_port(hwif); | |
679 | if (mate) | |
680 | ide_proc_register_port(mate); | |
1da177e4 LT |
681 | out: |
682 | return ret; | |
683 | } | |
684 | ||
685 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); | |
686 | ||
687 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
688 | ide_pci_device_t *d) | |
689 | { | |
690 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
691 | ata_index_t index_list[2]; | |
692 | int ret, i; | |
693 | ||
694 | for (i = 0; i < 2; i++) { | |
695 | ret = do_ide_setup_pci_device(pdev[i], d, index_list + i, !i); | |
696 | /* | |
697 | * FIXME: Mom, mom, they stole me the helper function to undo | |
698 | * do_ide_setup_pci_device() on the first device! | |
699 | */ | |
700 | if (ret < 0) | |
701 | goto out; | |
702 | } | |
703 | ||
704 | for (i = 0; i < 2; i++) { | |
705 | u8 idx[2] = { index_list[i].b.low, index_list[i].b.high }; | |
706 | int j; | |
707 | ||
708 | for (j = 0; j < 2; j++) { | |
709 | if ((idx[j] & 0xf0) != 0xf0) | |
710 | probe_hwif_init(ide_hwifs + idx[j]); | |
711 | } | |
712 | } | |
713 | ||
5cbf79cd BZ |
714 | for (i = 0; i < 2; i++) { |
715 | u8 idx[2] = { index_list[i].b.low, index_list[i].b.high }; | |
716 | int j; | |
717 | ||
718 | for (j = 0; j < 2; j++) { | |
719 | if ((idx[j] & 0xf0) != 0xf0) | |
720 | ide_proc_register_port(ide_hwifs + idx[j]); | |
721 | } | |
722 | } | |
1da177e4 LT |
723 | out: |
724 | return ret; | |
725 | } | |
726 | ||
727 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); | |
728 | ||
6d208b39 | 729 | #ifdef CONFIG_IDEPCI_PCIBUS_ORDER |
1da177e4 LT |
730 | /* |
731 | * Module interfaces | |
732 | */ | |
733 | ||
734 | static int pre_init = 1; /* Before first ordered IDE scan */ | |
735 | static LIST_HEAD(ide_pci_drivers); | |
736 | ||
737 | /* | |
c37ea218 | 738 | * __ide_pci_register_driver - attach IDE driver |
1da177e4 | 739 | * @driver: pci driver |
863b18f4 | 740 | * @module: owner module of the driver |
1da177e4 LT |
741 | * |
742 | * Registers a driver with the IDE layer. The IDE layer arranges that | |
743 | * boot time setup is done in the expected device order and then | |
744 | * hands the controllers off to the core PCI code to do the rest of | |
745 | * the work. | |
746 | * | |
747 | * The driver_data of the driver table must point to an ide_pci_device_t | |
748 | * describing the interface. | |
749 | * | |
750 | * Returns are the same as for pci_register_driver | |
751 | */ | |
752 | ||
725522b5 GKH |
753 | int __ide_pci_register_driver(struct pci_driver *driver, struct module *module, |
754 | const char *mod_name) | |
1da177e4 LT |
755 | { |
756 | if(!pre_init) | |
725522b5 | 757 | return __pci_register_driver(driver, module, mod_name); |
863b18f4 | 758 | driver->driver.owner = module; |
1da177e4 LT |
759 | list_add_tail(&driver->node, &ide_pci_drivers); |
760 | return 0; | |
761 | } | |
762 | ||
863b18f4 | 763 | EXPORT_SYMBOL_GPL(__ide_pci_register_driver); |
1da177e4 | 764 | |
1da177e4 LT |
765 | /** |
766 | * ide_scan_pcidev - find an IDE driver for a device | |
767 | * @dev: PCI device to check | |
768 | * | |
769 | * Look for an IDE driver to handle the device we are considering. | |
770 | * This is only used during boot up to get the ordering correct. After | |
771 | * boot up the pci layer takes over the job. | |
772 | */ | |
773 | ||
774 | static int __init ide_scan_pcidev(struct pci_dev *dev) | |
775 | { | |
776 | struct list_head *l; | |
777 | struct pci_driver *d; | |
778 | ||
0505b55f | 779 | list_for_each(l, &ide_pci_drivers) { |
1da177e4 | 780 | d = list_entry(l, struct pci_driver, node); |
0505b55f SS |
781 | if (d->id_table) { |
782 | const struct pci_device_id *id = pci_match_id(d->id_table, | |
783 | dev); | |
784 | if (id != NULL && d->probe(dev, id) >= 0) { | |
785 | dev->driver = d; | |
786 | pci_dev_get(dev); | |
787 | return 1; | |
1da177e4 LT |
788 | } |
789 | } | |
790 | } | |
791 | return 0; | |
792 | } | |
793 | ||
794 | /** | |
795 | * ide_scan_pcibus - perform the initial IDE driver scan | |
796 | * @scan_direction: set for reverse order scanning | |
797 | * | |
798 | * Perform the initial bus rather than driver ordered scan of the | |
799 | * PCI drivers. After this all IDE pci handling becomes standard | |
800 | * module ordering not traditionally ordered. | |
801 | */ | |
802 | ||
803 | void __init ide_scan_pcibus (int scan_direction) | |
804 | { | |
805 | struct pci_dev *dev = NULL; | |
806 | struct pci_driver *d; | |
807 | struct list_head *l, *n; | |
808 | ||
809 | pre_init = 0; | |
0505b55f SS |
810 | if (!scan_direction) |
811 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) | |
1da177e4 | 812 | ide_scan_pcidev(dev); |
0505b55f SS |
813 | else |
814 | while ((dev = pci_get_device_reverse(PCI_ANY_ID, PCI_ANY_ID, dev)) | |
815 | != NULL) | |
1da177e4 | 816 | ide_scan_pcidev(dev); |
1da177e4 LT |
817 | |
818 | /* | |
819 | * Hand the drivers over to the PCI layer now we | |
820 | * are post init. | |
821 | */ | |
822 | ||
d61bcce9 | 823 | list_for_each_safe(l, n, &ide_pci_drivers) { |
1da177e4 LT |
824 | list_del(l); |
825 | d = list_entry(l, struct pci_driver, node); | |
0505b55f SS |
826 | if (__pci_register_driver(d, d->driver.owner, d->driver.mod_name)) |
827 | printk(KERN_ERR "%s: failed to register driver for %s\n", | |
828 | __FUNCTION__, d->driver.mod_name); | |
1da177e4 LT |
829 | } |
830 | } | |
6d208b39 | 831 | #endif |