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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * SL82C105/Winbond 553 IDE driver |
4 | * | |
5 | * Maintainer unknown. | |
6 | * | |
7 | * Drive tuning added from Rebel.com's kernel sources | |
8 | * -- Russell King (15/11/98) linux@arm.linux.org.uk | |
9 | * | |
10 | * Merge in Russell's HW workarounds, fix various problems | |
11 | * with the timing registers setup. | |
12 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org | |
e93df705 | 13 | * |
75c2d7d7 | 14 | * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com> |
6ae8b1ef | 15 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
1da177e4 LT |
21 | #include <linux/pci.h> |
22 | #include <linux/ide.h> | |
23 | ||
24 | #include <asm/io.h> | |
1da177e4 | 25 | |
ced3ec8a BZ |
26 | #define DRV_NAME "sl82c105" |
27 | ||
1da177e4 LT |
28 | /* |
29 | * SL82C105 PCI config register 0x40 bits. | |
30 | */ | |
31 | #define CTRL_IDE_IRQB (1 << 30) | |
32 | #define CTRL_IDE_IRQA (1 << 28) | |
33 | #define CTRL_LEGIRQ (1 << 11) | |
34 | #define CTRL_P1F16 (1 << 5) | |
35 | #define CTRL_P1EN (1 << 4) | |
36 | #define CTRL_P0F16 (1 << 1) | |
37 | #define CTRL_P0EN (1 << 0) | |
38 | ||
39 | /* | |
e93df705 SS |
40 | * Convert a PIO mode and cycle time to the required on/off times |
41 | * for the interface. This has protection against runaway timings. | |
1da177e4 | 42 | */ |
7dd00083 | 43 | static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) |
1da177e4 | 44 | { |
3f847571 | 45 | struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); |
e93df705 | 46 | unsigned int cmd_on, cmd_off; |
2229833c | 47 | u8 iordy = 0; |
1da177e4 | 48 | |
3f847571 | 49 | cmd_on = (t->active + 29) / 30; |
7dd00083 | 50 | cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; |
1da177e4 | 51 | |
1da177e4 LT |
52 | if (cmd_on == 0) |
53 | cmd_on = 1; | |
54 | ||
1da177e4 LT |
55 | if (cmd_off == 0) |
56 | cmd_off = 1; | |
57 | ||
c9ef59ff | 58 | if (ide_pio_need_iordy(drive, pio)) |
2229833c BZ |
59 | iordy = 0x40; |
60 | ||
61 | return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; | |
1da177e4 LT |
62 | } |
63 | ||
64 | /* | |
e93df705 | 65 | * Configure the chipset for PIO mode. |
1da177e4 | 66 | */ |
e085b3ca | 67 | static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
1da177e4 | 68 | { |
e085b3ca | 69 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
5bfb151f | 70 | unsigned long timings = (unsigned long)ide_get_drivedata(drive); |
e93df705 | 71 | int reg = 0x44 + drive->dn * 4; |
e93df705 | 72 | u16 drv_ctrl; |
e085b3ca | 73 | const u8 pio = drive->pio_mode - XFER_PIO_0; |
1da177e4 | 74 | |
7dd00083 | 75 | drv_ctrl = get_pio_timings(drive, pio); |
46cedc9b SS |
76 | |
77 | /* | |
78 | * Store the PIO timings so that we can restore them | |
79 | * in case DMA will be turned off... | |
80 | */ | |
5bfb151f JR |
81 | timings &= 0xffff0000; |
82 | timings |= drv_ctrl; | |
83 | ide_set_drivedata(drive, (void *)timings); | |
1da177e4 | 84 | |
6ae8b1ef BZ |
85 | pci_write_config_word(dev, reg, drv_ctrl); |
86 | pci_read_config_word (dev, reg, &drv_ctrl); | |
e93df705 SS |
87 | |
88 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, | |
7dd00083 BZ |
89 | ide_xfer_verbose(pio + XFER_PIO_0), |
90 | ide_pio_cycle_time(drive, pio), drv_ctrl); | |
1da177e4 LT |
91 | } |
92 | ||
46cedc9b | 93 | /* |
88b2b32b | 94 | * Configure the chipset for DMA mode. |
46cedc9b | 95 | */ |
8776168c | 96 | static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
46cedc9b SS |
97 | { |
98 | static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; | |
5bfb151f | 99 | unsigned long timings = (unsigned long)ide_get_drivedata(drive); |
46cedc9b | 100 | u16 drv_ctrl; |
8776168c | 101 | const u8 speed = drive->dma_mode; |
46cedc9b | 102 | |
4db90a14 | 103 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; |
46cedc9b | 104 | |
4db90a14 BZ |
105 | /* |
106 | * Store the DMA timings so that we can actually program | |
107 | * them when DMA will be turned on... | |
108 | */ | |
5bfb151f JR |
109 | timings &= 0x0000ffff; |
110 | timings |= (unsigned long)drv_ctrl << 16; | |
111 | ide_set_drivedata(drive, (void *)timings); | |
46cedc9b SS |
112 | } |
113 | ||
3779f818 SS |
114 | static int sl82c105_test_irq(ide_hwif_t *hwif) |
115 | { | |
116 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
117 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; | |
118 | ||
119 | pci_read_config_dword(dev, 0x40, &val); | |
120 | ||
121 | return (val & mask) ? 1 : 0; | |
122 | } | |
123 | ||
1da177e4 LT |
124 | /* |
125 | * The SL82C105 holds off all IDE interrupts while in DMA mode until | |
126 | * all DMA activity is completed. Sometimes this causes problems (eg, | |
127 | * when the drive wants to report an error condition). | |
128 | * | |
129 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller | |
130 | * state machine. We need to kick this to work around various bugs. | |
131 | */ | |
132 | static inline void sl82c105_reset_host(struct pci_dev *dev) | |
133 | { | |
134 | u16 val; | |
135 | ||
136 | pci_read_config_word(dev, 0x7e, &val); | |
137 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); | |
138 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); | |
139 | } | |
140 | ||
141 | /* | |
142 | * If we get an IRQ timeout, it might be that the DMA state machine | |
143 | * got confused. Fix from Todd Inglett. Details from Winbond. | |
144 | * | |
145 | * This function is called when the IDE timer expires, the drive | |
146 | * indicates that it is READY, and we were waiting for DMA to complete. | |
147 | */ | |
841d2a9b | 148 | static void sl82c105_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 149 | { |
898ec223 | 150 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 151 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
688a87d1 SS |
152 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; |
153 | u8 dma_cmd; | |
1da177e4 | 154 | |
75c2d7d7 | 155 | printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n"); |
1da177e4 LT |
156 | |
157 | /* | |
158 | * Check the raw interrupt from the drive. | |
159 | */ | |
160 | pci_read_config_dword(dev, 0x40, &val); | |
161 | if (val & mask) | |
75c2d7d7 SS |
162 | printk(KERN_INFO "sl82c105: drive was requesting IRQ, " |
163 | "but host lost it\n"); | |
1da177e4 LT |
164 | |
165 | /* | |
166 | * Was DMA enabled? If so, disable it - we're resetting the | |
167 | * host. The IDE layer will be handling the drive for us. | |
168 | */ | |
cab7f8ed | 169 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
688a87d1 | 170 | if (dma_cmd & 1) { |
cab7f8ed | 171 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
75c2d7d7 | 172 | printk(KERN_INFO "sl82c105: DMA was enabled\n"); |
1da177e4 LT |
173 | } |
174 | ||
175 | sl82c105_reset_host(dev); | |
1da177e4 LT |
176 | } |
177 | ||
178 | /* | |
179 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. | |
180 | * Winbond recommend that the DMA state machine is reset prior to | |
181 | * setting the bus master DMA enable bit. | |
182 | * | |
183 | * The generic IDE core will have disabled the BMEN bit before this | |
184 | * function is called. | |
185 | */ | |
688a87d1 | 186 | static void sl82c105_dma_start(ide_drive_t *drive) |
1da177e4 | 187 | { |
898ec223 | 188 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 189 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
6ae8b1ef BZ |
190 | int reg = 0x44 + drive->dn * 4; |
191 | ||
5bfb151f JR |
192 | pci_write_config_word(dev, reg, |
193 | (unsigned long)ide_get_drivedata(drive) >> 16); | |
1da177e4 LT |
194 | |
195 | sl82c105_reset_host(dev); | |
196 | ide_dma_start(drive); | |
197 | } | |
198 | ||
35c9b4da | 199 | static void sl82c105_dma_clear(ide_drive_t *drive) |
1da177e4 | 200 | { |
36501650 BZ |
201 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
202 | ||
36501650 | 203 | sl82c105_reset_host(dev); |
1da177e4 LT |
204 | } |
205 | ||
6ae8b1ef | 206 | static int sl82c105_dma_end(ide_drive_t *drive) |
1da177e4 | 207 | { |
36501650 | 208 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
e93df705 | 209 | int reg = 0x44 + drive->dn * 4; |
f9288e15 | 210 | int ret = ide_dma_end(drive); |
7469aaf6 | 211 | |
5bfb151f JR |
212 | pci_write_config_word(dev, reg, |
213 | (unsigned long)ide_get_drivedata(drive)); | |
e93df705 | 214 | |
6ae8b1ef | 215 | return ret; |
1da177e4 LT |
216 | } |
217 | ||
1da177e4 LT |
218 | /* |
219 | * ATA reset will clear the 16 bits mode in the control | |
08590556 | 220 | * register, we need to reprogram it |
1da177e4 LT |
221 | */ |
222 | static void sl82c105_resetproc(ide_drive_t *drive) | |
223 | { | |
36501650 | 224 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
1da177e4 LT |
225 | u32 val; |
226 | ||
1da177e4 | 227 | pci_read_config_dword(dev, 0x40, &val); |
08590556 BZ |
228 | val |= (CTRL_P1F16 | CTRL_P0F16); |
229 | pci_write_config_dword(dev, 0x40, val); | |
1da177e4 | 230 | } |
1da177e4 LT |
231 | |
232 | /* | |
233 | * Return the revision of the Winbond bridge | |
234 | * which this function is part of. | |
235 | */ | |
6c610641 | 236 | static u8 sl82c105_bridge_revision(struct pci_dev *dev) |
1da177e4 LT |
237 | { |
238 | struct pci_dev *bridge; | |
1da177e4 LT |
239 | |
240 | /* | |
241 | * The bridge should be part of the same device, but function 0. | |
242 | */ | |
8c016394 SK |
243 | bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), |
244 | dev->bus->number, | |
245 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
1da177e4 LT |
246 | if (!bridge) |
247 | return -1; | |
248 | ||
249 | /* | |
250 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
251 | */ | |
252 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
253 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
640b31bf AC |
254 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { |
255 | pci_dev_put(bridge); | |
1da177e4 | 256 | return -1; |
640b31bf | 257 | } |
1da177e4 LT |
258 | /* |
259 | * We need to find function 0's revision, not function 1 | |
260 | */ | |
640b31bf | 261 | pci_dev_put(bridge); |
1da177e4 | 262 | |
44c10138 | 263 | return bridge->revision; |
1da177e4 LT |
264 | } |
265 | ||
266 | /* | |
267 | * Enable the PCI device | |
268 | * | |
269 | * --BenH: It's arch fixup code that should enable channels that | |
270 | * have not been enabled by firmware. I decided we can still enable | |
271 | * channel 0 here at least, but channel 1 has to be enabled by | |
272 | * firmware or arch code. We still set both to 16 bits mode. | |
273 | */ | |
2ed0ef54 | 274 | static int init_chipset_sl82c105(struct pci_dev *dev) |
1da177e4 LT |
275 | { |
276 | u32 val; | |
277 | ||
1da177e4 LT |
278 | pci_read_config_dword(dev, 0x40, &val); |
279 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
280 | pci_write_config_dword(dev, 0x40, val); | |
281 | ||
2ed0ef54 | 282 | return 0; |
1da177e4 LT |
283 | } |
284 | ||
ac95beed BZ |
285 | static const struct ide_port_ops sl82c105_port_ops = { |
286 | .set_pio_mode = sl82c105_set_pio_mode, | |
287 | .set_dma_mode = sl82c105_set_dma_mode, | |
288 | .resetproc = sl82c105_resetproc, | |
3779f818 | 289 | .test_irq = sl82c105_test_irq, |
ac95beed BZ |
290 | }; |
291 | ||
f37afdac BZ |
292 | static const struct ide_dma_ops sl82c105_dma_ops = { |
293 | .dma_host_set = ide_dma_host_set, | |
294 | .dma_setup = ide_dma_setup, | |
5e37bdc0 BZ |
295 | .dma_start = sl82c105_dma_start, |
296 | .dma_end = sl82c105_dma_end, | |
f37afdac | 297 | .dma_test_irq = ide_dma_test_irq, |
5e37bdc0 | 298 | .dma_lost_irq = sl82c105_dma_lost_irq, |
22117d6e | 299 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
35c9b4da | 300 | .dma_clear = sl82c105_dma_clear, |
592b5315 | 301 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
302 | }; |
303 | ||
fe31edc8 | 304 | static const struct ide_port_info sl82c105_chipset = { |
ced3ec8a | 305 | .name = DRV_NAME, |
1da177e4 | 306 | .init_chipset = init_chipset_sl82c105, |
1da177e4 | 307 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, |
ac95beed | 308 | .port_ops = &sl82c105_port_ops, |
5e37bdc0 | 309 | .dma_ops = &sl82c105_dma_ops, |
caea7602 BZ |
310 | .host_flags = IDE_HFLAG_IO_32BIT | |
311 | IDE_HFLAG_UNMASK_IRQS | | |
1fd18905 | 312 | IDE_HFLAG_SERIALIZE_DMA | |
5e71d9c5 | 313 | IDE_HFLAG_NO_AUTODMA, |
4099d143 | 314 | .pio_mask = ATA_PIO5, |
6c610641 | 315 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
316 | }; |
317 | ||
fe31edc8 | 318 | static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 319 | { |
6c610641 BZ |
320 | struct ide_port_info d = sl82c105_chipset; |
321 | u8 rev = sl82c105_bridge_revision(dev); | |
322 | ||
323 | if (rev <= 5) { | |
324 | /* | |
325 | * Never ever EVER under any circumstances enable | |
326 | * DMA when the bridge is this old. | |
327 | */ | |
ced3ec8a | 328 | printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge " |
6c610641 | 329 | "revision %d, BM-DMA disabled\n", rev); |
5e37bdc0 | 330 | d.dma_ops = NULL; |
6c610641 | 331 | d.mwdma_mask = 0; |
1fd18905 | 332 | d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA; |
6c610641 BZ |
333 | } |
334 | ||
6cdf6eb3 | 335 | return ide_pci_init_one(dev, &d, NULL); |
1da177e4 LT |
336 | } |
337 | ||
9cbcc5e3 BZ |
338 | static const struct pci_device_id sl82c105_pci_tbl[] = { |
339 | { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 }, | |
1da177e4 LT |
340 | { 0, }, |
341 | }; | |
342 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); | |
343 | ||
a9ab09e2 | 344 | static struct pci_driver sl82c105_pci_driver = { |
1da177e4 LT |
345 | .name = "W82C105_IDE", |
346 | .id_table = sl82c105_pci_tbl, | |
347 | .probe = sl82c105_init_one, | |
6ce71998 | 348 | .remove = ide_pci_remove, |
feb22b7f BZ |
349 | .suspend = ide_pci_suspend, |
350 | .resume = ide_pci_resume, | |
1da177e4 LT |
351 | }; |
352 | ||
82ab1eec | 353 | static int __init sl82c105_ide_init(void) |
1da177e4 | 354 | { |
a9ab09e2 | 355 | return ide_pci_register_driver(&sl82c105_pci_driver); |
1da177e4 LT |
356 | } |
357 | ||
6ce71998 BZ |
358 | static void __exit sl82c105_ide_exit(void) |
359 | { | |
a9ab09e2 | 360 | pci_unregister_driver(&sl82c105_pci_driver); |
6ce71998 BZ |
361 | } |
362 | ||
1da177e4 | 363 | module_init(sl82c105_ide_init); |
6ce71998 | 364 | module_exit(sl82c105_ide_exit); |
1da177e4 LT |
365 | |
366 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); | |
367 | MODULE_LICENSE("GPL"); |