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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (c) 1997-1998 Mark Lord |
93c0b560 | 3 | * Copyright (c) 2007 MontaVista Software, Inc. <source@mvista.com> |
58f189fc | 4 | * |
1da177e4 LT |
5 | * May be copied or modified under the terms of the GNU General Public License |
6 | * | |
7 | * June 22, 2004 - get rid of check_region | |
59904159 | 8 | * - Jesper Juhl |
1da177e4 LT |
9 | * |
10 | */ | |
11 | ||
12 | /* | |
13 | * This module provides support for the bus-master IDE DMA function | |
14 | * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards, | |
15 | * including a "Precision Instruments" board. The TRM290 pre-dates | |
16 | * the sff-8038 standard (ide-dma.c) by a few months, and differs | |
17 | * significantly enough to warrant separate routines for some functions, | |
18 | * while re-using others from ide-dma.c. | |
19 | * | |
20 | * EXPERIMENTAL! It works for me (a sample of one). | |
21 | * | |
22 | * Works reliably for me in DMA mode (READs only), | |
23 | * DMA WRITEs are disabled by default (see #define below); | |
24 | * | |
25 | * DMA is not enabled automatically for this chipset, | |
26 | * but can be turned on manually (with "hdparm -d1") at run time. | |
27 | * | |
28 | * I need volunteers with "spare" drives for further testing | |
29 | * and development, and maybe to help figure out the peculiarities. | |
30 | * Even knowing the registers (below), some things behave strangely. | |
31 | */ | |
32 | ||
33 | #define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */ | |
34 | ||
35 | /* | |
36 | * TRM-290 PCI-IDE2 Bus Master Chip | |
37 | * ================================ | |
38 | * The configuration registers are addressed in normal I/O port space | |
39 | * and are used as follows: | |
40 | * | |
41 | * trm290_base depends on jumper settings, and is probed for by ide-dma.c | |
42 | * | |
43 | * trm290_base+2 when WRITTEN: chiptest register (byte, write-only) | |
44 | * bit7 must always be written as "1" | |
45 | * bits6-2 undefined | |
46 | * bit1 1=legacy_compatible_mode, 0=native_pci_mode | |
47 | * bit0 1=test_mode, 0=normal(default) | |
48 | * | |
49 | * trm290_base+2 when READ: status register (byte, read-only) | |
50 | * bits7-2 undefined | |
51 | * bit1 channel0 busmaster interrupt status 0=none, 1=asserted | |
52 | * bit0 channel0 interrupt status 0=none, 1=asserted | |
53 | * | |
54 | * trm290_base+3 Interrupt mask register | |
55 | * bits7-5 undefined | |
56 | * bit4 legacy_header: 1=present, 0=absent | |
57 | * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only) | |
58 | * bit2 channel1 interrupt status 0=none, 1=asserted (read only) | |
59 | * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default) | |
60 | * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default) | |
61 | * | |
62 | * trm290_base+1 "CPR" Config Pointer Register (byte) | |
63 | * bit7 1=autoincrement CPR bits 2-0 after each access of CDR | |
64 | * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state | |
65 | * bit5 0=enabled master burst access (default), 1=disable (write only) | |
66 | * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast | |
67 | * bit3 0=primary IDE channel, 1=secondary IDE channel | |
68 | * bits2-0 register index for accesses through CDR port | |
69 | * | |
70 | * trm290_base+0 "CDR" Config Data Register (word) | |
71 | * two sets of seven config registers, | |
72 | * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6), | |
73 | * each index defined below: | |
74 | * | |
75 | * Index-0 Base address register for command block (word) | |
76 | * defaults: 0x1f0 for primary, 0x170 for secondary | |
77 | * | |
78 | * Index-1 general config register (byte) | |
79 | * bit7 1=DMA enable, 0=DMA disable | |
80 | * bit6 1=activate IDE_RESET, 0=no action (default) | |
81 | * bit5 1=enable IORDY, 0=disable IORDY (default) | |
82 | * bit4 0=16-bit data port(default), 1=8-bit (XT) data port | |
83 | * bit3 interrupt polarity: 1=active_low, 0=active_high(default) | |
84 | * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only) | |
85 | * bit1 bus_master_mode(?): 1=enable, 0=disable(default) | |
86 | * bit0 enable_io_ports: 1=enable(default), 0=disable | |
87 | * | |
88 | * Index-2 read-ahead counter preload bits 0-7 (byte, write only) | |
89 | * bits7-0 bits7-0 of readahead count | |
90 | * | |
91 | * Index-3 read-ahead config register (byte, write only) | |
92 | * bit7 1=enable_readahead, 0=disable_readahead(default) | |
93 | * bit6 1=clear_FIFO, 0=no_action | |
94 | * bit5 undefined | |
95 | * bit4 mode4 timing control: 1=enable, 0=disable(default) | |
96 | * bit3 undefined | |
97 | * bit2 undefined | |
98 | * bits1-0 bits9-8 of read-ahead count | |
99 | * | |
100 | * Index-4 base address register for control block (word) | |
101 | * defaults: 0x3f6 for primary, 0x376 for secondary | |
102 | * | |
103 | * Index-5 data port timings (shared by both drives) (byte) | |
104 | * standard PCI "clk" (clock) counts, default value = 0xf5 | |
105 | * | |
106 | * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk | |
107 | * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk, | |
108 | * 011=4clk, 100=5clk, 101=6clk, | |
109 | * 110=8clk, 111=12clk | |
110 | * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk, | |
111 | * 011=5clk, 100=6clk, 101=8clk, | |
112 | * 110=12clk, 111=16clk | |
113 | * | |
114 | * Index-6 command/control port timings (shared by both drives) (byte) | |
115 | * same layout as Index-5, default value = 0xde | |
116 | * | |
117 | * Suggested CDR programming for PIO mode0 (600ns): | |
118 | * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary | |
119 | * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary | |
120 | * | |
121 | * Suggested CDR programming for PIO mode3 (180ns): | |
122 | * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary | |
123 | * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary | |
124 | * | |
125 | * Suggested CDR programming for PIO mode4 (120ns): | |
126 | * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary | |
127 | * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary | |
128 | * | |
129 | */ | |
130 | ||
1da177e4 LT |
131 | #include <linux/types.h> |
132 | #include <linux/module.h> | |
133 | #include <linux/kernel.h> | |
1da177e4 LT |
134 | #include <linux/ioport.h> |
135 | #include <linux/interrupt.h> | |
136 | #include <linux/blkdev.h> | |
137 | #include <linux/init.h> | |
1da177e4 | 138 | #include <linux/pci.h> |
1da177e4 LT |
139 | #include <linux/ide.h> |
140 | ||
141 | #include <asm/io.h> | |
142 | ||
ced3ec8a BZ |
143 | #define DRV_NAME "trm290" |
144 | ||
1da177e4 LT |
145 | static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma) |
146 | { | |
147 | ide_hwif_t *hwif = HWIF(drive); | |
148 | u16 reg = 0; | |
149 | unsigned long flags; | |
150 | ||
151 | /* select PIO or DMA */ | |
152 | reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82); | |
153 | ||
154 | local_irq_save(flags); | |
155 | ||
156 | if (reg != hwif->select_data) { | |
157 | hwif->select_data = reg; | |
158 | /* set PIO/DMA */ | |
0ecdca26 BZ |
159 | outb(0x51 | (hwif->channel << 3), hwif->config_data + 1); |
160 | outw(reg & 0xff, hwif->config_data); | |
1da177e4 LT |
161 | } |
162 | ||
163 | /* enable IRQ if not probing */ | |
97100fc8 | 164 | if (drive->dev_flags & IDE_DFLAG_PRESENT) { |
0ecdca26 | 165 | reg = inw(hwif->config_data + 3); |
1da177e4 LT |
166 | reg &= 0x13; |
167 | reg &= ~(1 << hwif->channel); | |
0ecdca26 | 168 | outw(reg, hwif->config_data + 3); |
1da177e4 LT |
169 | } |
170 | ||
171 | local_irq_restore(flags); | |
172 | } | |
173 | ||
174 | static void trm290_selectproc (ide_drive_t *drive) | |
175 | { | |
97100fc8 | 176 | trm290_prepare_drive(drive, !!(drive->dev_flags & IDE_DFLAG_USING_DMA)); |
1da177e4 LT |
177 | } |
178 | ||
93c0b560 | 179 | static void trm290_dma_exec_cmd(ide_drive_t *drive, u8 command) |
1da177e4 | 180 | { |
c78d7172 | 181 | ide_execute_command(drive, command, &ide_dma_intr, WAIT_CMD, NULL); |
1da177e4 LT |
182 | } |
183 | ||
93c0b560 | 184 | static int trm290_dma_setup(ide_drive_t *drive) |
1da177e4 LT |
185 | { |
186 | ide_hwif_t *hwif = drive->hwif; | |
187 | struct request *rq = hwif->hwgroup->rq; | |
188 | unsigned int count, rw; | |
189 | ||
190 | if (rq_data_dir(rq)) { | |
191 | #ifdef TRM290_NO_DMA_WRITES | |
192 | /* always use PIO for writes */ | |
193 | trm290_prepare_drive(drive, 0); /* select PIO xfer */ | |
194 | return 1; | |
195 | #endif | |
196 | rw = 1; | |
197 | } else | |
198 | rw = 2; | |
199 | ||
200 | if (!(count = ide_build_dmatable(drive, rq))) { | |
201 | /* try PIO instead of DMA */ | |
202 | trm290_prepare_drive(drive, 0); /* select PIO xfer */ | |
203 | return 1; | |
204 | } | |
205 | /* select DMA xfer */ | |
206 | trm290_prepare_drive(drive, 1); | |
4e5a68ae | 207 | outl(hwif->dmatable_dma | rw, hwif->dma_base); |
1da177e4 LT |
208 | drive->waiting_for_dma = 1; |
209 | /* start DMA */ | |
4e5a68ae | 210 | outw(count * 2 - 1, hwif->dma_base + 2); |
1da177e4 LT |
211 | return 0; |
212 | } | |
213 | ||
93c0b560 | 214 | static void trm290_dma_start(ide_drive_t *drive) |
1da177e4 LT |
215 | { |
216 | } | |
217 | ||
5e37bdc0 | 218 | static int trm290_dma_end(ide_drive_t *drive) |
1da177e4 | 219 | { |
4e5a68ae | 220 | u16 status; |
1da177e4 LT |
221 | |
222 | drive->waiting_for_dma = 0; | |
223 | /* purge DMA mappings */ | |
224 | ide_destroy_dmatable(drive); | |
4e5a68ae SS |
225 | status = inw(HWIF(drive)->dma_base + 2); |
226 | return status != 0x00ff; | |
1da177e4 LT |
227 | } |
228 | ||
5e37bdc0 | 229 | static int trm290_dma_test_irq(ide_drive_t *drive) |
1da177e4 | 230 | { |
4e5a68ae | 231 | u16 status; |
1da177e4 | 232 | |
4e5a68ae SS |
233 | status = inw(HWIF(drive)->dma_base + 2); |
234 | return status == 0x00ff; | |
1da177e4 | 235 | } |
1da177e4 | 236 | |
15ce926a | 237 | static void trm290_dma_host_set(ide_drive_t *drive, int on) |
93c0b560 SS |
238 | { |
239 | } | |
240 | ||
1da177e4 LT |
241 | static void __devinit init_hwif_trm290(ide_hwif_t *hwif) |
242 | { | |
36501650 | 243 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4e5a68ae | 244 | unsigned int cfg_base = pci_resource_start(dev, 4); |
1da177e4 LT |
245 | unsigned long flags; |
246 | u8 reg = 0; | |
1da177e4 | 247 | |
4e5a68ae | 248 | if ((dev->class & 5) && cfg_base) |
ced3ec8a | 249 | printk(KERN_INFO DRV_NAME " %s: chip", pci_name(dev)); |
4e5a68ae SS |
250 | else { |
251 | cfg_base = 0x3df0; | |
ced3ec8a | 252 | printk(KERN_INFO DRV_NAME " %s: using default", pci_name(dev)); |
4e5a68ae SS |
253 | } |
254 | printk(KERN_CONT " config base at 0x%04x\n", cfg_base); | |
255 | hwif->config_data = cfg_base; | |
256 | hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0); | |
257 | ||
b8e73fba | 258 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", |
4e5a68ae SS |
259 | hwif->name, hwif->dma_base, hwif->dma_base + 3); |
260 | ||
b8e73fba | 261 | if (ide_allocate_dma_engine(hwif)) |
4e5a68ae | 262 | return; |
1da177e4 LT |
263 | |
264 | local_irq_save(flags); | |
265 | /* put config reg into first byte of hwif->select_data */ | |
0ecdca26 | 266 | outb(0x51 | (hwif->channel << 3), hwif->config_data + 1); |
1da177e4 LT |
267 | /* select PIO as default */ |
268 | hwif->select_data = 0x21; | |
0ecdca26 | 269 | outb(hwif->select_data, hwif->config_data); |
1da177e4 | 270 | /* get IRQ info */ |
0ecdca26 | 271 | reg = inb(hwif->config_data + 3); |
1da177e4 LT |
272 | /* mask IRQs for both ports */ |
273 | reg = (reg & 0x10) | 0x03; | |
0ecdca26 | 274 | outb(reg, hwif->config_data + 3); |
1da177e4 LT |
275 | local_irq_restore(flags); |
276 | ||
4e5a68ae | 277 | if (reg & 0x10) |
1da177e4 LT |
278 | /* legacy mode */ |
279 | hwif->irq = hwif->channel ? 15 : 14; | |
280 | else if (!hwif->irq && hwif->mate && hwif->mate->irq) | |
281 | /* sharing IRQ with mate */ | |
282 | hwif->irq = hwif->mate->irq; | |
283 | ||
1da177e4 LT |
284 | #if 1 |
285 | { | |
286 | /* | |
287 | * My trm290-based card doesn't seem to work with all possible values | |
288 | * for the control basereg, so this kludge ensures that we use only | |
289 | * values that are known to work. Ugh. -ml | |
290 | */ | |
291 | u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4; | |
292 | static u16 next_offset = 0; | |
293 | u8 old_mask; | |
294 | ||
0ecdca26 BZ |
295 | outb(0x54 | (hwif->channel << 3), hwif->config_data + 1); |
296 | old = inw(hwif->config_data); | |
1da177e4 | 297 | old &= ~1; |
0ecdca26 | 298 | old_mask = inb(old + 2); |
1da177e4 LT |
299 | if (old != compat && old_mask == 0xff) { |
300 | /* leave lower 10 bits untouched */ | |
301 | compat += (next_offset += 0x400); | |
4c3032d8 | 302 | hwif->io_ports.ctl_addr = compat + 2; |
0ecdca26 BZ |
303 | outw(compat | 1, hwif->config_data); |
304 | new = inw(hwif->config_data); | |
1da177e4 LT |
305 | printk(KERN_INFO "%s: control basereg workaround: " |
306 | "old=0x%04x, new=0x%04x\n", | |
307 | hwif->name, old, new & ~1); | |
308 | } | |
309 | } | |
310 | #endif | |
311 | } | |
312 | ||
ac95beed BZ |
313 | static const struct ide_port_ops trm290_port_ops = { |
314 | .selectproc = trm290_selectproc, | |
315 | }; | |
316 | ||
5e37bdc0 BZ |
317 | static struct ide_dma_ops trm290_dma_ops = { |
318 | .dma_host_set = trm290_dma_host_set, | |
319 | .dma_setup = trm290_dma_setup, | |
320 | .dma_exec_cmd = trm290_dma_exec_cmd, | |
321 | .dma_start = trm290_dma_start, | |
322 | .dma_end = trm290_dma_end, | |
323 | .dma_test_irq = trm290_dma_test_irq, | |
f37afdac BZ |
324 | .dma_lost_irq = ide_dma_lost_irq, |
325 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
326 | }; |
327 | ||
85620436 | 328 | static const struct ide_port_info trm290_chipset __devinitdata = { |
ced3ec8a | 329 | .name = DRV_NAME, |
1da177e4 | 330 | .init_hwif = init_hwif_trm290, |
528a572d | 331 | .chipset = ide_trm290, |
ac95beed | 332 | .port_ops = &trm290_port_ops, |
5e37bdc0 | 333 | .dma_ops = &trm290_dma_ops, |
7cab14a7 | 334 | .host_flags = IDE_HFLAG_NO_ATAPI_DMA | |
9ff6f72f | 335 | #if 0 /* play it safe for now */ |
7cab14a7 | 336 | IDE_HFLAG_TRUST_BIOS_FOR_DMA | |
9ff6f72f | 337 | #endif |
47b68788 | 338 | IDE_HFLAG_NO_AUTODMA | |
238e4f14 | 339 | IDE_HFLAG_NO_LBA48, |
1da177e4 LT |
340 | }; |
341 | ||
342 | static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
343 | { | |
6cdf6eb3 | 344 | return ide_pci_init_one(dev, &trm290_chipset, NULL); |
1da177e4 LT |
345 | } |
346 | ||
9cbcc5e3 BZ |
347 | static const struct pci_device_id trm290_pci_tbl[] = { |
348 | { PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 }, | |
1da177e4 LT |
349 | { 0, }, |
350 | }; | |
351 | MODULE_DEVICE_TABLE(pci, trm290_pci_tbl); | |
352 | ||
a9ab09e2 | 353 | static struct pci_driver trm290_pci_driver = { |
1da177e4 LT |
354 | .name = "TRM290_IDE", |
355 | .id_table = trm290_pci_tbl, | |
356 | .probe = trm290_init_one, | |
fc2c32b7 | 357 | .remove = ide_pci_remove, |
1da177e4 LT |
358 | }; |
359 | ||
82ab1eec | 360 | static int __init trm290_ide_init(void) |
1da177e4 | 361 | { |
a9ab09e2 | 362 | return ide_pci_register_driver(&trm290_pci_driver); |
1da177e4 LT |
363 | } |
364 | ||
fc2c32b7 BZ |
365 | static void __exit trm290_ide_exit(void) |
366 | { | |
a9ab09e2 | 367 | pci_unregister_driver(&trm290_pci_driver); |
fc2c32b7 BZ |
368 | } |
369 | ||
1da177e4 | 370 | module_init(trm290_ide_init); |
fc2c32b7 | 371 | module_exit(trm290_ide_exit); |
1da177e4 LT |
372 | |
373 | MODULE_AUTHOR("Mark Lord"); | |
374 | MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE"); | |
375 | MODULE_LICENSE("GPL"); |