[mirror_ubuntu-jammy-kernel.git] / drivers / ide / via82cxxx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237, vt8237a
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publicly available from via.com.tw
 *	Current device documentation available under NDA only
 */


#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/dmi.h>

#ifdef CONFIG_PPC_CHRP
#include <asm/processor.h>
#endif

#define DRV_NAME "via82cxxx"

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_BAD_PREQ		0x01 /* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x02 /* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x04 /* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x08 /* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x10 /* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x20 /* Don't touch Address Setup Timing */
#define VIA_SATA_PATA		0x80 /* SATA/PATA combined configuration */

enum {
	VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
};

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u8 udma_mask;
	u8 flags;
} via_isa_bridges[] = {
	{ "vx855",	PCI_DEVICE_ID_VIA_VX855,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "vx800",	PCI_DEVICE_ID_VIA_VX800,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "vt8261",	PCI_DEVICE_ID_VIA_8261,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6415",	PCI_DEVICE_ID_VIA_6415,     0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ "vtxxxx",	PCI_DEVICE_ID_VIA_ANON,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
	case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	}

	/* Set UDMA unless device is not UDMA capable */
	if (vdev->via_config->udma_mask) {
		u8 udma_etc;

		pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc);

		/* clear transfer mode bit */
		udma_etc &= ~0x20;

		if (timing->udma) {
			/* preserve 80-wire cable detection bit */
			udma_etc &= 0x10;
			udma_etc |= t;
		}

		pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc);
	}
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@hwif: port
 *	@drive: Drive to set up
 *
 *	via_set_drive() computes timing values configures the chipset to
 *	a desired transfer mode.  It also can be called by upper layers.
 */

static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
{
	ide_drive_t *peer = ide_get_pair_dev(drive);
	struct ide_host *host = dev_get_drvdata(hwif->dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	struct ide_timing t, p;
	unsigned int T, UT;
	const u8 speed = drive->dma_mode;

	T = 1000000000 / via_clock;

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: UT = T;   break;
	case ATA_UDMA4: UT = T/2; break;
	case ATA_UDMA5: UT = T/3; break;
	case ATA_UDMA6: UT = T/4; break;
	default:	UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer) {
		ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(hwif, drive->dn, &t);
}

/**
 *	via_set_pio_mode	-	set host controller for PIO mode
 *	@hwif: port
 *	@drive: drive
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	drive->dma_mode = drive->pio_mode;
	via_set_drive(hwif, drive);
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;

	for (via_config = via_isa_bridges;
	     via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
		if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			if ((*isa)->revision >= via_config->rev_min &&
			    (*isa)->revision <= via_config->rev_max)
				break;
			pci_dev_put(*isa);
		}

	return via_config;
}

/*
 * Check and handle 80-wire cable presence
 */
static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
{
	int i;

	switch (vdev->via_config->udma_mask) {
		case ATA_UDMA4:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA5:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA6:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;
	}
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static int init_chipset_via82cxxx(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	struct via_isa_bridge *via_config = vdev->via_config;
	u8 t, v;
	u32 u;

	/*
	 * Detect cable and configure Clk66
	 */
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	via_cable_detect(vdev, u);

	if (via_config->udma_mask == ATA_UDMA4) {
		/* Enable Clk66 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	return 0;
}

/*
 *	Cable special cases
 */

static const struct dmi_system_id cable_dmi_table[] = {
	{
		.ident = "Acer Ferrari 3400",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
		},
	},
	{ }
};

static int via_cable_override(struct pci_dev *pdev)
{
	/* Systems by DMI */
	if (dmi_check_system(cable_dmi_table))
		return 1;

	/* Arima W730-K8/Targa Visionary 811/... */
	if (pdev->subsystem_vendor == 0x161F &&
	    pdev->subsystem_device == 0x2032)
		return 1;

	return 0;
}

static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	struct ide_host *host = pci_get_drvdata(pdev);
	struct via82cxxx_dev *vdev = host->host_priv;

	if (via_cable_override(pdev))
		return ATA_CBL_PATA40_SHORT;

	if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
		return ATA_CBL_SATA;

	if ((vdev->via_80w >> hwif->channel) & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static const struct ide_port_ops via_port_ops = {
	.set_pio_mode		= via_set_pio_mode,
	.set_dma_mode		= via_set_drive,
	.cable_detect		= via82cxxx_cable_detect,
};

static const struct ide_port_info via82cxxx_chipset = {
	.name		= DRV_NAME,
	.init_chipset	= init_chipset_via82cxxx,
	.enablebits	= { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
	.port_ops	= &via_port_ops,
	.host_flags	= IDE_HFLAG_PIO_NO_BLACKLIST |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_IO_32BIT,
	.pio_mask	= ATA_PIO5,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	struct via82cxxx_dev *vdev;
	int rc;
	u8 idx = id->driver_data;
	struct ide_port_info d;

	d = via82cxxx_chipset;

	/*
	 * Find the ISA bridge and check we know what it is.
	 */
	via_config = via_config_find(&isa);

	/*
	 * Print the boot message.
	 */
	printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
		pci_name(dev), via_config->name, isa->revision,
		via_config->udma_mask ? "U" : "MW",
		via_dma[via_config->udma_mask ?
			(fls(via_config->udma_mask) - 1) : 0]);

	pci_dev_put(isa);

	/*
	 * Determine system bus clock.
	 */
	via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;

	switch (via_clock) {
	case 33000: via_clock = 33333; break;
	case 37000: via_clock = 37500; break;
	case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		via_clock = 33333;
	}

	if (idx == 1)
		d.enablebits[1].reg = d.enablebits[0].reg = 0;
	else
		d.host_flags |= IDE_HFLAG_NO_AUTODMA;

	if (idx == VIA_IDFLAG_SINGLE)
		d.host_flags |= IDE_HFLAG_SINGLE;

	if ((via_config->flags & VIA_NO_UNMASK) == 0)
		d.host_flags |= IDE_HFLAG_UNMASK_IRQS;

	d.udma_mask = via_config->udma_mask;

	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	if (!vdev) {
		printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
			pci_name(dev));
		return -ENOMEM;
	}

	vdev->via_config = via_config;

	rc = ide_pci_init_one(dev, &d, vdev);
	if (rc)
		kfree(vdev);

	return rc;
}

static void via_remove(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;

	ide_pci_remove(dev);
	kfree(vdev);
}

static const struct pci_device_id via_pci_tbl[] = {
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410),      1 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415),      1 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver via_pci_driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
	.remove		= via_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init via_ide_init(void)
{
	return ide_pci_register_driver(&via_pci_driver);
}

static void __exit via_ide_exit(void)
{
	pci_unregister_driver(&via_pci_driver);
}

module_init(via_ide_init);
module_exit(via_ide_exit);

MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4	2	/*
1da177e4 LT	3	* VIA IDE driver for Linux. Supported southbridges:
	4	*
	5	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	6	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
a7dec1e0	7	* vt8235, vt8237, vt8237a
1da177e4 LT	8	*
1da177e4 LT	9	* Copyright (c) 2000-2002 Vojtech Pavlik
42036c85	10	* Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
1da177e4 LT	11	*
	12	* Based on the work of:
	13	* Michel Aubry
	14	* Jeff Garzik
	15	* Andre Hedrick
	16	*
	17	* Documentation:
25985edc	18	* Obsolete device documentation publicly available from via.com.tw
1da177e4 LT	19	* Current device documentation available under NDA only
	20	*/
	21
1da177e4	22
1da177e4 LT	23	#include <linux/module.h>
1da177e4 LT	24	#include <linux/kernel.h>
5a0e3ad6	25	#include <linux/slab.h>
1da177e4 LT	26	#include <linux/pci.h>
	27	#include <linux/init.h>
	28	#include <linux/ide.h>
bdab00b7 BZ	29	#include <linux/dmi.h>
bdab00b7 BZ	30
74a9d5f1	31	#ifdef CONFIG_PPC_CHRP
1da177e4 LT	32	#include <asm/processor.h>
	33	#endif
	34
ced3ec8a BZ	35	#define DRV_NAME "via82cxxx"
ced3ec8a BZ	36
1da177e4 LT	37	#define VIA_IDE_ENABLE 0x40
	38	#define VIA_IDE_CONFIG 0x41
	39	#define VIA_FIFO_CONFIG 0x43
	40	#define VIA_MISC_1 0x44
	41	#define VIA_MISC_2 0x45
	42	#define VIA_MISC_3 0x46
	43	#define VIA_DRIVE_TIMING 0x48
	44	#define VIA_8BIT_TIMING 0x4e
	45	#define VIA_ADDRESS_SETUP 0x4c
	46	#define VIA_UDMA_TIMING 0x50
	47
75b1d975 BZ	48	#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
	49	#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
	50	#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
	51	#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
	52	#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
	53	#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
a13e4865	54	#define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */
1da177e4	55
42036c85 BZ	56	enum {
	57	VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
	58	};
	59
1da177e4 LT	60	/*
	61	* VIA SouthBridge chips.
	62	*/
	63
	64	static struct via_isa_bridge {
	65	char *name;
	66	u16 id;
	67	u8 rev_min;
	68	u8 rev_max;
75b1d975 BZ	69	u8 udma_mask;
75b1d975 BZ	70	u8 flags;
1da177e4	71	} via_isa_bridges[] = {
a13e4865 BZ	72	{ "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
	73	{ "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
	74	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
5b6c82ea	75	{ "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	76	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	77	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
2a800b7b	78	{ "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	79	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	80	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	81	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	82	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	83	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	84	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
	85	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
	86	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
	87	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
	88	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
	89	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	90	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
	91	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	92	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	93	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO \| VIA_BAD_PREQ },
	94	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	95	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	96	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
	97	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK },
	98	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
5b6c82ea	99	{ "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
1da177e4 LT	100	{ NULL }
	101	};
	102
1da177e4	103	static unsigned int via_clock;
75b1d975	104	static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4	105
7462cbff DD	106	struct via82cxxx_dev
	107	{
	108	struct via_isa_bridge *via_config;
	109	unsigned int via_80w;
	110	};
	111
1da177e4 LT	112	/**
	113	* via_set_speed - write timing registers
	114	* @dev: PCI device
	115	* @dn: device
	116	* @timing: IDE timing data to use
	117	*
	118	* via_set_speed writes timing values to the chipset registers
	119	*/
	120
7462cbff	121	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	122	{
36501650	123	struct pci_dev *dev = to_pci_dev(hwif->dev);
ee77325b BZ	124	struct ide_host *host = pci_get_drvdata(dev);
ee77325b BZ	125	struct via82cxxx_dev *vdev = host->host_priv;
1da177e4 LT	126	u8 t;
1da177e4 LT	127
7462cbff	128	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4	129	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
d6cddd3c	130	t = (t & ~(3 << ((3 - dn) << 1))) \| ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
1da177e4 LT	131	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	132	}
	133
	134	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
d6cddd3c	135	((clamp_val(timing->act8b, 1, 16) - 1) << 4) \| (clamp_val(timing->rec8b, 1, 16) - 1));
1da177e4 LT	136
1da177e4 LT	137	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
d6cddd3c	138	((clamp_val(timing->active, 1, 16) - 1) << 4) \| (clamp_val(timing->recover, 1, 16) - 1));
1da177e4	139
75b1d975	140	switch (vdev->via_config->udma_mask) {
d6cddd3c HH	141	case ATA_UDMA2: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	142	case ATA_UDMA4: t = timing->udma ? (0xe8 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
	143	case ATA_UDMA5: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	144	case ATA_UDMA6: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
1da177e4 LT	145	}
1da177e4 LT	146
68d0a036 BZ	147	/* Set UDMA unless device is not UDMA capable */
	148	if (vdev->via_config->udma_mask) {
	149	u8 udma_etc;
	150
	151	pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc);
	152
	153	/* clear transfer mode bit */
	154	udma_etc &= ~0x20;
	155
	156	if (timing->udma) {
	157	/* preserve 80-wire cable detection bit */
	158	udma_etc &= 0x10;
	159	udma_etc \|= t;
	160	}
	161
	162	pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc);
	163	}
1da177e4 LT	164	}
	165
	166	/**
	167	* via_set_drive - configure transfer mode
8776168c	168	* @hwif: port
1da177e4	169	* @drive: Drive to set up
1da177e4	170	*
88b2b32b BZ	171	* via_set_drive() computes timing values configures the chipset to
88b2b32b BZ	172	* a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	173	*/
1da177e4 LT	174
8776168c	175	static void via_set_drive(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	176	{
7e59ea21	177	ide_drive_t *peer = ide_get_pair_dev(drive);
baf6722a	178	struct ide_host *host = dev_get_drvdata(hwif->dev);
ee77325b	179	struct via82cxxx_dev *vdev = host->host_priv;
1da177e4 LT	180	struct ide_timing t, p;
1da177e4 LT	181	unsigned int T, UT;
8776168c	182	const u8 speed = drive->dma_mode;
1da177e4	183
1da177e4 LT	184	T = 1000000000 / via_clock;
1da177e4 LT	185
75b1d975 BZ	186	switch (vdev->via_config->udma_mask) {
	187	case ATA_UDMA2: UT = T; break;
	188	case ATA_UDMA4: UT = T/2; break;
	189	case ATA_UDMA5: UT = T/3; break;
	190	case ATA_UDMA6: UT = T/4; break;
	191	default: UT = T;
1da177e4 LT	192	}
	193
	194	ide_timing_compute(drive, speed, &t, T, UT);
	195
7e59ea21	196	if (peer) {
f0e5f62d	197	ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
1da177e4 LT	198	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	199	}
	200
898ec223	201	via_set_speed(hwif, drive->dn, &t);
1da177e4 LT	202	}
	203
	204	/**
88b2b32b	205	* via_set_pio_mode - set host controller for PIO mode
e085b3ca	206	* @hwif: port
26bcb879	207	* @drive: drive
1da177e4 LT	208	*
	209	* A callback from the upper layers for PIO-only tuning.
	210	*/
	211
e085b3ca	212	static void via_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	213	{
8776168c BZ	214	drive->dma_mode = drive->pio_mode;
8776168c BZ	215	via_set_drive(hwif, drive);
1da177e4 LT	216	}
1da177e4 LT	217
7462cbff DD	218	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	219	{
	220	struct via_isa_bridge *via_config;
7462cbff	221
5b6c82ea BZ	222	for (via_config = via_isa_bridges;
5b6c82ea BZ	223	via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
652aa162	224	if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
7462cbff DD	225	!!(via_config->flags & VIA_BAD_ID),
	226	via_config->id, NULL))) {
	227
44c10138 AK	228	if ((*isa)->revision >= via_config->rev_min &&
44c10138 AK	229	(*isa)->revision <= via_config->rev_max)
7462cbff	230	break;
652aa162	231	pci_dev_put(*isa);
7462cbff DD	232	}
	233
	234	return via_config;
1da177e4 LT	235	}
1da177e4 LT	236
cd36beec BZ	237	/*
	238	* Check and handle 80-wire cable presence
	239	*/
feb22b7f	240	static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
cd36beec BZ	241	{
	242	int i;
	243
75b1d975 BZ	244	switch (vdev->via_config->udma_mask) {
75b1d975 BZ	245	case ATA_UDMA4:
cd36beec BZ	246	for (i = 24; i >= 0; i -= 8)
	247	if (((u >> (i & 16)) & 8) &&
	248	((u >> i) & 0x20) &&
	249	(((u >> i) & 7) < 2)) {
	250	/*
	251	* 2x PCI clock and
	252	* UDMA w/ < 3T/cycle
	253	*/
	254	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	255	}
	256	break;
	257
75b1d975	258	case ATA_UDMA5:
cd36beec BZ	259	for (i = 24; i >= 0; i -= 8)
	260	if (((u >> i) & 0x10) \|\|
	261	(((u >> i) & 0x20) &&
	262	(((u >> i) & 7) < 4))) {
	263	/* BIOS 80-wire bit or
	264	* UDMA w/ < 60ns/cycle
	265	*/
	266	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	267	}
	268	break;
	269
75b1d975	270	case ATA_UDMA6:
cd36beec BZ	271	for (i = 24; i >= 0; i -= 8)
	272	if (((u >> i) & 0x10) \|\|
	273	(((u >> i) & 0x20) &&
	274	(((u >> i) & 7) < 6))) {
	275	/* BIOS 80-wire bit or
	276	* UDMA w/ < 60ns/cycle
	277	*/
	278	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	279	}
	280	break;
	281	}
	282	}
	283
1da177e4 LT	284	/**
	285	* init_chipset_via82cxxx - initialization handler
	286	* @dev: PCI device
1da177e4 LT	287	*
	288	* The initialization callback. Here we determine the IDE chip type
	289	* and initialize its drive independent registers.
	290	*/
	291
2ed0ef54	292	static int init_chipset_via82cxxx(struct pci_dev *dev)
1da177e4	293	{
ee77325b BZ	294	struct ide_host *host = pci_get_drvdata(dev);
ee77325b BZ	295	struct via82cxxx_dev *vdev = host->host_priv;
37525beb	296	struct via_isa_bridge *via_config = vdev->via_config;
1da177e4	297	u8 t, v;
cd36beec BZ	298	u32 u;
cd36beec BZ	299
1da177e4	300	/*
cd36beec	301	* Detect cable and configure Clk66
1da177e4	302	*/
cd36beec BZ	303	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	304
	305	via_cable_detect(vdev, u);
1da177e4	306
75b1d975	307	if (via_config->udma_mask == ATA_UDMA4) {
7462cbff	308	/* Enable Clk66 */
7462cbff DD	309	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
7462cbff DD	310	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4	311	/* Would cause trouble on 596a and 686 */
1da177e4 LT	312	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	313	}
	314
	315	/*
	316	* Check whether interfaces are enabled.
	317	*/
	318
	319	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	320
	321	/*
	322	* Set up FIFO sizes and thresholds.
	323	*/
	324
	325	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	326
	327	/* Disable PREQ# till DDACK# */
	328	if (via_config->flags & VIA_BAD_PREQ) {
	329	/* Would crash on 586b rev 41 */
	330	t &= 0x7f;
	331	}
	332
	333	/* Fix FIFO split between channels */
	334	if (via_config->flags & VIA_SET_FIFO) {
	335	t &= (t & 0x9f);
	336	switch (v & 3) {
	337	case 2: t \|= 0x00; break; /* 16 on primary */
	338	case 1: t \|= 0x60; break; /* 16 on secondary */
	339	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	340	}
	341	}
	342
	343	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	344
1da177e4 LT	345	return 0;
	346	}
	347
bdab00b7 BZ	348	/*
	349	* Cable special cases
	350	*/
	351
1855256c	352	static const struct dmi_system_id cable_dmi_table[] = {
bdab00b7 BZ	353	{
	354	.ident = "Acer Ferrari 3400",
	355	.matches = {
	356	DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
	357	DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
	358	},
	359	},
	360	{ }
	361	};
	362
58e47bb1	363	static int via_cable_override(struct pci_dev *pdev)
bdab00b7 BZ	364	{
	365	/* Systems by DMI */
	366	if (dmi_check_system(cable_dmi_table))
	367	return 1;
58e47bb1 BZ	368
	369	/* Arima W730-K8/Targa Visionary 811/... */
	370	if (pdev->subsystem_vendor == 0x161F &&
	371	pdev->subsystem_device == 0x2032)
	372	return 1;
	373
bdab00b7 BZ	374	return 0;
	375	}
	376
f454cbe8	377	static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
bdab00b7	378	{
36501650	379	struct pci_dev *pdev = to_pci_dev(hwif->dev);
ee77325b BZ	380	struct ide_host *host = pci_get_drvdata(pdev);
ee77325b BZ	381	struct via82cxxx_dev *vdev = host->host_priv;
bdab00b7	382
58e47bb1	383	if (via_cable_override(pdev))
bdab00b7 BZ	384	return ATA_CBL_PATA40_SHORT;
bdab00b7 BZ	385
a13e4865 BZ	386	if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
	387	return ATA_CBL_SATA;
	388
bdab00b7 BZ	389	if ((vdev->via_80w >> hwif->channel) & 1)
	390	return ATA_CBL_PATA80;
	391	else
	392	return ATA_CBL_PATA40;
	393	}
	394
ac95beed BZ	395	static const struct ide_port_ops via_port_ops = {
	396	.set_pio_mode = via_set_pio_mode,
	397	.set_dma_mode = via_set_drive,
	398	.cable_detect = via82cxxx_cable_detect,
	399	};
1da177e4	400
fe31edc8	401	static const struct ide_port_info via82cxxx_chipset = {
ced3ec8a	402	.name = DRV_NAME,
6157332e	403	.init_chipset = init_chipset_via82cxxx,
6157332e	404	.enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
ac95beed	405	.port_ops = &via_port_ops,
6157332e	406	.host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \|
6157332e	407	IDE_HFLAG_POST_SET_MODE \|
5e71d9c5	408	IDE_HFLAG_IO_32BIT,
6157332e BZ	409	.pio_mask = ATA_PIO5,
	410	.swdma_mask = ATA_SWDMA2,
	411	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	412	};
1da177e4 LT	413
fe31edc8	414	static int via_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	415	{
23a1b2a7 AC	416	struct pci_dev *isa = NULL;
23a1b2a7 AC	417	struct via_isa_bridge *via_config;
ee77325b BZ	418	struct via82cxxx_dev *vdev;
ee77325b BZ	419	int rc;
6157332e	420	u8 idx = id->driver_data;
039788e1	421	struct ide_port_info d;
6157332e BZ	422
6157332e BZ	423	d = via82cxxx_chipset;
8acf28c0	424
23a1b2a7 AC	425	/*
	426	* Find the ISA bridge and check we know what it is.
	427	*/
	428	via_config = via_config_find(&isa);
8acf28c0	429
37525beb BZ	430	/*
	431	* Print the boot message.
	432	*/
ced3ec8a	433	printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
28cfd8af	434	pci_name(dev), via_config->name, isa->revision,
37525beb BZ	435	via_config->udma_mask ? "U" : "MW",
37525beb BZ	436	via_dma[via_config->udma_mask ?
28cfd8af	437	(fls(via_config->udma_mask) - 1) : 0]);
37525beb BZ	438
	439	pci_dev_put(isa);
	440
	441	/*
	442	* Determine system bus clock.
	443	*/
	444	via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
	445
	446	switch (via_clock) {
	447	case 33000: via_clock = 33333; break;
	448	case 37000: via_clock = 37500; break;
	449	case 41000: via_clock = 41666; break;
	450	}
	451
	452	if (via_clock < 20000 \|\| via_clock > 50000) {
ced3ec8a	453	printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
37525beb	454	"impossible (%d), using 33 MHz instead.\n", via_clock);
37525beb BZ	455	via_clock = 33333;
	456	}
	457
42036c85	458	if (idx == 1)
6157332e	459	d.enablebits[1].reg = d.enablebits[0].reg = 0;
42036c85 BZ	460	else
	461	d.host_flags \|= IDE_HFLAG_NO_AUTODMA;
	462
	463	if (idx == VIA_IDFLAG_SINGLE)
	464	d.host_flags \|= IDE_HFLAG_SINGLE;
6157332e BZ	465
	466	if ((via_config->flags & VIA_NO_UNMASK) == 0)
	467	d.host_flags \|= IDE_HFLAG_UNMASK_IRQS;
caea7602	468
6157332e	469	d.udma_mask = via_config->udma_mask;
8acf28c0	470
ee77325b BZ	471	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
ee77325b BZ	472	if (!vdev) {
ced3ec8a BZ	473	printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
ced3ec8a BZ	474	pci_name(dev));
ee77325b BZ	475	return -ENOMEM;
	476	}
	477
37525beb BZ	478	vdev->via_config = via_config;
37525beb BZ	479
ee77325b BZ	480	rc = ide_pci_init_one(dev, &d, vdev);
	481	if (rc)
	482	kfree(vdev);
	483
	484	return rc;
1da177e4 LT	485	}
1da177e4 LT	486
fe31edc8	487	static void via_remove(struct pci_dev *dev)
585f67e7 BZ	488	{
	489	struct ide_host *host = pci_get_drvdata(dev);
	490	struct via82cxxx_dev *vdev = host->host_priv;
	491
	492	ide_pci_remove(dev);
	493	kfree(vdev);
	494	}
	495
9cbcc5e3 BZ	496	static const struct pci_device_id via_pci_tbl[] = {
	497	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
	498	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
84f7e451	499	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
42036c85	500	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
9cbcc5e3	501	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
a354ae87	502	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 },
9cbcc5e3	503	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
1da177e4 LT	504	{ 0, },
	505	};
	506	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	507
a9ab09e2	508	static struct pci_driver via_pci_driver = {
1da177e4 LT	509	.name = "VIA_IDE",
	510	.id_table = via_pci_tbl,
	511	.probe = via_init_one,
fe31edc8	512	.remove = via_remove,
feb22b7f BZ	513	.suspend = ide_pci_suspend,
feb22b7f BZ	514	.resume = ide_pci_resume,
1da177e4 LT	515	};
1da177e4 LT	516
82ab1eec	517	static int __init via_ide_init(void)
1da177e4	518	{
a9ab09e2	519	return ide_pci_register_driver(&via_pci_driver);
1da177e4 LT	520	}
1da177e4 LT	521
585f67e7 BZ	522	static void __exit via_ide_exit(void)
585f67e7 BZ	523	{
a9ab09e2	524	pci_unregister_driver(&via_pci_driver);
585f67e7 BZ	525	}
585f67e7 BZ	526
1da177e4	527	module_init(via_ide_init);
585f67e7	528	module_exit(via_ide_exit);
1da177e4	529
42036c85	530	MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
1da177e4 LT	531	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
1da177e4 LT	532	MODULE_LICENSE("GPL");