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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * VIA IDE driver for Linux. Supported southbridges: |
3 | * | |
4 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
5 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
a7dec1e0 | 6 | * vt8235, vt8237, vt8237a |
1da177e4 LT |
7 | * |
8 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
42036c85 | 9 | * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
10 | * |
11 | * Based on the work of: | |
12 | * Michel Aubry | |
13 | * Jeff Garzik | |
14 | * Andre Hedrick | |
15 | * | |
16 | * Documentation: | |
17 | * Obsolete device documentation publically available from via.com.tw | |
18 | * Current device documentation available under NDA only | |
19 | */ | |
20 | ||
21 | /* | |
22 | * This program is free software; you can redistribute it and/or modify it | |
23 | * under the terms of the GNU General Public License version 2 as published by | |
24 | * the Free Software Foundation. | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/kernel.h> | |
1da177e4 LT |
29 | #include <linux/pci.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/ide.h> | |
bdab00b7 BZ |
32 | #include <linux/dmi.h> |
33 | ||
74a9d5f1 | 34 | #ifdef CONFIG_PPC_CHRP |
1da177e4 LT |
35 | #include <asm/processor.h> |
36 | #endif | |
37 | ||
ced3ec8a BZ |
38 | #define DRV_NAME "via82cxxx" |
39 | ||
1da177e4 LT |
40 | #define VIA_IDE_ENABLE 0x40 |
41 | #define VIA_IDE_CONFIG 0x41 | |
42 | #define VIA_FIFO_CONFIG 0x43 | |
43 | #define VIA_MISC_1 0x44 | |
44 | #define VIA_MISC_2 0x45 | |
45 | #define VIA_MISC_3 0x46 | |
46 | #define VIA_DRIVE_TIMING 0x48 | |
47 | #define VIA_8BIT_TIMING 0x4e | |
48 | #define VIA_ADDRESS_SETUP 0x4c | |
49 | #define VIA_UDMA_TIMING 0x50 | |
50 | ||
75b1d975 BZ |
51 | #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */ |
52 | #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */ | |
53 | #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */ | |
54 | #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ | |
55 | #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ | |
56 | #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ | |
1da177e4 | 57 | |
42036c85 BZ |
58 | enum { |
59 | VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */ | |
60 | }; | |
61 | ||
1da177e4 LT |
62 | /* |
63 | * VIA SouthBridge chips. | |
64 | */ | |
65 | ||
66 | static struct via_isa_bridge { | |
67 | char *name; | |
68 | u16 id; | |
69 | u8 rev_min; | |
70 | u8 rev_max; | |
75b1d975 BZ |
71 | u8 udma_mask; |
72 | u8 flags; | |
1da177e4 | 73 | } via_isa_bridges[] = { |
5993856e | 74 | { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
b311ec4a | 75 | { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
75b1d975 BZ |
76 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
77 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
78 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
79 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
80 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
81 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
82 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
83 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
84 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, | |
85 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, | |
86 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, | |
87 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, | |
88 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, | |
89 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
90 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, | |
91 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
92 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, | |
93 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, | |
94 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, | |
95 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, | |
96 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, | |
97 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, | |
98 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
1da177e4 LT |
99 | { NULL } |
100 | }; | |
101 | ||
1da177e4 | 102 | static unsigned int via_clock; |
75b1d975 | 103 | static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
1da177e4 | 104 | |
7462cbff DD |
105 | struct via82cxxx_dev |
106 | { | |
107 | struct via_isa_bridge *via_config; | |
108 | unsigned int via_80w; | |
109 | }; | |
110 | ||
1da177e4 LT |
111 | /** |
112 | * via_set_speed - write timing registers | |
113 | * @dev: PCI device | |
114 | * @dn: device | |
115 | * @timing: IDE timing data to use | |
116 | * | |
117 | * via_set_speed writes timing values to the chipset registers | |
118 | */ | |
119 | ||
7462cbff | 120 | static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) |
1da177e4 | 121 | { |
36501650 | 122 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
ee77325b BZ |
123 | struct ide_host *host = pci_get_drvdata(dev); |
124 | struct via82cxxx_dev *vdev = host->host_priv; | |
1da177e4 LT |
125 | u8 t; |
126 | ||
7462cbff | 127 | if (~vdev->via_config->flags & VIA_BAD_AST) { |
1da177e4 | 128 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); |
d6cddd3c | 129 | t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); |
1da177e4 LT |
130 | pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); |
131 | } | |
132 | ||
133 | pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), | |
d6cddd3c | 134 | ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); |
1da177e4 LT |
135 | |
136 | pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), | |
d6cddd3c | 137 | ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); |
1da177e4 | 138 | |
75b1d975 | 139 | switch (vdev->via_config->udma_mask) { |
d6cddd3c HH |
140 | case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; |
141 | case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; | |
142 | case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; | |
143 | case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; | |
75b1d975 | 144 | default: return; |
1da177e4 LT |
145 | } |
146 | ||
147 | pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); | |
148 | } | |
149 | ||
150 | /** | |
151 | * via_set_drive - configure transfer mode | |
152 | * @drive: Drive to set up | |
153 | * @speed: desired speed | |
154 | * | |
88b2b32b BZ |
155 | * via_set_drive() computes timing values configures the chipset to |
156 | * a desired transfer mode. It also can be called by upper layers. | |
1da177e4 LT |
157 | */ |
158 | ||
88b2b32b | 159 | static void via_set_drive(ide_drive_t *drive, const u8 speed) |
1da177e4 | 160 | { |
36501650 | 161 | ide_hwif_t *hwif = drive->hwif; |
7e59ea21 | 162 | ide_drive_t *peer = ide_get_pair_dev(drive); |
36501650 | 163 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
ee77325b BZ |
164 | struct ide_host *host = pci_get_drvdata(dev); |
165 | struct via82cxxx_dev *vdev = host->host_priv; | |
1da177e4 LT |
166 | struct ide_timing t, p; |
167 | unsigned int T, UT; | |
168 | ||
1da177e4 LT |
169 | T = 1000000000 / via_clock; |
170 | ||
75b1d975 BZ |
171 | switch (vdev->via_config->udma_mask) { |
172 | case ATA_UDMA2: UT = T; break; | |
173 | case ATA_UDMA4: UT = T/2; break; | |
174 | case ATA_UDMA5: UT = T/3; break; | |
175 | case ATA_UDMA6: UT = T/4; break; | |
176 | default: UT = T; | |
1da177e4 LT |
177 | } |
178 | ||
179 | ide_timing_compute(drive, speed, &t, T, UT); | |
180 | ||
7e59ea21 | 181 | if (peer) { |
1da177e4 LT |
182 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); |
183 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
184 | } | |
185 | ||
898ec223 | 186 | via_set_speed(hwif, drive->dn, &t); |
1da177e4 LT |
187 | } |
188 | ||
189 | /** | |
88b2b32b | 190 | * via_set_pio_mode - set host controller for PIO mode |
26bcb879 BZ |
191 | * @drive: drive |
192 | * @pio: PIO mode number | |
1da177e4 LT |
193 | * |
194 | * A callback from the upper layers for PIO-only tuning. | |
195 | */ | |
196 | ||
26bcb879 | 197 | static void via_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 198 | { |
26bcb879 | 199 | via_set_drive(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
200 | } |
201 | ||
7462cbff DD |
202 | static struct via_isa_bridge *via_config_find(struct pci_dev **isa) |
203 | { | |
204 | struct via_isa_bridge *via_config; | |
7462cbff DD |
205 | |
206 | for (via_config = via_isa_bridges; via_config->id; via_config++) | |
652aa162 | 207 | if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + |
7462cbff DD |
208 | !!(via_config->flags & VIA_BAD_ID), |
209 | via_config->id, NULL))) { | |
210 | ||
44c10138 AK |
211 | if ((*isa)->revision >= via_config->rev_min && |
212 | (*isa)->revision <= via_config->rev_max) | |
7462cbff | 213 | break; |
652aa162 | 214 | pci_dev_put(*isa); |
7462cbff DD |
215 | } |
216 | ||
217 | return via_config; | |
1da177e4 LT |
218 | } |
219 | ||
cd36beec BZ |
220 | /* |
221 | * Check and handle 80-wire cable presence | |
222 | */ | |
feb22b7f | 223 | static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u) |
cd36beec BZ |
224 | { |
225 | int i; | |
226 | ||
75b1d975 BZ |
227 | switch (vdev->via_config->udma_mask) { |
228 | case ATA_UDMA4: | |
cd36beec BZ |
229 | for (i = 24; i >= 0; i -= 8) |
230 | if (((u >> (i & 16)) & 8) && | |
231 | ((u >> i) & 0x20) && | |
232 | (((u >> i) & 7) < 2)) { | |
233 | /* | |
234 | * 2x PCI clock and | |
235 | * UDMA w/ < 3T/cycle | |
236 | */ | |
237 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
238 | } | |
239 | break; | |
240 | ||
75b1d975 | 241 | case ATA_UDMA5: |
cd36beec BZ |
242 | for (i = 24; i >= 0; i -= 8) |
243 | if (((u >> i) & 0x10) || | |
244 | (((u >> i) & 0x20) && | |
245 | (((u >> i) & 7) < 4))) { | |
246 | /* BIOS 80-wire bit or | |
247 | * UDMA w/ < 60ns/cycle | |
248 | */ | |
249 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
250 | } | |
251 | break; | |
252 | ||
75b1d975 | 253 | case ATA_UDMA6: |
cd36beec BZ |
254 | for (i = 24; i >= 0; i -= 8) |
255 | if (((u >> i) & 0x10) || | |
256 | (((u >> i) & 0x20) && | |
257 | (((u >> i) & 7) < 6))) { | |
258 | /* BIOS 80-wire bit or | |
259 | * UDMA w/ < 60ns/cycle | |
260 | */ | |
261 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
262 | } | |
263 | break; | |
264 | } | |
265 | } | |
266 | ||
1da177e4 LT |
267 | /** |
268 | * init_chipset_via82cxxx - initialization handler | |
269 | * @dev: PCI device | |
1da177e4 LT |
270 | * |
271 | * The initialization callback. Here we determine the IDE chip type | |
272 | * and initialize its drive independent registers. | |
273 | */ | |
274 | ||
2ed0ef54 | 275 | static int init_chipset_via82cxxx(struct pci_dev *dev) |
1da177e4 | 276 | { |
ee77325b BZ |
277 | struct ide_host *host = pci_get_drvdata(dev); |
278 | struct via82cxxx_dev *vdev = host->host_priv; | |
37525beb | 279 | struct via_isa_bridge *via_config = vdev->via_config; |
1da177e4 | 280 | u8 t, v; |
cd36beec BZ |
281 | u32 u; |
282 | ||
1da177e4 | 283 | /* |
cd36beec | 284 | * Detect cable and configure Clk66 |
1da177e4 | 285 | */ |
cd36beec BZ |
286 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); |
287 | ||
288 | via_cable_detect(vdev, u); | |
1da177e4 | 289 | |
75b1d975 | 290 | if (via_config->udma_mask == ATA_UDMA4) { |
7462cbff | 291 | /* Enable Clk66 */ |
7462cbff DD |
292 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); |
293 | } else if (via_config->flags & VIA_BAD_CLK66) { | |
1da177e4 | 294 | /* Would cause trouble on 596a and 686 */ |
1da177e4 LT |
295 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); |
296 | } | |
297 | ||
298 | /* | |
299 | * Check whether interfaces are enabled. | |
300 | */ | |
301 | ||
302 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); | |
303 | ||
304 | /* | |
305 | * Set up FIFO sizes and thresholds. | |
306 | */ | |
307 | ||
308 | pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); | |
309 | ||
310 | /* Disable PREQ# till DDACK# */ | |
311 | if (via_config->flags & VIA_BAD_PREQ) { | |
312 | /* Would crash on 586b rev 41 */ | |
313 | t &= 0x7f; | |
314 | } | |
315 | ||
316 | /* Fix FIFO split between channels */ | |
317 | if (via_config->flags & VIA_SET_FIFO) { | |
318 | t &= (t & 0x9f); | |
319 | switch (v & 3) { | |
320 | case 2: t |= 0x00; break; /* 16 on primary */ | |
321 | case 1: t |= 0x60; break; /* 16 on secondary */ | |
322 | case 3: t |= 0x20; break; /* 8 pri 8 sec */ | |
323 | } | |
324 | } | |
325 | ||
326 | pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); | |
327 | ||
1da177e4 LT |
328 | return 0; |
329 | } | |
330 | ||
bdab00b7 BZ |
331 | /* |
332 | * Cable special cases | |
333 | */ | |
334 | ||
1855256c | 335 | static const struct dmi_system_id cable_dmi_table[] = { |
bdab00b7 BZ |
336 | { |
337 | .ident = "Acer Ferrari 3400", | |
338 | .matches = { | |
339 | DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), | |
340 | DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), | |
341 | }, | |
342 | }, | |
343 | { } | |
344 | }; | |
345 | ||
58e47bb1 | 346 | static int via_cable_override(struct pci_dev *pdev) |
bdab00b7 BZ |
347 | { |
348 | /* Systems by DMI */ | |
349 | if (dmi_check_system(cable_dmi_table)) | |
350 | return 1; | |
58e47bb1 BZ |
351 | |
352 | /* Arima W730-K8/Targa Visionary 811/... */ | |
353 | if (pdev->subsystem_vendor == 0x161F && | |
354 | pdev->subsystem_device == 0x2032) | |
355 | return 1; | |
356 | ||
bdab00b7 BZ |
357 | return 0; |
358 | } | |
359 | ||
f454cbe8 | 360 | static u8 via82cxxx_cable_detect(ide_hwif_t *hwif) |
bdab00b7 | 361 | { |
36501650 | 362 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
ee77325b BZ |
363 | struct ide_host *host = pci_get_drvdata(pdev); |
364 | struct via82cxxx_dev *vdev = host->host_priv; | |
bdab00b7 | 365 | |
58e47bb1 | 366 | if (via_cable_override(pdev)) |
bdab00b7 BZ |
367 | return ATA_CBL_PATA40_SHORT; |
368 | ||
369 | if ((vdev->via_80w >> hwif->channel) & 1) | |
370 | return ATA_CBL_PATA80; | |
371 | else | |
372 | return ATA_CBL_PATA40; | |
373 | } | |
374 | ||
ac95beed BZ |
375 | static const struct ide_port_ops via_port_ops = { |
376 | .set_pio_mode = via_set_pio_mode, | |
377 | .set_dma_mode = via_set_drive, | |
378 | .cable_detect = via82cxxx_cable_detect, | |
379 | }; | |
1da177e4 | 380 | |
85620436 | 381 | static const struct ide_port_info via82cxxx_chipset __devinitdata = { |
ced3ec8a | 382 | .name = DRV_NAME, |
6157332e | 383 | .init_chipset = init_chipset_via82cxxx, |
6157332e | 384 | .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, |
ac95beed | 385 | .port_ops = &via_port_ops, |
6157332e | 386 | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | |
6157332e | 387 | IDE_HFLAG_POST_SET_MODE | |
5e71d9c5 | 388 | IDE_HFLAG_IO_32BIT, |
6157332e BZ |
389 | .pio_mask = ATA_PIO5, |
390 | .swdma_mask = ATA_SWDMA2, | |
391 | .mwdma_mask = ATA_MWDMA2, | |
1da177e4 LT |
392 | }; |
393 | ||
394 | static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
395 | { | |
23a1b2a7 AC |
396 | struct pci_dev *isa = NULL; |
397 | struct via_isa_bridge *via_config; | |
ee77325b BZ |
398 | struct via82cxxx_dev *vdev; |
399 | int rc; | |
6157332e | 400 | u8 idx = id->driver_data; |
039788e1 | 401 | struct ide_port_info d; |
6157332e BZ |
402 | |
403 | d = via82cxxx_chipset; | |
8acf28c0 | 404 | |
23a1b2a7 AC |
405 | /* |
406 | * Find the ISA bridge and check we know what it is. | |
407 | */ | |
408 | via_config = via_config_find(&isa); | |
23a1b2a7 | 409 | if (!via_config->id) { |
ced3ec8a | 410 | printk(KERN_WARNING DRV_NAME " %s: unknown chipset, skipping\n", |
28cfd8af | 411 | pci_name(dev)); |
23a1b2a7 AC |
412 | return -ENODEV; |
413 | } | |
8acf28c0 | 414 | |
37525beb BZ |
415 | /* |
416 | * Print the boot message. | |
417 | */ | |
ced3ec8a | 418 | printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n", |
28cfd8af | 419 | pci_name(dev), via_config->name, isa->revision, |
37525beb BZ |
420 | via_config->udma_mask ? "U" : "MW", |
421 | via_dma[via_config->udma_mask ? | |
28cfd8af | 422 | (fls(via_config->udma_mask) - 1) : 0]); |
37525beb BZ |
423 | |
424 | pci_dev_put(isa); | |
425 | ||
426 | /* | |
427 | * Determine system bus clock. | |
428 | */ | |
429 | via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000; | |
430 | ||
431 | switch (via_clock) { | |
432 | case 33000: via_clock = 33333; break; | |
433 | case 37000: via_clock = 37500; break; | |
434 | case 41000: via_clock = 41666; break; | |
435 | } | |
436 | ||
437 | if (via_clock < 20000 || via_clock > 50000) { | |
ced3ec8a | 438 | printk(KERN_WARNING DRV_NAME ": User given PCI clock speed " |
37525beb | 439 | "impossible (%d), using 33 MHz instead.\n", via_clock); |
37525beb BZ |
440 | via_clock = 33333; |
441 | } | |
442 | ||
42036c85 | 443 | if (idx == 1) |
6157332e | 444 | d.enablebits[1].reg = d.enablebits[0].reg = 0; |
42036c85 BZ |
445 | else |
446 | d.host_flags |= IDE_HFLAG_NO_AUTODMA; | |
447 | ||
448 | if (idx == VIA_IDFLAG_SINGLE) | |
449 | d.host_flags |= IDE_HFLAG_SINGLE; | |
6157332e BZ |
450 | |
451 | if ((via_config->flags & VIA_NO_UNMASK) == 0) | |
452 | d.host_flags |= IDE_HFLAG_UNMASK_IRQS; | |
caea7602 | 453 | |
6157332e | 454 | d.udma_mask = via_config->udma_mask; |
8acf28c0 | 455 | |
ee77325b BZ |
456 | vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); |
457 | if (!vdev) { | |
ced3ec8a BZ |
458 | printk(KERN_ERR DRV_NAME " %s: out of memory :(\n", |
459 | pci_name(dev)); | |
ee77325b BZ |
460 | return -ENOMEM; |
461 | } | |
462 | ||
37525beb BZ |
463 | vdev->via_config = via_config; |
464 | ||
ee77325b BZ |
465 | rc = ide_pci_init_one(dev, &d, vdev); |
466 | if (rc) | |
467 | kfree(vdev); | |
468 | ||
469 | return rc; | |
1da177e4 LT |
470 | } |
471 | ||
585f67e7 BZ |
472 | static void __devexit via_remove(struct pci_dev *dev) |
473 | { | |
474 | struct ide_host *host = pci_get_drvdata(dev); | |
475 | struct via82cxxx_dev *vdev = host->host_priv; | |
476 | ||
477 | ide_pci_remove(dev); | |
478 | kfree(vdev); | |
479 | } | |
480 | ||
9cbcc5e3 BZ |
481 | static const struct pci_device_id via_pci_tbl[] = { |
482 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 }, | |
483 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 }, | |
84f7e451 | 484 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 }, |
42036c85 | 485 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE }, |
9cbcc5e3 BZ |
486 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 }, |
487 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 }, | |
1da177e4 LT |
488 | { 0, }, |
489 | }; | |
490 | MODULE_DEVICE_TABLE(pci, via_pci_tbl); | |
491 | ||
a9ab09e2 | 492 | static struct pci_driver via_pci_driver = { |
1da177e4 LT |
493 | .name = "VIA_IDE", |
494 | .id_table = via_pci_tbl, | |
495 | .probe = via_init_one, | |
a69999e2 | 496 | .remove = __devexit_p(via_remove), |
feb22b7f BZ |
497 | .suspend = ide_pci_suspend, |
498 | .resume = ide_pci_resume, | |
1da177e4 LT |
499 | }; |
500 | ||
82ab1eec | 501 | static int __init via_ide_init(void) |
1da177e4 | 502 | { |
a9ab09e2 | 503 | return ide_pci_register_driver(&via_pci_driver); |
1da177e4 LT |
504 | } |
505 | ||
585f67e7 BZ |
506 | static void __exit via_ide_exit(void) |
507 | { | |
a9ab09e2 | 508 | pci_unregister_driver(&via_pci_driver); |
585f67e7 BZ |
509 | } |
510 | ||
1da177e4 | 511 | module_init(via_ide_init); |
585f67e7 | 512 | module_exit(via_ide_exit); |
1da177e4 | 513 | |
42036c85 | 514 | MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick"); |
1da177e4 LT |
515 | MODULE_DESCRIPTION("PCI driver module for VIA IDE"); |
516 | MODULE_LICENSE("GPL"); |