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27471fdb AH |
1 | /* |
2 | * (C) Copyright 2008 Intel Corporation | |
3 | * Authors: | |
4 | * Andy Henroid <andrew.d.henroid@intel.com> | |
5 | * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Save DIMM power on Intel 7300-based platforms when all CPUs/cores | |
10 | * are idle, using the DIMM thermal throttling capability. | |
11 | * | |
12 | * This driver depends on the Intel integrated DMA controller (I/O AT). | |
13 | * If the driver for I/O AT (drivers/dma/ioatdma*) is also enabled, | |
14 | * this driver should work cooperatively. | |
15 | */ | |
16 | ||
17 | /* #define DEBUG */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/notifier.h> | |
23 | #include <linux/cpumask.h> | |
24 | #include <linux/ktime.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/debugfs.h> | |
27 | #include <linux/stop_machine.h> | |
3ad0b02e | 28 | #include <linux/i7300_idle.h> |
27471fdb AH |
29 | |
30 | #include <asm/idle.h> | |
31 | ||
32 | #include "../dma/ioatdma_hw.h" | |
33 | #include "../dma/ioatdma_registers.h" | |
34 | ||
35 | #define I7300_IDLE_DRIVER_VERSION "1.55" | |
36 | #define I7300_PRINT "i7300_idle:" | |
37 | ||
33093e18 VP |
38 | #define MAX_STOP_RETRIES 10 |
39 | ||
27471fdb AH |
40 | static int debug; |
41 | module_param_named(debug, debug, uint, 0644); | |
42 | MODULE_PARM_DESC(debug, "Enable debug printks in this driver"); | |
43 | ||
44 | #define dprintk(fmt, arg...) \ | |
45 | do { if (debug) printk(KERN_INFO I7300_PRINT fmt, ##arg); } while (0) | |
46 | ||
47 | /* | |
48 | * Value to set THRTLOW to when initiating throttling | |
49 | * 0 = No throttling | |
50 | * 1 = Throttle when > 4 activations per eval window (Maximum throttling) | |
51 | * 2 = Throttle when > 8 activations | |
33093e18 | 52 | * 168 = Throttle when > 672 activations (Minimum throttling) |
27471fdb | 53 | */ |
33093e18 VP |
54 | #define MAX_THROTTLE_LOW_LIMIT 168 |
55 | static uint throttle_low_limit = 1; | |
56 | module_param_named(throttle_low_limit, throttle_low_limit, uint, 0644); | |
57 | MODULE_PARM_DESC(throttle_low_limit, | |
27471fdb AH |
58 | "Value for THRTLOWLM activation field " |
59 | "(0 = disable throttle, 1 = Max throttle, 168 = Min throttle)"); | |
60 | ||
61 | /* | |
62 | * simple invocation and duration statistics | |
63 | */ | |
64 | static unsigned long total_starts; | |
65 | static unsigned long total_us; | |
66 | ||
67 | #ifdef DEBUG | |
68 | static unsigned long past_skip; | |
69 | #endif | |
70 | ||
71 | static struct pci_dev *fbd_dev; | |
72 | ||
73 | static spinlock_t i7300_idle_lock; | |
74 | static int i7300_idle_active; | |
75 | ||
76 | static u8 i7300_idle_thrtctl_saved; | |
77 | static u8 i7300_idle_thrtlow_saved; | |
78 | static u32 i7300_idle_mc_saved; | |
79 | ||
80 | static cpumask_t idle_cpumask; | |
81 | static ktime_t start_ktime; | |
82 | static unsigned long avg_idle_us; | |
83 | ||
84 | static struct dentry *debugfs_dir; | |
85 | ||
86 | /* Begin: I/O AT Helper routines */ | |
87 | ||
88 | #define IOAT_CHANBASE(ioat_ctl, chan) (ioat_ctl + 0x80 + 0x80 * chan) | |
89 | /* Snoop control (disable snoops when coherency is not important) */ | |
90 | #define IOAT_DESC_SADDR_SNP_CTL (1UL << 1) | |
91 | #define IOAT_DESC_DADDR_SNP_CTL (1UL << 2) | |
92 | ||
93 | static struct pci_dev *ioat_dev; | |
94 | static struct ioat_dma_descriptor *ioat_desc; /* I/O AT desc & data (1 page) */ | |
95 | static unsigned long ioat_desc_phys; | |
96 | static u8 *ioat_iomap; /* I/O AT memory-mapped control regs (aka CB_BAR) */ | |
97 | static u8 *ioat_chanbase; | |
98 | ||
99 | /* Start I/O AT memory copy */ | |
100 | static int i7300_idle_ioat_start(void) | |
101 | { | |
102 | u32 err; | |
103 | /* Clear error (due to circular descriptor pointer) */ | |
104 | err = readl(ioat_chanbase + IOAT_CHANERR_OFFSET); | |
105 | if (err) | |
106 | writel(err, ioat_chanbase + IOAT_CHANERR_OFFSET); | |
107 | ||
108 | writeb(IOAT_CHANCMD_START, ioat_chanbase + IOAT1_CHANCMD_OFFSET); | |
109 | return 0; | |
110 | } | |
111 | ||
112 | /* Stop I/O AT memory copy */ | |
113 | static void i7300_idle_ioat_stop(void) | |
114 | { | |
115 | int i; | |
33093e18 | 116 | u64 sts; |
27471fdb | 117 | |
33093e18 | 118 | for (i = 0; i < MAX_STOP_RETRIES; i++) { |
27471fdb AH |
119 | writeb(IOAT_CHANCMD_RESET, |
120 | ioat_chanbase + IOAT1_CHANCMD_OFFSET); | |
121 | ||
122 | udelay(10); | |
123 | ||
124 | sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) & | |
125 | IOAT_CHANSTS_DMA_TRANSFER_STATUS; | |
126 | ||
127 | if (sts != IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE) | |
128 | break; | |
129 | ||
130 | } | |
131 | ||
33093e18 VP |
132 | if (i == MAX_STOP_RETRIES) { |
133 | dprintk("failed to stop I/O AT after %d retries\n", | |
134 | MAX_STOP_RETRIES); | |
135 | } | |
27471fdb AH |
136 | } |
137 | ||
138 | /* Test I/O AT by copying 1024 byte from 2k to 1k */ | |
139 | static int __init i7300_idle_ioat_selftest(u8 *ctl, | |
140 | struct ioat_dma_descriptor *desc, unsigned long desc_phys) | |
141 | { | |
142 | u64 chan_sts; | |
143 | ||
144 | memset(desc, 0, 2048); | |
145 | memset((u8 *) desc + 2048, 0xab, 1024); | |
146 | ||
147 | desc[0].size = 1024; | |
148 | desc[0].ctl = 0; | |
149 | desc[0].src_addr = desc_phys + 2048; | |
150 | desc[0].dst_addr = desc_phys + 1024; | |
151 | desc[0].next = 0; | |
152 | ||
153 | writeb(IOAT_CHANCMD_RESET, ioat_chanbase + IOAT1_CHANCMD_OFFSET); | |
154 | writeb(IOAT_CHANCMD_START, ioat_chanbase + IOAT1_CHANCMD_OFFSET); | |
155 | ||
156 | udelay(1000); | |
157 | ||
158 | chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) & | |
159 | IOAT_CHANSTS_DMA_TRANSFER_STATUS; | |
160 | ||
161 | if (chan_sts != IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE) { | |
162 | /* Not complete, reset the channel */ | |
163 | writeb(IOAT_CHANCMD_RESET, | |
164 | ioat_chanbase + IOAT1_CHANCMD_OFFSET); | |
165 | return -1; | |
166 | } | |
167 | ||
168 | if (*(u32 *) ((u8 *) desc + 3068) != 0xabababab || | |
169 | *(u32 *) ((u8 *) desc + 2044) != 0xabababab) { | |
170 | dprintk("Data values src 0x%x, dest 0x%x, memset 0x%x\n", | |
171 | *(u32 *) ((u8 *) desc + 2048), | |
172 | *(u32 *) ((u8 *) desc + 1024), | |
173 | *(u32 *) ((u8 *) desc + 3072)); | |
174 | return -1; | |
175 | } | |
176 | return 0; | |
177 | } | |
178 | ||
179 | static struct device dummy_dma_dev = { | |
180 | .bus_id = "fallback device", | |
181 | .coherent_dma_mask = DMA_64BIT_MASK, | |
182 | .dma_mask = &dummy_dma_dev.coherent_dma_mask, | |
183 | }; | |
184 | ||
185 | /* Setup and initialize I/O AT */ | |
186 | /* This driver needs I/O AT as the throttling takes effect only when there is | |
187 | * some memory activity. We use I/O AT to set up a dummy copy, while all CPUs | |
188 | * go idle and memory is throttled. | |
189 | */ | |
190 | static int __init i7300_idle_ioat_init(void) | |
191 | { | |
192 | u8 ver, chan_count, ioat_chan; | |
193 | u16 chan_ctl; | |
194 | ||
195 | ioat_iomap = (u8 *) ioremap_nocache(pci_resource_start(ioat_dev, 0), | |
196 | pci_resource_len(ioat_dev, 0)); | |
197 | ||
198 | if (!ioat_iomap) { | |
199 | printk(KERN_ERR I7300_PRINT "failed to map I/O AT registers\n"); | |
200 | goto err_ret; | |
201 | } | |
202 | ||
203 | ver = readb(ioat_iomap + IOAT_VER_OFFSET); | |
204 | if (ver != IOAT_VER_1_2) { | |
205 | printk(KERN_ERR I7300_PRINT "unknown I/O AT version (%u.%u)\n", | |
206 | ver >> 4, ver & 0xf); | |
207 | goto err_unmap; | |
208 | } | |
209 | ||
210 | chan_count = readb(ioat_iomap + IOAT_CHANCNT_OFFSET); | |
211 | if (!chan_count) { | |
212 | printk(KERN_ERR I7300_PRINT "unexpected # of I/O AT channels " | |
213 | "(%u)\n", | |
214 | chan_count); | |
215 | goto err_unmap; | |
216 | } | |
217 | ||
218 | ioat_chan = chan_count - 1; | |
219 | ioat_chanbase = IOAT_CHANBASE(ioat_iomap, ioat_chan); | |
220 | ||
221 | chan_ctl = readw(ioat_chanbase + IOAT_CHANCTRL_OFFSET); | |
222 | if (chan_ctl & IOAT_CHANCTRL_CHANNEL_IN_USE) { | |
223 | printk(KERN_ERR I7300_PRINT "channel %d in use\n", ioat_chan); | |
224 | goto err_unmap; | |
225 | } | |
226 | ||
227 | writew(IOAT_CHANCTRL_CHANNEL_IN_USE, | |
228 | ioat_chanbase + IOAT_CHANCTRL_OFFSET); | |
229 | ||
230 | ioat_desc = (struct ioat_dma_descriptor *)dma_alloc_coherent( | |
231 | &dummy_dma_dev, 4096, | |
232 | (dma_addr_t *)&ioat_desc_phys, GFP_KERNEL); | |
233 | if (!ioat_desc) { | |
234 | printk(KERN_ERR I7300_PRINT "failed to allocate I/O AT desc\n"); | |
235 | goto err_mark_unused; | |
236 | } | |
237 | ||
238 | writel(ioat_desc_phys & 0xffffffffUL, | |
239 | ioat_chanbase + IOAT1_CHAINADDR_OFFSET_LOW); | |
240 | writel(ioat_desc_phys >> 32, | |
241 | ioat_chanbase + IOAT1_CHAINADDR_OFFSET_HIGH); | |
242 | ||
243 | if (i7300_idle_ioat_selftest(ioat_iomap, ioat_desc, ioat_desc_phys)) { | |
244 | printk(KERN_ERR I7300_PRINT "I/O AT self-test failed\n"); | |
245 | goto err_free; | |
246 | } | |
247 | ||
248 | /* Setup circular I/O AT descriptor chain */ | |
249 | ioat_desc[0].ctl = IOAT_DESC_SADDR_SNP_CTL | IOAT_DESC_DADDR_SNP_CTL; | |
250 | ioat_desc[0].src_addr = ioat_desc_phys + 2048; | |
251 | ioat_desc[0].dst_addr = ioat_desc_phys + 3072; | |
252 | ioat_desc[0].size = 128; | |
253 | ioat_desc[0].next = ioat_desc_phys + sizeof(struct ioat_dma_descriptor); | |
254 | ||
255 | ioat_desc[1].ctl = ioat_desc[0].ctl; | |
256 | ioat_desc[1].src_addr = ioat_desc[0].src_addr; | |
257 | ioat_desc[1].dst_addr = ioat_desc[0].dst_addr; | |
258 | ioat_desc[1].size = ioat_desc[0].size; | |
259 | ioat_desc[1].next = ioat_desc_phys; | |
260 | ||
261 | return 0; | |
262 | ||
263 | err_free: | |
264 | dma_free_coherent(&dummy_dma_dev, 4096, (void *)ioat_desc, 0); | |
265 | err_mark_unused: | |
266 | writew(0, ioat_chanbase + IOAT_CHANCTRL_OFFSET); | |
267 | err_unmap: | |
268 | iounmap(ioat_iomap); | |
269 | err_ret: | |
270 | return -ENODEV; | |
271 | } | |
272 | ||
273 | /* Cleanup I/O AT */ | |
274 | static void __exit i7300_idle_ioat_exit(void) | |
275 | { | |
276 | int i; | |
277 | u64 chan_sts; | |
278 | ||
279 | i7300_idle_ioat_stop(); | |
280 | ||
281 | /* Wait for a while for the channel to halt before releasing */ | |
33093e18 | 282 | for (i = 0; i < MAX_STOP_RETRIES; i++) { |
27471fdb AH |
283 | writeb(IOAT_CHANCMD_RESET, |
284 | ioat_chanbase + IOAT1_CHANCMD_OFFSET); | |
285 | ||
286 | chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) & | |
287 | IOAT_CHANSTS_DMA_TRANSFER_STATUS; | |
288 | ||
289 | if (chan_sts != IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE) { | |
290 | writew(0, ioat_chanbase + IOAT_CHANCTRL_OFFSET); | |
291 | break; | |
292 | } | |
293 | udelay(1000); | |
294 | } | |
295 | ||
296 | chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) & | |
297 | IOAT_CHANSTS_DMA_TRANSFER_STATUS; | |
298 | ||
299 | /* | |
300 | * We tried to reset multiple times. If IO A/T channel is still active | |
301 | * flag an error and return without cleanup. Memory leak is better | |
302 | * than random corruption in that extreme error situation. | |
303 | */ | |
304 | if (chan_sts == IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE) { | |
305 | printk(KERN_ERR I7300_PRINT "Unable to stop IO A/T channels." | |
306 | " Not freeing resources\n"); | |
307 | return; | |
308 | } | |
309 | ||
310 | dma_free_coherent(&dummy_dma_dev, 4096, (void *)ioat_desc, 0); | |
311 | iounmap(ioat_iomap); | |
312 | } | |
313 | ||
314 | /* End: I/O AT Helper routines */ | |
315 | ||
316 | #define DIMM_THRTLOW 0x64 | |
317 | #define DIMM_THRTCTL 0x67 | |
318 | #define DIMM_THRTCTL_THRMHUNT (1UL << 0) | |
319 | #define DIMM_MC 0x40 | |
320 | #define DIMM_GTW_MODE (1UL << 17) | |
321 | #define DIMM_GBLACT 0x60 | |
322 | ||
323 | /* | |
324 | * Keep track of an exponential-decaying average of recent idle durations. | |
325 | * The latest duration gets DURATION_WEIGHT_PCT percentage weight | |
326 | * in this average, with the old average getting the remaining weight. | |
327 | * | |
328 | * High weights emphasize recent history, low weights include long history. | |
329 | */ | |
330 | #define DURATION_WEIGHT_PCT 55 | |
331 | ||
332 | /* | |
333 | * When the decaying average of recent durations or the predicted duration | |
334 | * of the next timer interrupt is shorter than duration_threshold, the | |
335 | * driver will decline to throttle. | |
336 | */ | |
337 | #define DURATION_THRESHOLD_US 100 | |
338 | ||
339 | ||
340 | /* Store DIMM thermal throttle configuration */ | |
341 | static int i7300_idle_thrt_save(void) | |
342 | { | |
343 | u32 new_mc_val; | |
344 | u8 gblactlm; | |
345 | ||
346 | pci_read_config_byte(fbd_dev, DIMM_THRTCTL, &i7300_idle_thrtctl_saved); | |
347 | pci_read_config_byte(fbd_dev, DIMM_THRTLOW, &i7300_idle_thrtlow_saved); | |
348 | pci_read_config_dword(fbd_dev, DIMM_MC, &i7300_idle_mc_saved); | |
349 | /* | |
350 | * Make sure we have Global Throttling Window Mode set to have a | |
351 | * "short" window. This (mostly) works around an issue where | |
352 | * throttling persists until the end of the global throttling window | |
353 | * size. On the tested system, this was resulting in a maximum of | |
354 | * 64 ms to exit throttling (average 32 ms). The actual numbers | |
355 | * depends on system frequencies. Setting the short window reduces | |
356 | * this by a factor of 4096. | |
357 | * | |
358 | * We will only do this only if the system is set for | |
359 | * unlimited-activations while in open-loop throttling (i.e., when | |
360 | * Global Activation Throttle Limit is zero). | |
361 | */ | |
362 | pci_read_config_byte(fbd_dev, DIMM_GBLACT, &gblactlm); | |
363 | dprintk("thrtctl_saved = 0x%02x, thrtlow_saved = 0x%02x\n", | |
364 | i7300_idle_thrtctl_saved, | |
365 | i7300_idle_thrtlow_saved); | |
366 | dprintk("mc_saved = 0x%08x, gblactlm = 0x%02x\n", | |
367 | i7300_idle_mc_saved, | |
368 | gblactlm); | |
369 | if (gblactlm == 0) { | |
370 | new_mc_val = i7300_idle_mc_saved | DIMM_GTW_MODE; | |
371 | pci_write_config_dword(fbd_dev, DIMM_MC, new_mc_val); | |
372 | return 0; | |
373 | } else { | |
374 | dprintk("could not set GTW_MODE = 1 (OLTT enabled)\n"); | |
375 | return -ENODEV; | |
376 | } | |
377 | } | |
378 | ||
379 | /* Restore DIMM thermal throttle configuration */ | |
380 | static void i7300_idle_thrt_restore(void) | |
381 | { | |
382 | pci_write_config_dword(fbd_dev, DIMM_MC, i7300_idle_mc_saved); | |
383 | pci_write_config_byte(fbd_dev, DIMM_THRTLOW, i7300_idle_thrtlow_saved); | |
384 | pci_write_config_byte(fbd_dev, DIMM_THRTCTL, i7300_idle_thrtctl_saved); | |
385 | } | |
386 | ||
387 | /* Enable DIMM thermal throttling */ | |
388 | static void i7300_idle_start(void) | |
389 | { | |
390 | u8 new_ctl; | |
391 | u8 limit; | |
392 | ||
393 | new_ctl = i7300_idle_thrtctl_saved & ~DIMM_THRTCTL_THRMHUNT; | |
394 | pci_write_config_byte(fbd_dev, DIMM_THRTCTL, new_ctl); | |
395 | ||
33093e18 VP |
396 | limit = throttle_low_limit; |
397 | if (unlikely(limit > MAX_THROTTLE_LOW_LIMIT)) | |
398 | limit = MAX_THROTTLE_LOW_LIMIT; | |
27471fdb AH |
399 | |
400 | pci_write_config_byte(fbd_dev, DIMM_THRTLOW, limit); | |
401 | ||
402 | new_ctl = i7300_idle_thrtctl_saved | DIMM_THRTCTL_THRMHUNT; | |
403 | pci_write_config_byte(fbd_dev, DIMM_THRTCTL, new_ctl); | |
404 | } | |
405 | ||
406 | /* Disable DIMM thermal throttling */ | |
407 | static void i7300_idle_stop(void) | |
408 | { | |
409 | u8 new_ctl; | |
410 | u8 got_ctl; | |
411 | ||
412 | new_ctl = i7300_idle_thrtctl_saved & ~DIMM_THRTCTL_THRMHUNT; | |
413 | pci_write_config_byte(fbd_dev, DIMM_THRTCTL, new_ctl); | |
414 | ||
415 | pci_write_config_byte(fbd_dev, DIMM_THRTLOW, i7300_idle_thrtlow_saved); | |
416 | pci_write_config_byte(fbd_dev, DIMM_THRTCTL, i7300_idle_thrtctl_saved); | |
417 | pci_read_config_byte(fbd_dev, DIMM_THRTCTL, &got_ctl); | |
418 | WARN_ON_ONCE(got_ctl != i7300_idle_thrtctl_saved); | |
419 | } | |
420 | ||
421 | ||
422 | /* | |
423 | * i7300_avg_duration_check() | |
424 | * return 0 if the decaying average of recent idle durations is | |
425 | * more than DURATION_THRESHOLD_US | |
426 | */ | |
427 | static int i7300_avg_duration_check(void) | |
428 | { | |
429 | if (avg_idle_us >= DURATION_THRESHOLD_US) | |
430 | return 0; | |
431 | ||
432 | #ifdef DEBUG | |
433 | past_skip++; | |
434 | #endif | |
435 | return 1; | |
436 | } | |
437 | ||
438 | /* Idle notifier to look at idle CPUs */ | |
439 | static int i7300_idle_notifier(struct notifier_block *nb, unsigned long val, | |
440 | void *data) | |
441 | { | |
442 | unsigned long flags; | |
443 | ktime_t now_ktime; | |
444 | static ktime_t idle_begin_time; | |
445 | static int time_init = 1; | |
446 | ||
33093e18 | 447 | if (!throttle_low_limit) |
27471fdb AH |
448 | return 0; |
449 | ||
450 | if (unlikely(time_init)) { | |
451 | time_init = 0; | |
452 | idle_begin_time = ktime_get(); | |
453 | } | |
454 | ||
455 | spin_lock_irqsave(&i7300_idle_lock, flags); | |
456 | if (val == IDLE_START) { | |
457 | ||
458 | cpu_set(smp_processor_id(), idle_cpumask); | |
459 | ||
460 | if (cpus_weight(idle_cpumask) != num_online_cpus()) | |
461 | goto end; | |
462 | ||
463 | now_ktime = ktime_get(); | |
464 | idle_begin_time = now_ktime; | |
465 | ||
466 | if (i7300_avg_duration_check()) | |
467 | goto end; | |
468 | ||
469 | i7300_idle_active = 1; | |
470 | total_starts++; | |
471 | start_ktime = now_ktime; | |
472 | ||
473 | i7300_idle_start(); | |
474 | i7300_idle_ioat_start(); | |
475 | ||
476 | } else if (val == IDLE_END) { | |
477 | cpu_clear(smp_processor_id(), idle_cpumask); | |
478 | if (cpus_weight(idle_cpumask) == (num_online_cpus() - 1)) { | |
479 | /* First CPU coming out of idle */ | |
480 | u64 idle_duration_us; | |
481 | ||
482 | now_ktime = ktime_get(); | |
483 | ||
484 | idle_duration_us = ktime_to_us(ktime_sub | |
485 | (now_ktime, idle_begin_time)); | |
486 | ||
487 | avg_idle_us = | |
488 | ((100 - DURATION_WEIGHT_PCT) * avg_idle_us + | |
489 | DURATION_WEIGHT_PCT * idle_duration_us) / 100; | |
490 | ||
491 | if (i7300_idle_active) { | |
492 | ktime_t idle_ktime; | |
493 | ||
494 | idle_ktime = ktime_sub(now_ktime, start_ktime); | |
495 | total_us += ktime_to_us(idle_ktime); | |
496 | ||
497 | i7300_idle_ioat_stop(); | |
498 | i7300_idle_stop(); | |
499 | i7300_idle_active = 0; | |
500 | } | |
501 | } | |
502 | } | |
503 | end: | |
504 | spin_unlock_irqrestore(&i7300_idle_lock, flags); | |
505 | return 0; | |
506 | } | |
507 | ||
508 | static struct notifier_block i7300_idle_nb = { | |
509 | .notifier_call = i7300_idle_notifier, | |
510 | }; | |
511 | ||
27471fdb AH |
512 | MODULE_DEVICE_TABLE(pci, pci_tbl); |
513 | ||
27471fdb AH |
514 | int stats_open_generic(struct inode *inode, struct file *fp) |
515 | { | |
516 | fp->private_data = inode->i_private; | |
517 | return 0; | |
518 | } | |
519 | ||
520 | static ssize_t stats_read_ul(struct file *fp, char __user *ubuf, size_t count, | |
521 | loff_t *off) | |
522 | { | |
523 | unsigned long *p = fp->private_data; | |
524 | char buf[32]; | |
525 | int len; | |
526 | ||
527 | len = snprintf(buf, 32, "%lu\n", *p); | |
528 | return simple_read_from_buffer(ubuf, count, off, buf, len); | |
529 | } | |
530 | ||
531 | static const struct file_operations idle_fops = { | |
532 | .open = stats_open_generic, | |
533 | .read = stats_read_ul, | |
534 | }; | |
535 | ||
536 | struct debugfs_file_info { | |
537 | void *ptr; | |
538 | char name[32]; | |
539 | struct dentry *file; | |
540 | } debugfs_file_list[] = { | |
541 | {&total_starts, "total_starts", NULL}, | |
542 | {&total_us, "total_us", NULL}, | |
543 | #ifdef DEBUG | |
544 | {&past_skip, "past_skip", NULL}, | |
545 | #endif | |
546 | {NULL, "", NULL} | |
547 | }; | |
548 | ||
549 | static int __init i7300_idle_init(void) | |
550 | { | |
551 | spin_lock_init(&i7300_idle_lock); | |
552 | cpus_clear(idle_cpumask); | |
553 | total_us = 0; | |
554 | ||
3ad0b02e | 555 | if (i7300_idle_platform_probe(&fbd_dev, &ioat_dev)) |
27471fdb AH |
556 | return -ENODEV; |
557 | ||
558 | if (i7300_idle_thrt_save()) | |
559 | return -ENODEV; | |
560 | ||
561 | if (i7300_idle_ioat_init()) | |
562 | return -ENODEV; | |
563 | ||
564 | debugfs_dir = debugfs_create_dir("i7300_idle", NULL); | |
565 | if (debugfs_dir) { | |
566 | int i = 0; | |
567 | ||
568 | while (debugfs_file_list[i].ptr != NULL) { | |
569 | debugfs_file_list[i].file = debugfs_create_file( | |
570 | debugfs_file_list[i].name, | |
571 | S_IRUSR, | |
572 | debugfs_dir, | |
573 | debugfs_file_list[i].ptr, | |
574 | &idle_fops); | |
575 | i++; | |
576 | } | |
577 | } | |
578 | ||
579 | idle_notifier_register(&i7300_idle_nb); | |
580 | ||
581 | printk(KERN_INFO "i7300_idle: loaded v%s\n", I7300_IDLE_DRIVER_VERSION); | |
582 | return 0; | |
583 | } | |
584 | ||
585 | static void __exit i7300_idle_exit(void) | |
586 | { | |
587 | idle_notifier_unregister(&i7300_idle_nb); | |
588 | ||
589 | if (debugfs_dir) { | |
590 | int i = 0; | |
591 | ||
592 | while (debugfs_file_list[i].file != NULL) { | |
593 | debugfs_remove(debugfs_file_list[i].file); | |
594 | i++; | |
595 | } | |
596 | ||
597 | debugfs_remove(debugfs_dir); | |
598 | } | |
599 | i7300_idle_thrt_restore(); | |
600 | i7300_idle_ioat_exit(); | |
601 | } | |
602 | ||
603 | module_init(i7300_idle_init); | |
604 | module_exit(i7300_idle_exit); | |
605 | ||
606 | MODULE_AUTHOR("Andy Henroid <andrew.d.henroid@intel.com>"); | |
607 | MODULE_DESCRIPTION("Intel Chipset DIMM Idle Power Saving Driver v" | |
608 | I7300_IDLE_DRIVER_VERSION); | |
609 | MODULE_LICENSE("GPL"); |