[mirror_ubuntu-artful-kernel.git] / drivers / idle / intel_idle.c

/*
 * intel_idle.c - native hardware idle loop for modern Intel processors
 *
 * Copyright (c) 2010, Intel Corporation.
 * Len Brown <len.brown@intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 */

/*
 * intel_idle is a cpuidle driver that loads on specific Intel processors
 * in lieu of the legacy ACPI processor_idle driver.  The intent is to
 * make Linux more efficient on these processors, as intel_idle knows
 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
 */

/*
 * Design Assumptions
 *
 * All CPUs have same idle states as boot CPU
 *
 * Chipset BM_STS (bus master status) bit is a NOP
 *	for preventing entry into deep C-stats
 */

/*
 * Known limitations
 *
 * The driver currently initializes for_each_online_cpu() upon modprobe.
 * It it unaware of subsequent processors hot-added to the system.
 * This means that if you boot with maxcpus=n and later online
 * processors above n, those processors will use C1 only.
 *
 * ACPI has a .suspend hack to turn off deep c-statees during suspend
 * to avoid complications with the lapic timer workaround.
 * Have not seen issues with suspend, but may need same workaround here.
 *
 * There is currently no kernel-based automatic probing/loading mechanism
 * if the driver is built as a module.
 */

/* un-comment DEBUG to enable pr_debug() statements */
#define DEBUG

#include <linux/kernel.h>
#include <linux/cpuidle.h>
#include <linux/clockchips.h>
#include <linux/hrtimer.h>	/* ktime_get_real() */
#include <trace/events/power.h>
#include <linux/sched.h>
#include <linux/notifier.h>
#include <linux/cpu.h>
#include <asm/mwait.h>

#define INTEL_IDLE_VERSION "0.4"
#define PREFIX "intel_idle: "

static struct cpuidle_driver intel_idle_driver = {
	.name = "intel_idle",
	.owner = THIS_MODULE,
};
/* intel_idle.max_cstate=0 disables driver */
static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;

static unsigned int mwait_substates;

#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
/* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
static unsigned int lapic_timer_reliable_states = (1 << 1);	 /* Default to only C1 */

static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);

static struct cpuidle_state *cpuidle_state_table;

/*
 * Set this flag for states where the HW flushes the TLB for us
 * and so we don't need cross-calls to keep it consistent.
 * If this flag is set, SW flushes the TLB, so even if the
 * HW doesn't do the flushing, this flag is safe to use.
 */
#define CPUIDLE_FLAG_TLB_FLUSHED	0x10000

/*
 * States are indexed by the cstate number,
 * which is also the index into the MWAIT hint array.
 * Thus C0 is a dummy.
 */
static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "NHM-C1",
		.desc = "MWAIT 0x00",
		.driver_data = (void *) 0x00,
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 3,
		.target_residency = 6,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "NHM-C3",
		.desc = "MWAIT 0x10",
		.driver_data = (void *) 0x10,
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 20,
		.target_residency = 80,
		.enter = &intel_idle },
	{ /* MWAIT C3 */
		.name = "NHM-C6",
		.desc = "MWAIT 0x20",
		.driver_data = (void *) 0x20,
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 200,
		.target_residency = 800,
		.enter = &intel_idle },
};

static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "SNB-C1",
		.desc = "MWAIT 0x00",
		.driver_data = (void *) 0x00,
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 1,
		.target_residency = 1,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "SNB-C3",
		.desc = "MWAIT 0x10",
		.driver_data = (void *) 0x10,
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 80,
		.target_residency = 211,
		.enter = &intel_idle },
	{ /* MWAIT C3 */
		.name = "SNB-C6",
		.desc = "MWAIT 0x20",
		.driver_data = (void *) 0x20,
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 104,
		.target_residency = 345,
		.enter = &intel_idle },
	{ /* MWAIT C4 */
		.name = "SNB-C7",
		.desc = "MWAIT 0x30",
		.driver_data = (void *) 0x30,
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 109,
		.target_residency = 345,
		.enter = &intel_idle },
};

static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "ATM-C1",
		.desc = "MWAIT 0x00",
		.driver_data = (void *) 0x00,
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 1,
		.target_residency = 4,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "ATM-C2",
		.desc = "MWAIT 0x10",
		.driver_data = (void *) 0x10,
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 20,
		.target_residency = 80,
		.enter = &intel_idle },
	{ /* MWAIT C3 */ },
	{ /* MWAIT C4 */
		.name = "ATM-C4",
		.desc = "MWAIT 0x30",
		.driver_data = (void *) 0x30,
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 100,
		.target_residency = 400,
		.enter = &intel_idle },
	{ /* MWAIT C5 */ },
	{ /* MWAIT C6 */
		.name = "ATM-C6",
		.desc = "MWAIT 0x52",
		.driver_data = (void *) 0x52,
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 140,
		.target_residency = 560,
		.enter = &intel_idle },
};

/**
 * intel_idle
 * @dev: cpuidle_device
 * @state: cpuidle state
 *
 */
static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
{
	unsigned long ecx = 1; /* break on interrupt flag */
	unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
	unsigned int cstate;
	ktime_t kt_before, kt_after;
	s64 usec_delta;
	int cpu = smp_processor_id();

	cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;

	local_irq_disable();

	/*
	 * leave_mm() to avoid costly and often unnecessary wakeups
	 * for flushing the user TLB's associated with the active mm.
	 */
	if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
		leave_mm(cpu);

	if (!(lapic_timer_reliable_states & (1 << (cstate))))
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

	kt_before = ktime_get_real();

	stop_critical_timings();
	if (!need_resched()) {

		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__mwait(eax, ecx);
	}

	start_critical_timings();

	kt_after = ktime_get_real();
	usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));

	local_irq_enable();

	if (!(lapic_timer_reliable_states & (1 << (cstate))))
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);

	return usec_delta;
}

static void __setup_broadcast_timer(void *arg)
{
	unsigned long reason = (unsigned long)arg;
	int cpu = smp_processor_id();

	reason = reason ?
		CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;

	clockevents_notify(reason, &cpu);
}

static int __cpuinit setup_broadcast_cpuhp_notify(struct notifier_block *n,
		unsigned long action, void *hcpu)
{
	int hotcpu = (unsigned long)hcpu;

	switch (action & 0xf) {
	case CPU_ONLINE:
		smp_call_function_single(hotcpu, __setup_broadcast_timer,
			(void *)true, 1);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(hotcpu, __setup_broadcast_timer,
			(void *)false, 1);
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block __cpuinitdata setup_broadcast_notifier = {
	.notifier_call = setup_broadcast_cpuhp_notify,
};

/*
 * intel_idle_probe()
 */
static int intel_idle_probe(void)
{
	unsigned int eax, ebx, ecx;

	if (max_cstate == 0) {
		pr_debug(PREFIX "disabled\n");
		return -EPERM;
	}

	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
		return -ENODEV;

	if (!boot_cpu_has(X86_FEATURE_MWAIT))
		return -ENODEV;

	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
		return -ENODEV;

	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);

	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
		!(ecx & CPUID5_ECX_INTERRUPT_BREAK))
			return -ENODEV;

	pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);


	if (boot_cpu_data.x86 != 6)	/* family 6 */
		return -ENODEV;

	switch (boot_cpu_data.x86_model) {

	case 0x1A:	/* Core i7, Xeon 5500 series */
	case 0x1E:	/* Core i7 and i5 Processor - Lynnfield Jasper Forest */
	case 0x1F:	/* Core i7 and i5 Processor - Nehalem */
	case 0x2E:	/* Nehalem-EX Xeon */
	case 0x2F:	/* Westmere-EX Xeon */
	case 0x25:	/* Westmere */
	case 0x2C:	/* Westmere */
		cpuidle_state_table = nehalem_cstates;
		break;

	case 0x1C:	/* 28 - Atom Processor */
	case 0x26:	/* 38 - Lincroft Atom Processor */
		cpuidle_state_table = atom_cstates;
		break;

	case 0x2A:	/* SNB */
	case 0x2D:	/* SNB Xeon */
		cpuidle_state_table = snb_cstates;
		break;

	default:
		pr_debug(PREFIX "does not run on family %d model %d\n",
			boot_cpu_data.x86, boot_cpu_data.x86_model);
		return -ENODEV;
	}

	if (boot_cpu_has(X86_FEATURE_ARAT))	/* Always Reliable APIC Timer */
		lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
	else {
		smp_call_function(__setup_broadcast_timer, (void *)true, 1);
		register_cpu_notifier(&setup_broadcast_notifier);
	}

	pr_debug(PREFIX "v" INTEL_IDLE_VERSION
		" model 0x%X\n", boot_cpu_data.x86_model);

	pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
		lapic_timer_reliable_states);
	return 0;
}

/*
 * intel_idle_cpuidle_devices_uninit()
 * unregister, free cpuidle_devices
 */
static void intel_idle_cpuidle_devices_uninit(void)
{
	int i;
	struct cpuidle_device *dev;

	for_each_online_cpu(i) {
		dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
		cpuidle_unregister_device(dev);
	}

	free_percpu(intel_idle_cpuidle_devices);
	return;
}
/*
 * intel_idle_cpuidle_devices_init()
 * allocate, initialize, register cpuidle_devices
 */
static int intel_idle_cpuidle_devices_init(void)
{
	int i, cstate;
	struct cpuidle_device *dev;

	intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
	if (intel_idle_cpuidle_devices == NULL)
		return -ENOMEM;

	for_each_online_cpu(i) {
		dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);

		dev->state_count = 1;

		for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
			int num_substates;

			if (cstate > max_cstate) {
				printk(PREFIX "max_cstate %d reached\n",
					max_cstate);
				break;
			}

			/* does the state exist in CPUID.MWAIT? */
			num_substates = (mwait_substates >> ((cstate) * 4))
						& MWAIT_SUBSTATE_MASK;
			if (num_substates == 0)
				continue;
			/* is the state not enabled? */
			if (cpuidle_state_table[cstate].enter == NULL) {
				/* does the driver not know about the state? */
				if (*cpuidle_state_table[cstate].name == '\0')
					pr_debug(PREFIX "unaware of model 0x%x"
						" MWAIT %d please"
						" contact lenb@kernel.org",
					boot_cpu_data.x86_model, cstate);
				continue;
			}

			if ((cstate > 2) &&
				!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
				mark_tsc_unstable("TSC halts in idle"
					" states deeper than C2");

			dev->states[dev->state_count] =	/* structure copy */
				cpuidle_state_table[cstate];

			dev->state_count += 1;
		}

		dev->cpu = i;
		if (cpuidle_register_device(dev)) {
			pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
				 i);
			intel_idle_cpuidle_devices_uninit();
			return -EIO;
		}
	}

	return 0;
}


static int __init intel_idle_init(void)
{
	int retval;

	/* Do not load intel_idle at all for now if idle= is passed */
	if (boot_option_idle_override != IDLE_NO_OVERRIDE)
		return -ENODEV;

	retval = intel_idle_probe();
	if (retval)
		return retval;

	retval = cpuidle_register_driver(&intel_idle_driver);
	if (retval) {
		printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
			cpuidle_get_driver()->name);
		return retval;
	}

	retval = intel_idle_cpuidle_devices_init();
	if (retval) {
		cpuidle_unregister_driver(&intel_idle_driver);
		return retval;
	}

	return 0;
}

static void __exit intel_idle_exit(void)
{
	intel_idle_cpuidle_devices_uninit();
	cpuidle_unregister_driver(&intel_idle_driver);

	if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
		smp_call_function(__setup_broadcast_timer, (void *)false, 1);
		unregister_cpu_notifier(&setup_broadcast_notifier);
	}

	return;
}

module_init(intel_idle_init);
module_exit(intel_idle_exit);

module_param(max_cstate, int, 0444);

MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
MODULE_LICENSE("GPL");
Commit	Line	Data
26717172 LB	1	/*
	2	* intel_idle.c - native hardware idle loop for modern Intel processors
	3	*
	4	* Copyright (c) 2010, Intel Corporation.
	5	* Len Brown <len.brown@intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	/*
	22	* intel_idle is a cpuidle driver that loads on specific Intel processors
	23	* in lieu of the legacy ACPI processor_idle driver. The intent is to
	24	* make Linux more efficient on these processors, as intel_idle knows
	25	* more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
	26	*/
	27
	28	/*
	29	* Design Assumptions
	30	*
	31	* All CPUs have same idle states as boot CPU
	32	*
	33	* Chipset BM_STS (bus master status) bit is a NOP
	34	* for preventing entry into deep C-stats
	35	*/
	36
	37	/*
	38	* Known limitations
	39	*
	40	* The driver currently initializes for_each_online_cpu() upon modprobe.
	41	* It it unaware of subsequent processors hot-added to the system.
	42	* This means that if you boot with maxcpus=n and later online
	43	* processors above n, those processors will use C1 only.
	44	*
	45	* ACPI has a .suspend hack to turn off deep c-statees during suspend
	46	* to avoid complications with the lapic timer workaround.
	47	* Have not seen issues with suspend, but may need same workaround here.
	48	*
	49	* There is currently no kernel-based automatic probing/loading mechanism
	50	* if the driver is built as a module.
	51	*/
	52
	53	/* un-comment DEBUG to enable pr_debug() statements */
	54	#define DEBUG
	55
	56	#include <linux/kernel.h>
	57	#include <linux/cpuidle.h>
	58	#include <linux/clockchips.h>
	59	#include <linux/hrtimer.h> /* ktime_get_real() */
	60	#include <trace/events/power.h>
	61	#include <linux/sched.h>
2a2d31c8 SL	62	#include <linux/notifier.h>
2a2d31c8 SL	63	#include <linux/cpu.h>
bc83cccc	64	#include <asm/mwait.h>
26717172 LB	65
	66	#define INTEL_IDLE_VERSION "0.4"
	67	#define PREFIX "intel_idle: "
	68
26717172 LB	69	static struct cpuidle_driver intel_idle_driver = {
	70	.name = "intel_idle",
	71	.owner = THIS_MODULE,
	72	};
	73	/* intel_idle.max_cstate=0 disables driver */
	74	static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
26717172	75
c4236282	76	static unsigned int mwait_substates;
26717172	77
2a2d31c8	78	#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
26717172	79	/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
d13780d4	80	static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
26717172	81
3265eba0	82	static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
26717172 LB	83	static int intel_idle(struct cpuidle_device dev, struct cpuidle_state state);
	84
	85	static struct cpuidle_state *cpuidle_state_table;
	86
956d033f LB	87	/*
	88	* Set this flag for states where the HW flushes the TLB for us
	89	* and so we don't need cross-calls to keep it consistent.
	90	* If this flag is set, SW flushes the TLB, so even if the
	91	* HW doesn't do the flushing, this flag is safe to use.
	92	*/
	93	#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
	94
26717172 LB	95	/*
	96	* States are indexed by the cstate number,
	97	* which is also the index into the MWAIT hint array.
	98	* Thus C0 is a dummy.
	99	*/
	100	static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
	101	{ /* MWAIT C0 */ },
	102	{ /* MWAIT C1 */
	103	.name = "NHM-C1",
	104	.desc = "MWAIT 0x00",
	105	.driver_data = (void *) 0x00,
	106	.flags = CPUIDLE_FLAG_TIME_VALID,
	107	.exit_latency = 3,
26717172 LB	108	.target_residency = 6,
	109	.enter = &intel_idle },
	110	{ /* MWAIT C2 */
	111	.name = "NHM-C3",
	112	.desc = "MWAIT 0x10",
	113	.driver_data = (void *) 0x10,
6110a1f4	114	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	115	.exit_latency = 20,
26717172 LB	116	.target_residency = 80,
	117	.enter = &intel_idle },
	118	{ /* MWAIT C3 */
	119	.name = "NHM-C6",
	120	.desc = "MWAIT 0x20",
	121	.driver_data = (void *) 0x20,
6110a1f4	122	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	123	.exit_latency = 200,
26717172 LB	124	.target_residency = 800,
	125	.enter = &intel_idle },
	126	};
	127
d13780d4 LB	128	static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	129	{ /* MWAIT C0 */ },
	130	{ /* MWAIT C1 */
	131	.name = "SNB-C1",
	132	.desc = "MWAIT 0x00",
	133	.driver_data = (void *) 0x00,
	134	.flags = CPUIDLE_FLAG_TIME_VALID,
	135	.exit_latency = 1,
ddbd550d	136	.target_residency = 1,
d13780d4 LB	137	.enter = &intel_idle },
	138	{ /* MWAIT C2 */
	139	.name = "SNB-C3",
	140	.desc = "MWAIT 0x10",
	141	.driver_data = (void *) 0x10,
00527cc6	142	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	143	.exit_latency = 80,
ddbd550d	144	.target_residency = 211,
d13780d4 LB	145	.enter = &intel_idle },
	146	{ /* MWAIT C3 */
	147	.name = "SNB-C6",
	148	.desc = "MWAIT 0x20",
	149	.driver_data = (void *) 0x20,
00527cc6	150	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	151	.exit_latency = 104,
ddbd550d	152	.target_residency = 345,
d13780d4 LB	153	.enter = &intel_idle },
	154	{ /* MWAIT C4 */
	155	.name = "SNB-C7",
	156	.desc = "MWAIT 0x30",
	157	.driver_data = (void *) 0x30,
00527cc6	158	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	159	.exit_latency = 109,
ddbd550d	160	.target_residency = 345,
d13780d4 LB	161	.enter = &intel_idle },
	162	};
	163
26717172 LB	164	static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
	165	{ /* MWAIT C0 */ },
	166	{ /* MWAIT C1 */
	167	.name = "ATM-C1",
	168	.desc = "MWAIT 0x00",
	169	.driver_data = (void *) 0x00,
	170	.flags = CPUIDLE_FLAG_TIME_VALID,
	171	.exit_latency = 1,
26717172 LB	172	.target_residency = 4,
	173	.enter = &intel_idle },
	174	{ /* MWAIT C2 */
	175	.name = "ATM-C2",
	176	.desc = "MWAIT 0x10",
	177	.driver_data = (void *) 0x10,
	178	.flags = CPUIDLE_FLAG_TIME_VALID,
	179	.exit_latency = 20,
26717172 LB	180	.target_residency = 80,
	181	.enter = &intel_idle },
	182	{ /* MWAIT C3 */ },
	183	{ /* MWAIT C4 */
	184	.name = "ATM-C4",
	185	.desc = "MWAIT 0x30",
	186	.driver_data = (void *) 0x30,
6110a1f4	187	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	188	.exit_latency = 100,
26717172 LB	189	.target_residency = 400,
	190	.enter = &intel_idle },
	191	{ /* MWAIT C5 */ },
	192	{ /* MWAIT C6 */
	193	.name = "ATM-C6",
7fcca7d9 LB	194	.desc = "MWAIT 0x52",
7fcca7d9 LB	195	.driver_data = (void *) 0x52,
6110a1f4	196	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
7fcca7d9	197	.exit_latency = 140,
7fcca7d9 LB	198	.target_residency = 560,
7fcca7d9 LB	199	.enter = &intel_idle },
26717172 LB	200	};
26717172 LB	201
26717172 LB	202	/**
	203	* intel_idle
	204	* @dev: cpuidle_device
	205	* @state: cpuidle state
	206	*
	207	*/
	208	static int intel_idle(struct cpuidle_device dev, struct cpuidle_state state)
	209	{
	210	unsigned long ecx = 1; /* break on interrupt flag */
	211	unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
	212	unsigned int cstate;
	213	ktime_t kt_before, kt_after;
	214	s64 usec_delta;
	215	int cpu = smp_processor_id();
	216
	217	cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
	218
26717172 LB	219	local_irq_disable();
26717172 LB	220
6110a1f4	221	/*
c8381cc3 LB	222	* leave_mm() to avoid costly and often unnecessary wakeups
c8381cc3 LB	223	* for flushing the user TLB's associated with the active mm.
6110a1f4	224	*/
c8381cc3	225	if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
6110a1f4 SS	226	leave_mm(cpu);
6110a1f4 SS	227
26717172 LB	228	if (!(lapic_timer_reliable_states & (1 << (cstate))))
	229	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
	230
	231	kt_before = ktime_get_real();
	232
	233	stop_critical_timings();
26717172 LB	234	if (!need_resched()) {
	235
	236	__monitor((void *)&current_thread_info()->flags, 0, 0);
	237	smp_mb();
	238	if (!need_resched())
	239	__mwait(eax, ecx);
	240	}
	241
	242	start_critical_timings();
	243
	244	kt_after = ktime_get_real();
	245	usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
	246
	247	local_irq_enable();
	248
	249	if (!(lapic_timer_reliable_states & (1 << (cstate))))
	250	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	251
	252	return usec_delta;
	253	}
	254
2a2d31c8 SL	255	static void __setup_broadcast_timer(void *arg)
	256	{
	257	unsigned long reason = (unsigned long)arg;
	258	int cpu = smp_processor_id();
	259
	260	reason = reason ?
	261	CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
	262
	263	clockevents_notify(reason, &cpu);
	264	}
	265
	266	static int __cpuinit setup_broadcast_cpuhp_notify(struct notifier_block *n,
	267	unsigned long action, void *hcpu)
	268	{
	269	int hotcpu = (unsigned long)hcpu;
	270
	271	switch (action & 0xf) {
	272	case CPU_ONLINE:
	273	smp_call_function_single(hotcpu, __setup_broadcast_timer,
	274	(void *)true, 1);
	275	break;
	276	case CPU_DOWN_PREPARE:
	277	smp_call_function_single(hotcpu, __setup_broadcast_timer,
	278	(void *)false, 1);
	279	break;
	280	}
	281	return NOTIFY_OK;
	282	}
	283
	284	static struct notifier_block __cpuinitdata setup_broadcast_notifier = {
	285	.notifier_call = setup_broadcast_cpuhp_notify,
	286	};
	287
26717172 LB	288	/*
	289	* intel_idle_probe()
	290	*/
	291	static int intel_idle_probe(void)
	292	{
c4236282	293	unsigned int eax, ebx, ecx;
26717172 LB	294
	295	if (max_cstate == 0) {
	296	pr_debug(PREFIX "disabled\n");
	297	return -EPERM;
	298	}
	299
	300	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
	301	return -ENODEV;
	302
	303	if (!boot_cpu_has(X86_FEATURE_MWAIT))
	304	return -ENODEV;
	305
	306	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
	307	return -ENODEV;
	308
c4236282	309	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
26717172 LB	310
	311	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) \|\|
	312	!(ecx & CPUID5_ECX_INTERRUPT_BREAK))
	313	return -ENODEV;
26717172	314
c4236282	315	pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
26717172	316
26717172 LB	317
	318	if (boot_cpu_data.x86 != 6) /* family 6 */
	319	return -ENODEV;
	320
	321	switch (boot_cpu_data.x86_model) {
	322
	323	case 0x1A: /* Core i7, Xeon 5500 series */
	324	case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
	325	case 0x1F: /* Core i7 and i5 Processor - Nehalem */
	326	case 0x2E: /* Nehalem-EX Xeon */
ec67a2ba	327	case 0x2F: /* Westmere-EX Xeon */
26717172 LB	328	case 0x25: /* Westmere */
	329	case 0x2C: /* Westmere */
	330	cpuidle_state_table = nehalem_cstates;
26717172 LB	331	break;
	332
	333	case 0x1C: /* 28 - Atom Processor */
4725fd3c	334	case 0x26: /* 38 - Lincroft Atom Processor */
26717172	335	cpuidle_state_table = atom_cstates;
26717172	336	break;
d13780d4 LB	337
	338	case 0x2A: /* SNB */
	339	case 0x2D: /* SNB Xeon */
	340	cpuidle_state_table = snb_cstates;
d13780d4	341	break;
26717172 LB	342
	343	default:
	344	pr_debug(PREFIX "does not run on family %d model %d\n",
	345	boot_cpu_data.x86, boot_cpu_data.x86_model);
	346	return -ENODEV;
	347	}
	348
56b9aea3	349	if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
2a2d31c8 SL	350	lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
	351	else {
	352	smp_call_function(__setup_broadcast_timer, (void *)true, 1);
	353	register_cpu_notifier(&setup_broadcast_notifier);
	354	}
56b9aea3	355
26717172 LB	356	pr_debug(PREFIX "v" INTEL_IDLE_VERSION
	357	" model 0x%X\n", boot_cpu_data.x86_model);
	358
	359	pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
	360	lapic_timer_reliable_states);
	361	return 0;
	362	}
	363
	364	/*
	365	* intel_idle_cpuidle_devices_uninit()
	366	* unregister, free cpuidle_devices
	367	*/
	368	static void intel_idle_cpuidle_devices_uninit(void)
	369	{
	370	int i;
	371	struct cpuidle_device *dev;
	372
	373	for_each_online_cpu(i) {
	374	dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
	375	cpuidle_unregister_device(dev);
	376	}
	377
	378	free_percpu(intel_idle_cpuidle_devices);
	379	return;
	380	}
	381	/*
	382	* intel_idle_cpuidle_devices_init()
	383	* allocate, initialize, register cpuidle_devices
	384	*/
	385	static int intel_idle_cpuidle_devices_init(void)
	386	{
	387	int i, cstate;
	388	struct cpuidle_device *dev;
	389
	390	intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
	391	if (intel_idle_cpuidle_devices == NULL)
	392	return -ENOMEM;
	393
	394	for_each_online_cpu(i) {
	395	dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
	396
	397	dev->state_count = 1;
	398
	399	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
	400	int num_substates;
	401
	402	if (cstate > max_cstate) {
	403	printk(PREFIX "max_cstate %d reached\n",
	404	max_cstate);
	405	break;
	406	}
	407
	408	/* does the state exist in CPUID.MWAIT? */
c4236282	409	num_substates = (mwait_substates >> ((cstate) * 4))
26717172 LB	410	& MWAIT_SUBSTATE_MASK;
	411	if (num_substates == 0)
	412	continue;
	413	/* is the state not enabled? */
	414	if (cpuidle_state_table[cstate].enter == NULL) {
	415	/* does the driver not know about the state? */
	416	if (*cpuidle_state_table[cstate].name == '\0')
	417	pr_debug(PREFIX "unaware of model 0x%x"
	418	" MWAIT %d please"
	419	" contact lenb@kernel.org",
	420	boot_cpu_data.x86_model, cstate);
	421	continue;
	422	}
	423
	424	if ((cstate > 2) &&
	425	!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
	426	mark_tsc_unstable("TSC halts in idle"
	427	" states deeper than C2");
	428
	429	dev->states[dev->state_count] = /* structure copy */
	430	cpuidle_state_table[cstate];
	431
	432	dev->state_count += 1;
	433	}
	434
	435	dev->cpu = i;
	436	if (cpuidle_register_device(dev)) {
	437	pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
	438	i);
	439	intel_idle_cpuidle_devices_uninit();
	440	return -EIO;
	441	}
	442	}
	443
	444	return 0;
	445	}
	446
	447
	448	static int __init intel_idle_init(void)
	449	{
	450	int retval;
	451
d1896049 TR	452	/* Do not load intel_idle at all for now if idle= is passed */
	453	if (boot_option_idle_override != IDLE_NO_OVERRIDE)
	454	return -ENODEV;
	455
26717172 LB	456	retval = intel_idle_probe();
	457	if (retval)
	458	return retval;
	459
	460	retval = cpuidle_register_driver(&intel_idle_driver);
	461	if (retval) {
	462	printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
	463	cpuidle_get_driver()->name);
	464	return retval;
	465	}
	466
	467	retval = intel_idle_cpuidle_devices_init();
	468	if (retval) {
	469	cpuidle_unregister_driver(&intel_idle_driver);
	470	return retval;
	471	}
	472
	473	return 0;
	474	}
	475
	476	static void __exit intel_idle_exit(void)
	477	{
	478	intel_idle_cpuidle_devices_uninit();
	479	cpuidle_unregister_driver(&intel_idle_driver);
	480
2a2d31c8 SL	481	if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
	482	smp_call_function(__setup_broadcast_timer, (void *)false, 1);
	483	unregister_cpu_notifier(&setup_broadcast_notifier);
	484	}
	485
26717172 LB	486	return;
	487	}
	488
	489	module_init(intel_idle_init);
	490	module_exit(intel_idle_exit);
	491
26717172	492	module_param(max_cstate, int, 0444);
26717172 LB	493
	494	MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
	495	MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
	496	MODULE_LICENSE("GPL");