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26717172 LB |
1 | /* |
2 | * intel_idle.c - native hardware idle loop for modern Intel processors | |
3 | * | |
4 | * Copyright (c) 2010, Intel Corporation. | |
5 | * Len Brown <len.brown@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * intel_idle is a cpuidle driver that loads on specific Intel processors | |
23 | * in lieu of the legacy ACPI processor_idle driver. The intent is to | |
24 | * make Linux more efficient on these processors, as intel_idle knows | |
25 | * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Design Assumptions | |
30 | * | |
31 | * All CPUs have same idle states as boot CPU | |
32 | * | |
33 | * Chipset BM_STS (bus master status) bit is a NOP | |
34 | * for preventing entry into deep C-stats | |
35 | */ | |
36 | ||
37 | /* | |
38 | * Known limitations | |
39 | * | |
40 | * The driver currently initializes for_each_online_cpu() upon modprobe. | |
41 | * It it unaware of subsequent processors hot-added to the system. | |
42 | * This means that if you boot with maxcpus=n and later online | |
43 | * processors above n, those processors will use C1 only. | |
44 | * | |
45 | * ACPI has a .suspend hack to turn off deep c-statees during suspend | |
46 | * to avoid complications with the lapic timer workaround. | |
47 | * Have not seen issues with suspend, but may need same workaround here. | |
48 | * | |
49 | * There is currently no kernel-based automatic probing/loading mechanism | |
50 | * if the driver is built as a module. | |
51 | */ | |
52 | ||
53 | /* un-comment DEBUG to enable pr_debug() statements */ | |
54 | #define DEBUG | |
55 | ||
56 | #include <linux/kernel.h> | |
57 | #include <linux/cpuidle.h> | |
58 | #include <linux/clockchips.h> | |
59 | #include <linux/hrtimer.h> /* ktime_get_real() */ | |
60 | #include <trace/events/power.h> | |
61 | #include <linux/sched.h> | |
62 | ||
63 | #define INTEL_IDLE_VERSION "0.4" | |
64 | #define PREFIX "intel_idle: " | |
65 | ||
66 | #define MWAIT_SUBSTATE_MASK (0xf) | |
67 | #define MWAIT_CSTATE_MASK (0xf) | |
68 | #define MWAIT_SUBSTATE_SIZE (4) | |
69 | #define MWAIT_MAX_NUM_CSTATES 8 | |
70 | #define CPUID_MWAIT_LEAF (5) | |
71 | #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1) | |
72 | #define CPUID5_ECX_INTERRUPT_BREAK (0x2) | |
73 | ||
74 | static struct cpuidle_driver intel_idle_driver = { | |
75 | .name = "intel_idle", | |
76 | .owner = THIS_MODULE, | |
77 | }; | |
78 | /* intel_idle.max_cstate=0 disables driver */ | |
79 | static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1; | |
26717172 | 80 | |
c4236282 | 81 | static unsigned int mwait_substates; |
26717172 LB |
82 | |
83 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ | |
84 | static unsigned int lapic_timer_reliable_states; | |
85 | ||
86 | static struct cpuidle_device *intel_idle_cpuidle_devices; | |
87 | static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state); | |
88 | ||
89 | static struct cpuidle_state *cpuidle_state_table; | |
90 | ||
91 | /* | |
92 | * States are indexed by the cstate number, | |
93 | * which is also the index into the MWAIT hint array. | |
94 | * Thus C0 is a dummy. | |
95 | */ | |
96 | static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = { | |
97 | { /* MWAIT C0 */ }, | |
98 | { /* MWAIT C1 */ | |
99 | .name = "NHM-C1", | |
100 | .desc = "MWAIT 0x00", | |
101 | .driver_data = (void *) 0x00, | |
102 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
103 | .exit_latency = 3, | |
104 | .power_usage = 1000, | |
105 | .target_residency = 6, | |
106 | .enter = &intel_idle }, | |
107 | { /* MWAIT C2 */ | |
108 | .name = "NHM-C3", | |
109 | .desc = "MWAIT 0x10", | |
110 | .driver_data = (void *) 0x10, | |
111 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
112 | .exit_latency = 20, | |
113 | .power_usage = 500, | |
114 | .target_residency = 80, | |
115 | .enter = &intel_idle }, | |
116 | { /* MWAIT C3 */ | |
117 | .name = "NHM-C6", | |
118 | .desc = "MWAIT 0x20", | |
119 | .driver_data = (void *) 0x20, | |
120 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
121 | .exit_latency = 200, | |
122 | .power_usage = 350, | |
123 | .target_residency = 800, | |
124 | .enter = &intel_idle }, | |
125 | }; | |
126 | ||
127 | static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { | |
128 | { /* MWAIT C0 */ }, | |
129 | { /* MWAIT C1 */ | |
130 | .name = "ATM-C1", | |
131 | .desc = "MWAIT 0x00", | |
132 | .driver_data = (void *) 0x00, | |
133 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
134 | .exit_latency = 1, | |
135 | .power_usage = 1000, | |
136 | .target_residency = 4, | |
137 | .enter = &intel_idle }, | |
138 | { /* MWAIT C2 */ | |
139 | .name = "ATM-C2", | |
140 | .desc = "MWAIT 0x10", | |
141 | .driver_data = (void *) 0x10, | |
142 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
143 | .exit_latency = 20, | |
144 | .power_usage = 500, | |
145 | .target_residency = 80, | |
146 | .enter = &intel_idle }, | |
147 | { /* MWAIT C3 */ }, | |
148 | { /* MWAIT C4 */ | |
149 | .name = "ATM-C4", | |
150 | .desc = "MWAIT 0x30", | |
151 | .driver_data = (void *) 0x30, | |
152 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
153 | .exit_latency = 100, | |
154 | .power_usage = 250, | |
155 | .target_residency = 400, | |
156 | .enter = &intel_idle }, | |
157 | { /* MWAIT C5 */ }, | |
158 | { /* MWAIT C6 */ | |
159 | .name = "ATM-C6", | |
160 | .desc = "MWAIT 0x40", | |
161 | .driver_data = (void *) 0x40, | |
162 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
163 | .exit_latency = 200, | |
164 | .power_usage = 150, | |
165 | .target_residency = 800, | |
166 | .enter = NULL }, /* disabled */ | |
167 | }; | |
168 | ||
26717172 LB |
169 | /** |
170 | * intel_idle | |
171 | * @dev: cpuidle_device | |
172 | * @state: cpuidle state | |
173 | * | |
174 | */ | |
175 | static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state) | |
176 | { | |
177 | unsigned long ecx = 1; /* break on interrupt flag */ | |
178 | unsigned long eax = (unsigned long)cpuidle_get_statedata(state); | |
179 | unsigned int cstate; | |
180 | ktime_t kt_before, kt_after; | |
181 | s64 usec_delta; | |
182 | int cpu = smp_processor_id(); | |
183 | ||
184 | cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; | |
185 | ||
26717172 LB |
186 | local_irq_disable(); |
187 | ||
188 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) | |
189 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
190 | ||
191 | kt_before = ktime_get_real(); | |
192 | ||
193 | stop_critical_timings(); | |
194 | #ifndef MODULE | |
195 | trace_power_start(POWER_CSTATE, (eax >> 4) + 1); | |
196 | #endif | |
197 | if (!need_resched()) { | |
198 | ||
199 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
200 | smp_mb(); | |
201 | if (!need_resched()) | |
202 | __mwait(eax, ecx); | |
203 | } | |
204 | ||
205 | start_critical_timings(); | |
206 | ||
207 | kt_after = ktime_get_real(); | |
208 | usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before)); | |
209 | ||
210 | local_irq_enable(); | |
211 | ||
212 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) | |
213 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
214 | ||
215 | return usec_delta; | |
216 | } | |
217 | ||
218 | /* | |
219 | * intel_idle_probe() | |
220 | */ | |
221 | static int intel_idle_probe(void) | |
222 | { | |
c4236282 | 223 | unsigned int eax, ebx, ecx; |
26717172 LB |
224 | |
225 | if (max_cstate == 0) { | |
226 | pr_debug(PREFIX "disabled\n"); | |
227 | return -EPERM; | |
228 | } | |
229 | ||
230 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
231 | return -ENODEV; | |
232 | ||
233 | if (!boot_cpu_has(X86_FEATURE_MWAIT)) | |
234 | return -ENODEV; | |
235 | ||
236 | if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
237 | return -ENODEV; | |
238 | ||
c4236282 | 239 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); |
26717172 LB |
240 | |
241 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || | |
242 | !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) | |
243 | return -ENODEV; | |
26717172 | 244 | |
c4236282 | 245 | pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); |
26717172 LB |
246 | |
247 | if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ | |
248 | lapic_timer_reliable_states = 0xFFFFFFFF; | |
249 | ||
250 | if (boot_cpu_data.x86 != 6) /* family 6 */ | |
251 | return -ENODEV; | |
252 | ||
253 | switch (boot_cpu_data.x86_model) { | |
254 | ||
255 | case 0x1A: /* Core i7, Xeon 5500 series */ | |
256 | case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */ | |
257 | case 0x1F: /* Core i7 and i5 Processor - Nehalem */ | |
258 | case 0x2E: /* Nehalem-EX Xeon */ | |
259 | lapic_timer_reliable_states = (1 << 1); /* C1 */ | |
260 | ||
261 | case 0x25: /* Westmere */ | |
262 | case 0x2C: /* Westmere */ | |
263 | cpuidle_state_table = nehalem_cstates; | |
26717172 LB |
264 | break; |
265 | ||
266 | case 0x1C: /* 28 - Atom Processor */ | |
267 | lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */ | |
268 | cpuidle_state_table = atom_cstates; | |
26717172 LB |
269 | break; |
270 | #ifdef FUTURE_USE | |
271 | case 0x17: /* 23 - Core 2 Duo */ | |
272 | lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */ | |
273 | #endif | |
274 | ||
275 | default: | |
276 | pr_debug(PREFIX "does not run on family %d model %d\n", | |
277 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
278 | return -ENODEV; | |
279 | } | |
280 | ||
281 | pr_debug(PREFIX "v" INTEL_IDLE_VERSION | |
282 | " model 0x%X\n", boot_cpu_data.x86_model); | |
283 | ||
284 | pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", | |
285 | lapic_timer_reliable_states); | |
286 | return 0; | |
287 | } | |
288 | ||
289 | /* | |
290 | * intel_idle_cpuidle_devices_uninit() | |
291 | * unregister, free cpuidle_devices | |
292 | */ | |
293 | static void intel_idle_cpuidle_devices_uninit(void) | |
294 | { | |
295 | int i; | |
296 | struct cpuidle_device *dev; | |
297 | ||
298 | for_each_online_cpu(i) { | |
299 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
300 | cpuidle_unregister_device(dev); | |
301 | } | |
302 | ||
303 | free_percpu(intel_idle_cpuidle_devices); | |
304 | return; | |
305 | } | |
306 | /* | |
307 | * intel_idle_cpuidle_devices_init() | |
308 | * allocate, initialize, register cpuidle_devices | |
309 | */ | |
310 | static int intel_idle_cpuidle_devices_init(void) | |
311 | { | |
312 | int i, cstate; | |
313 | struct cpuidle_device *dev; | |
314 | ||
315 | intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); | |
316 | if (intel_idle_cpuidle_devices == NULL) | |
317 | return -ENOMEM; | |
318 | ||
319 | for_each_online_cpu(i) { | |
320 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
321 | ||
322 | dev->state_count = 1; | |
323 | ||
324 | for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) { | |
325 | int num_substates; | |
326 | ||
327 | if (cstate > max_cstate) { | |
328 | printk(PREFIX "max_cstate %d reached\n", | |
329 | max_cstate); | |
330 | break; | |
331 | } | |
332 | ||
333 | /* does the state exist in CPUID.MWAIT? */ | |
c4236282 | 334 | num_substates = (mwait_substates >> ((cstate) * 4)) |
26717172 LB |
335 | & MWAIT_SUBSTATE_MASK; |
336 | if (num_substates == 0) | |
337 | continue; | |
338 | /* is the state not enabled? */ | |
339 | if (cpuidle_state_table[cstate].enter == NULL) { | |
340 | /* does the driver not know about the state? */ | |
341 | if (*cpuidle_state_table[cstate].name == '\0') | |
342 | pr_debug(PREFIX "unaware of model 0x%x" | |
343 | " MWAIT %d please" | |
344 | " contact lenb@kernel.org", | |
345 | boot_cpu_data.x86_model, cstate); | |
346 | continue; | |
347 | } | |
348 | ||
349 | if ((cstate > 2) && | |
350 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
351 | mark_tsc_unstable("TSC halts in idle" | |
352 | " states deeper than C2"); | |
353 | ||
354 | dev->states[dev->state_count] = /* structure copy */ | |
355 | cpuidle_state_table[cstate]; | |
356 | ||
357 | dev->state_count += 1; | |
358 | } | |
359 | ||
360 | dev->cpu = i; | |
361 | if (cpuidle_register_device(dev)) { | |
362 | pr_debug(PREFIX "cpuidle_register_device %d failed!\n", | |
363 | i); | |
364 | intel_idle_cpuidle_devices_uninit(); | |
365 | return -EIO; | |
366 | } | |
367 | } | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | ||
373 | static int __init intel_idle_init(void) | |
374 | { | |
375 | int retval; | |
376 | ||
377 | retval = intel_idle_probe(); | |
378 | if (retval) | |
379 | return retval; | |
380 | ||
381 | retval = cpuidle_register_driver(&intel_idle_driver); | |
382 | if (retval) { | |
383 | printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", | |
384 | cpuidle_get_driver()->name); | |
385 | return retval; | |
386 | } | |
387 | ||
388 | retval = intel_idle_cpuidle_devices_init(); | |
389 | if (retval) { | |
390 | cpuidle_unregister_driver(&intel_idle_driver); | |
391 | return retval; | |
392 | } | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | static void __exit intel_idle_exit(void) | |
398 | { | |
399 | intel_idle_cpuidle_devices_uninit(); | |
400 | cpuidle_unregister_driver(&intel_idle_driver); | |
401 | ||
402 | return; | |
403 | } | |
404 | ||
405 | module_init(intel_idle_init); | |
406 | module_exit(intel_idle_exit); | |
407 | ||
26717172 | 408 | module_param(max_cstate, int, 0444); |
26717172 LB |
409 | |
410 | MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); | |
411 | MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); | |
412 | MODULE_LICENSE("GPL"); |