[mirror_ubuntu-artful-kernel.git] / drivers / idle / intel_idle.c

/*
 * intel_idle.c - native hardware idle loop for modern Intel processors
 *
 * Copyright (c) 2010, Intel Corporation.
 * Len Brown <len.brown@intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 */

/*
 * intel_idle is a cpuidle driver that loads on specific Intel processors
 * in lieu of the legacy ACPI processor_idle driver.  The intent is to
 * make Linux more efficient on these processors, as intel_idle knows
 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
 */

/*
 * Design Assumptions
 *
 * All CPUs have same idle states as boot CPU
 *
 * Chipset BM_STS (bus master status) bit is a NOP
 *	for preventing entry into deep C-stats
 */

/*
 * Known limitations
 *
 * The driver currently initializes for_each_online_cpu() upon modprobe.
 * It it unaware of subsequent processors hot-added to the system.
 * This means that if you boot with maxcpus=n and later online
 * processors above n, those processors will use C1 only.
 *
 * ACPI has a .suspend hack to turn off deep c-statees during suspend
 * to avoid complications with the lapic timer workaround.
 * Have not seen issues with suspend, but may need same workaround here.
 *
 * There is currently no kernel-based automatic probing/loading mechanism
 * if the driver is built as a module.
 */

/* un-comment DEBUG to enable pr_debug() statements */
#define DEBUG

#include <linux/kernel.h>
#include <linux/cpuidle.h>
#include <linux/clockchips.h>
#include <trace/events/power.h>
#include <linux/sched.h>
#include <linux/notifier.h>
#include <linux/cpu.h>
#include <linux/module.h>
#include <asm/cpu_device_id.h>
#include <asm/mwait.h>
#include <asm/msr.h>

#define INTEL_IDLE_VERSION "0.4"
#define PREFIX "intel_idle: "

static struct cpuidle_driver intel_idle_driver = {
	.name = "intel_idle",
	.owner = THIS_MODULE,
	.en_core_tk_irqen = 1,
};
/* intel_idle.max_cstate=0 disables driver */
static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;

static unsigned int mwait_substates;

#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
/* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
static unsigned int lapic_timer_reliable_states = (1 << 1);	 /* Default to only C1 */

struct idle_cpu {
	struct cpuidle_state *state_table;

	/*
	 * Hardware C-state auto-demotion may not always be optimal.
	 * Indicate which enable bits to clear here.
	 */
	unsigned long auto_demotion_disable_flags;
};

static const struct idle_cpu *icpu;
static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
static int intel_idle(struct cpuidle_device *dev,
			struct cpuidle_driver *drv, int index);
static int intel_idle_cpu_init(int cpu);

static struct cpuidle_state *cpuidle_state_table;

/*
 * Set this flag for states where the HW flushes the TLB for us
 * and so we don't need cross-calls to keep it consistent.
 * If this flag is set, SW flushes the TLB, so even if the
 * HW doesn't do the flushing, this flag is safe to use.
 */
#define CPUIDLE_FLAG_TLB_FLUSHED	0x10000

/*
 * States are indexed by the cstate number,
 * which is also the index into the MWAIT hint array.
 * Thus C0 is a dummy.
 */
static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "C1-NHM",
		.desc = "MWAIT 0x00",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 3,
		.target_residency = 6,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "C3-NHM",
		.desc = "MWAIT 0x10",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 20,
		.target_residency = 80,
		.enter = &intel_idle },
	{ /* MWAIT C3 */
		.name = "C6-NHM",
		.desc = "MWAIT 0x20",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 200,
		.target_residency = 800,
		.enter = &intel_idle },
};

static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "C1-SNB",
		.desc = "MWAIT 0x00",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 1,
		.target_residency = 1,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "C3-SNB",
		.desc = "MWAIT 0x10",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 80,
		.target_residency = 211,
		.enter = &intel_idle },
	{ /* MWAIT C3 */
		.name = "C6-SNB",
		.desc = "MWAIT 0x20",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 104,
		.target_residency = 345,
		.enter = &intel_idle },
	{ /* MWAIT C4 */
		.name = "C7-SNB",
		.desc = "MWAIT 0x30",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 109,
		.target_residency = 345,
		.enter = &intel_idle },
};

static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "C1-IVB",
		.desc = "MWAIT 0x00",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 1,
		.target_residency = 1,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "C3-IVB",
		.desc = "MWAIT 0x10",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 59,
		.target_residency = 156,
		.enter = &intel_idle },
	{ /* MWAIT C3 */
		.name = "C6-IVB",
		.desc = "MWAIT 0x20",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 80,
		.target_residency = 300,
		.enter = &intel_idle },
	{ /* MWAIT C4 */
		.name = "C7-IVB",
		.desc = "MWAIT 0x30",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 87,
		.target_residency = 300,
		.enter = &intel_idle },
};

static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
	{ /* MWAIT C0 */ },
	{ /* MWAIT C1 */
		.name = "C1-ATM",
		.desc = "MWAIT 0x00",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 1,
		.target_residency = 4,
		.enter = &intel_idle },
	{ /* MWAIT C2 */
		.name = "C2-ATM",
		.desc = "MWAIT 0x10",
		.flags = CPUIDLE_FLAG_TIME_VALID,
		.exit_latency = 20,
		.target_residency = 80,
		.enter = &intel_idle },
	{ /* MWAIT C3 */ },
	{ /* MWAIT C4 */
		.name = "C4-ATM",
		.desc = "MWAIT 0x30",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 100,
		.target_residency = 400,
		.enter = &intel_idle },
	{ /* MWAIT C5 */ },
	{ /* MWAIT C6 */
		.name = "C6-ATM",
		.desc = "MWAIT 0x52",
		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 140,
		.target_residency = 560,
		.enter = &intel_idle },
};

static long get_driver_data(int cstate)
{
	int driver_data;
	switch (cstate) {

	case 1:	/* MWAIT C1 */
		driver_data = 0x00;
		break;
	case 2:	/* MWAIT C2 */
		driver_data = 0x10;
		break;
	case 3:	/* MWAIT C3 */
		driver_data = 0x20;
		break;
	case 4:	/* MWAIT C4 */
		driver_data = 0x30;
		break;
	case 5:	/* MWAIT C5 */
		driver_data = 0x40;
		break;
	case 6:	/* MWAIT C6 */
		driver_data = 0x52;
		break;
	default:
		driver_data = 0x00;
	}
	return driver_data;
}

/**
 * intel_idle
 * @dev: cpuidle_device
 * @drv: cpuidle driver
 * @index: index of cpuidle state
 *
 * Must be called under local_irq_disable().
 */
static int intel_idle(struct cpuidle_device *dev,
		struct cpuidle_driver *drv, int index)
{
	unsigned long ecx = 1; /* break on interrupt flag */
	struct cpuidle_state *state = &drv->states[index];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
	unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
	unsigned int cstate;
	int cpu = smp_processor_id();

	cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;

	/*
	 * leave_mm() to avoid costly and often unnecessary wakeups
	 * for flushing the user TLB's associated with the active mm.
	 */
	if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
		leave_mm(cpu);

	if (!(lapic_timer_reliable_states & (1 << (cstate))))
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

	stop_critical_timings();
	if (!need_resched()) {

		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__mwait(eax, ecx);
	}

	start_critical_timings();

	if (!(lapic_timer_reliable_states & (1 << (cstate))))
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);

	return index;
}

static void __setup_broadcast_timer(void *arg)
{
	unsigned long reason = (unsigned long)arg;
	int cpu = smp_processor_id();

	reason = reason ?
		CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;

	clockevents_notify(reason, &cpu);
}

static int cpu_hotplug_notify(struct notifier_block *n,
			      unsigned long action, void *hcpu)
{
	int hotcpu = (unsigned long)hcpu;
	struct cpuidle_device *dev;

	switch (action & 0xf) {
	case CPU_ONLINE:

		if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
			smp_call_function_single(hotcpu, __setup_broadcast_timer,
						 (void *)true, 1);

		/*
		 * Some systems can hotplug a cpu at runtime after
		 * the kernel has booted, we have to initialize the
		 * driver in this case
		 */
		dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
		if (!dev->registered)
			intel_idle_cpu_init(hotcpu);

		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block cpu_hotplug_notifier = {
	.notifier_call = cpu_hotplug_notify,
};

static void auto_demotion_disable(void *dummy)
{
	unsigned long long msr_bits;

	rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
	msr_bits &= ~(icpu->auto_demotion_disable_flags);
	wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
}

static const struct idle_cpu idle_cpu_nehalem = {
	.state_table = nehalem_cstates,
	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
};

static const struct idle_cpu idle_cpu_atom = {
	.state_table = atom_cstates,
};

static const struct idle_cpu idle_cpu_lincroft = {
	.state_table = atom_cstates,
	.auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
};

static const struct idle_cpu idle_cpu_snb = {
	.state_table = snb_cstates,
};

static const struct idle_cpu idle_cpu_ivb = {
	.state_table = ivb_cstates,
};

#define ICPU(model, cpu) \
	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }

static const struct x86_cpu_id intel_idle_ids[] = {
	ICPU(0x1a, idle_cpu_nehalem),
	ICPU(0x1e, idle_cpu_nehalem),
	ICPU(0x1f, idle_cpu_nehalem),
	ICPU(0x25, idle_cpu_nehalem),
	ICPU(0x2c, idle_cpu_nehalem),
	ICPU(0x2e, idle_cpu_nehalem),
	ICPU(0x1c, idle_cpu_atom),
	ICPU(0x26, idle_cpu_lincroft),
	ICPU(0x2f, idle_cpu_nehalem),
	ICPU(0x2a, idle_cpu_snb),
	ICPU(0x2d, idle_cpu_snb),
	ICPU(0x3a, idle_cpu_ivb),
	ICPU(0x3e, idle_cpu_ivb),
	{}
};
MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);

/*
 * intel_idle_probe()
 */
static int intel_idle_probe(void)
{
	unsigned int eax, ebx, ecx;
	const struct x86_cpu_id *id;

	if (max_cstate == 0) {
		pr_debug(PREFIX "disabled\n");
		return -EPERM;
	}

	id = x86_match_cpu(intel_idle_ids);
	if (!id) {
		if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
		    boot_cpu_data.x86 == 6)
			pr_debug(PREFIX "does not run on family %d model %d\n",
				boot_cpu_data.x86, boot_cpu_data.x86_model);
		return -ENODEV;
	}

	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
		return -ENODEV;

	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);

	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
	    !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
	    !mwait_substates)
			return -ENODEV;

	pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);

	icpu = (const struct idle_cpu *)id->driver_data;
	cpuidle_state_table = icpu->state_table;

	if (boot_cpu_has(X86_FEATURE_ARAT))	/* Always Reliable APIC Timer */
		lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
	else
		on_each_cpu(__setup_broadcast_timer, (void *)true, 1);

	register_cpu_notifier(&cpu_hotplug_notifier);

	pr_debug(PREFIX "v" INTEL_IDLE_VERSION
		" model 0x%X\n", boot_cpu_data.x86_model);

	pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
		lapic_timer_reliable_states);
	return 0;
}

/*
 * intel_idle_cpuidle_devices_uninit()
 * unregister, free cpuidle_devices
 */
static void intel_idle_cpuidle_devices_uninit(void)
{
	int i;
	struct cpuidle_device *dev;

	for_each_online_cpu(i) {
		dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
		cpuidle_unregister_device(dev);
	}

	free_percpu(intel_idle_cpuidle_devices);
	return;
}
/*
 * intel_idle_cpuidle_driver_init()
 * allocate, initialize cpuidle_states
 */
static int intel_idle_cpuidle_driver_init(void)
{
	int cstate;
	struct cpuidle_driver *drv = &intel_idle_driver;

	drv->state_count = 1;

	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
		int num_substates;

		if (cstate > max_cstate) {
			printk(PREFIX "max_cstate %d reached\n",
				max_cstate);
			break;
		}

		/* does the state exist in CPUID.MWAIT? */
		num_substates = (mwait_substates >> ((cstate) * 4))
					& MWAIT_SUBSTATE_MASK;
		if (num_substates == 0)
			continue;
		/* is the state not enabled? */
		if (cpuidle_state_table[cstate].enter == NULL) {
			/* does the driver not know about the state? */
			if (*cpuidle_state_table[cstate].name == '\0')
				pr_debug(PREFIX "unaware of model 0x%x"
					" MWAIT %d please"
					" contact lenb@kernel.org",
				boot_cpu_data.x86_model, cstate);
			continue;
		}

		if ((cstate > 2) &&
			!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
			mark_tsc_unstable("TSC halts in idle"
					" states deeper than C2");

		drv->states[drv->state_count] =	/* structure copy */
			cpuidle_state_table[cstate];

		drv->state_count += 1;
	}

	if (icpu->auto_demotion_disable_flags)
		on_each_cpu(auto_demotion_disable, NULL, 1);

	return 0;
}


/*
 * intel_idle_cpu_init()
 * allocate, initialize, register cpuidle_devices
 * @cpu: cpu/core to initialize
 */
static int intel_idle_cpu_init(int cpu)
{
	int cstate;
	struct cpuidle_device *dev;

	dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);

	dev->state_count = 1;

	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
		int num_substates;

		if (cstate > max_cstate) {
			printk(PREFIX "max_cstate %d reached\n", max_cstate);
			break;
		}

		/* does the state exist in CPUID.MWAIT? */
		num_substates = (mwait_substates >> ((cstate) * 4))
			& MWAIT_SUBSTATE_MASK;
		if (num_substates == 0)
			continue;
		/* is the state not enabled? */
		if (cpuidle_state_table[cstate].enter == NULL)
			continue;

		dev->states_usage[dev->state_count].driver_data =
			(void *)get_driver_data(cstate);

		dev->state_count += 1;
	}

	dev->cpu = cpu;

	if (cpuidle_register_device(dev)) {
		pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
		intel_idle_cpuidle_devices_uninit();
		return -EIO;
	}

	if (icpu->auto_demotion_disable_flags)
		smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);

	return 0;
}

static int __init intel_idle_init(void)
{
	int retval, i;

	/* Do not load intel_idle at all for now if idle= is passed */
	if (boot_option_idle_override != IDLE_NO_OVERRIDE)
		return -ENODEV;

	retval = intel_idle_probe();
	if (retval)
		return retval;

	intel_idle_cpuidle_driver_init();
	retval = cpuidle_register_driver(&intel_idle_driver);
	if (retval) {
		struct cpuidle_driver *drv = cpuidle_get_driver();
		printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
			drv ? drv->name : "none");
		return retval;
	}

	intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
	if (intel_idle_cpuidle_devices == NULL)
		return -ENOMEM;

	for_each_online_cpu(i) {
		retval = intel_idle_cpu_init(i);
		if (retval) {
			cpuidle_unregister_driver(&intel_idle_driver);
			return retval;
		}
	}

	return 0;
}

static void __exit intel_idle_exit(void)
{
	intel_idle_cpuidle_devices_uninit();
	cpuidle_unregister_driver(&intel_idle_driver);


	if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
		on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
	unregister_cpu_notifier(&cpu_hotplug_notifier);

	return;
}

module_init(intel_idle_init);
module_exit(intel_idle_exit);

module_param(max_cstate, int, 0444);

MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
MODULE_LICENSE("GPL");
Commit	Line	Data
26717172 LB	1	/*
	2	* intel_idle.c - native hardware idle loop for modern Intel processors
	3	*
	4	* Copyright (c) 2010, Intel Corporation.
	5	* Len Brown <len.brown@intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	/*
	22	* intel_idle is a cpuidle driver that loads on specific Intel processors
	23	* in lieu of the legacy ACPI processor_idle driver. The intent is to
	24	* make Linux more efficient on these processors, as intel_idle knows
	25	* more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
	26	*/
	27
	28	/*
	29	* Design Assumptions
	30	*
	31	* All CPUs have same idle states as boot CPU
	32	*
	33	* Chipset BM_STS (bus master status) bit is a NOP
	34	* for preventing entry into deep C-stats
	35	*/
	36
	37	/*
	38	* Known limitations
	39	*
	40	* The driver currently initializes for_each_online_cpu() upon modprobe.
	41	* It it unaware of subsequent processors hot-added to the system.
	42	* This means that if you boot with maxcpus=n and later online
	43	* processors above n, those processors will use C1 only.
	44	*
	45	* ACPI has a .suspend hack to turn off deep c-statees during suspend
	46	* to avoid complications with the lapic timer workaround.
	47	* Have not seen issues with suspend, but may need same workaround here.
	48	*
	49	* There is currently no kernel-based automatic probing/loading mechanism
	50	* if the driver is built as a module.
	51	*/
	52
	53	/* un-comment DEBUG to enable pr_debug() statements */
	54	#define DEBUG
	55
	56	#include <linux/kernel.h>
	57	#include <linux/cpuidle.h>
	58	#include <linux/clockchips.h>
26717172 LB	59	#include <trace/events/power.h>
26717172 LB	60	#include <linux/sched.h>
2a2d31c8 SL	61	#include <linux/notifier.h>
2a2d31c8 SL	62	#include <linux/cpu.h>
7c52d551	63	#include <linux/module.h>
b66b8b9a	64	#include <asm/cpu_device_id.h>
bc83cccc	65	#include <asm/mwait.h>
14796fca	66	#include <asm/msr.h>
26717172 LB	67
	68	#define INTEL_IDLE_VERSION "0.4"
	69	#define PREFIX "intel_idle: "
	70
26717172 LB	71	static struct cpuidle_driver intel_idle_driver = {
	72	.name = "intel_idle",
	73	.owner = THIS_MODULE,
a474a515	74	.en_core_tk_irqen = 1,
26717172 LB	75	};
	76	/* intel_idle.max_cstate=0 disables driver */
	77	static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
26717172	78
c4236282	79	static unsigned int mwait_substates;
26717172	80
2a2d31c8	81	#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
26717172	82	/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
d13780d4	83	static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
26717172	84
b66b8b9a AK	85	struct idle_cpu {
	86	struct cpuidle_state *state_table;
	87
	88	/*
	89	* Hardware C-state auto-demotion may not always be optimal.
	90	* Indicate which enable bits to clear here.
	91	*/
	92	unsigned long auto_demotion_disable_flags;
	93	};
	94
	95	static const struct idle_cpu *icpu;
3265eba0	96	static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
46bcfad7 DD	97	static int intel_idle(struct cpuidle_device *dev,
46bcfad7 DD	98	struct cpuidle_driver *drv, int index);
25ac7761	99	static int intel_idle_cpu_init(int cpu);
26717172 LB	100
	101	static struct cpuidle_state *cpuidle_state_table;
	102
956d033f LB	103	/*
	104	* Set this flag for states where the HW flushes the TLB for us
	105	* and so we don't need cross-calls to keep it consistent.
	106	* If this flag is set, SW flushes the TLB, so even if the
	107	* HW doesn't do the flushing, this flag is safe to use.
	108	*/
	109	#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
	110
26717172 LB	111	/*
	112	* States are indexed by the cstate number,
	113	* which is also the index into the MWAIT hint array.
	114	* Thus C0 is a dummy.
	115	*/
	116	static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
	117	{ /* MWAIT C0 */ },
	118	{ /* MWAIT C1 */
15e123e5	119	.name = "C1-NHM",
26717172	120	.desc = "MWAIT 0x00",
26717172 LB	121	.flags = CPUIDLE_FLAG_TIME_VALID,
26717172 LB	122	.exit_latency = 3,
26717172 LB	123	.target_residency = 6,
	124	.enter = &intel_idle },
	125	{ /* MWAIT C2 */
15e123e5	126	.name = "C3-NHM",
26717172	127	.desc = "MWAIT 0x10",
6110a1f4	128	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	129	.exit_latency = 20,
26717172 LB	130	.target_residency = 80,
	131	.enter = &intel_idle },
	132	{ /* MWAIT C3 */
15e123e5	133	.name = "C6-NHM",
26717172	134	.desc = "MWAIT 0x20",
6110a1f4	135	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	136	.exit_latency = 200,
26717172 LB	137	.target_residency = 800,
	138	.enter = &intel_idle },
	139	};
	140
d13780d4 LB	141	static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	142	{ /* MWAIT C0 */ },
	143	{ /* MWAIT C1 */
15e123e5	144	.name = "C1-SNB",
d13780d4	145	.desc = "MWAIT 0x00",
d13780d4 LB	146	.flags = CPUIDLE_FLAG_TIME_VALID,
d13780d4 LB	147	.exit_latency = 1,
ddbd550d	148	.target_residency = 1,
d13780d4 LB	149	.enter = &intel_idle },
d13780d4 LB	150	{ /* MWAIT C2 */
15e123e5	151	.name = "C3-SNB",
d13780d4	152	.desc = "MWAIT 0x10",
00527cc6	153	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	154	.exit_latency = 80,
ddbd550d	155	.target_residency = 211,
d13780d4 LB	156	.enter = &intel_idle },
d13780d4 LB	157	{ /* MWAIT C3 */
15e123e5	158	.name = "C6-SNB",
d13780d4	159	.desc = "MWAIT 0x20",
00527cc6	160	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	161	.exit_latency = 104,
ddbd550d	162	.target_residency = 345,
d13780d4 LB	163	.enter = &intel_idle },
d13780d4 LB	164	{ /* MWAIT C4 */
15e123e5	165	.name = "C7-SNB",
d13780d4	166	.desc = "MWAIT 0x30",
00527cc6	167	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4	168	.exit_latency = 109,
ddbd550d	169	.target_residency = 345,
d13780d4 LB	170	.enter = &intel_idle },
	171	};
	172
6edab08c LB	173	static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
	174	{ /* MWAIT C0 */ },
	175	{ /* MWAIT C1 */
	176	.name = "C1-IVB",
	177	.desc = "MWAIT 0x00",
	178	.flags = CPUIDLE_FLAG_TIME_VALID,
	179	.exit_latency = 1,
	180	.target_residency = 1,
	181	.enter = &intel_idle },
	182	{ /* MWAIT C2 */
	183	.name = "C3-IVB",
	184	.desc = "MWAIT 0x10",
	185	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
	186	.exit_latency = 59,
	187	.target_residency = 156,
	188	.enter = &intel_idle },
	189	{ /* MWAIT C3 */
	190	.name = "C6-IVB",
	191	.desc = "MWAIT 0x20",
	192	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
	193	.exit_latency = 80,
	194	.target_residency = 300,
	195	.enter = &intel_idle },
	196	{ /* MWAIT C4 */
	197	.name = "C7-IVB",
	198	.desc = "MWAIT 0x30",
	199	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
	200	.exit_latency = 87,
	201	.target_residency = 300,
	202	.enter = &intel_idle },
	203	};
	204
26717172 LB	205	static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
	206	{ /* MWAIT C0 */ },
	207	{ /* MWAIT C1 */
15e123e5	208	.name = "C1-ATM",
26717172	209	.desc = "MWAIT 0x00",
26717172 LB	210	.flags = CPUIDLE_FLAG_TIME_VALID,
26717172 LB	211	.exit_latency = 1,
26717172 LB	212	.target_residency = 4,
	213	.enter = &intel_idle },
	214	{ /* MWAIT C2 */
15e123e5	215	.name = "C2-ATM",
26717172	216	.desc = "MWAIT 0x10",
26717172 LB	217	.flags = CPUIDLE_FLAG_TIME_VALID,
26717172 LB	218	.exit_latency = 20,
26717172 LB	219	.target_residency = 80,
	220	.enter = &intel_idle },
	221	{ /* MWAIT C3 */ },
	222	{ /* MWAIT C4 */
15e123e5	223	.name = "C4-ATM",
26717172	224	.desc = "MWAIT 0x30",
6110a1f4	225	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
26717172	226	.exit_latency = 100,
26717172 LB	227	.target_residency = 400,
	228	.enter = &intel_idle },
	229	{ /* MWAIT C5 */ },
	230	{ /* MWAIT C6 */
15e123e5	231	.name = "C6-ATM",
7fcca7d9	232	.desc = "MWAIT 0x52",
6110a1f4	233	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_TLB_FLUSHED,
7fcca7d9	234	.exit_latency = 140,
7fcca7d9 LB	235	.target_residency = 560,
7fcca7d9 LB	236	.enter = &intel_idle },
26717172 LB	237	};
26717172 LB	238
95e3ec11	239	static long get_driver_data(int cstate)
4202735e DD	240	{
	241	int driver_data;
	242	switch (cstate) {
	243
	244	case 1: /* MWAIT C1 */
	245	driver_data = 0x00;
	246	break;
	247	case 2: /* MWAIT C2 */
	248	driver_data = 0x10;
	249	break;
	250	case 3: /* MWAIT C3 */
	251	driver_data = 0x20;
	252	break;
	253	case 4: /* MWAIT C4 */
	254	driver_data = 0x30;
	255	break;
	256	case 5: /* MWAIT C5 */
	257	driver_data = 0x40;
	258	break;
	259	case 6: /* MWAIT C6 */
	260	driver_data = 0x52;
	261	break;
	262	default:
	263	driver_data = 0x00;
	264	}
	265	return driver_data;
	266	}
	267
26717172 LB	268	/**
	269	* intel_idle
	270	* @dev: cpuidle_device
46bcfad7	271	* @drv: cpuidle driver
e978aa7d	272	* @index: index of cpuidle state
26717172	273	*
63ff07be	274	* Must be called under local_irq_disable().
26717172	275	*/
46bcfad7 DD	276	static int intel_idle(struct cpuidle_device *dev,
46bcfad7 DD	277	struct cpuidle_driver *drv, int index)
26717172 LB	278	{
26717172 LB	279	unsigned long ecx = 1; /* break on interrupt flag */
46bcfad7	280	struct cpuidle_state *state = &drv->states[index];
4202735e DD	281	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
4202735e DD	282	unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
26717172	283	unsigned int cstate;
26717172 LB	284	int cpu = smp_processor_id();
	285
	286	cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
	287
6110a1f4	288	/*
c8381cc3 LB	289	* leave_mm() to avoid costly and often unnecessary wakeups
c8381cc3 LB	290	* for flushing the user TLB's associated with the active mm.
6110a1f4	291	*/
c8381cc3	292	if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
6110a1f4 SS	293	leave_mm(cpu);
6110a1f4 SS	294
26717172 LB	295	if (!(lapic_timer_reliable_states & (1 << (cstate))))
	296	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
	297
26717172	298	stop_critical_timings();
26717172 LB	299	if (!need_resched()) {
	300
	301	__monitor((void *)&current_thread_info()->flags, 0, 0);
	302	smp_mb();
	303	if (!need_resched())
	304	__mwait(eax, ecx);
	305	}
	306
	307	start_critical_timings();
	308
26717172 LB	309	if (!(lapic_timer_reliable_states & (1 << (cstate))))
	310	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	311
e978aa7d	312	return index;
26717172 LB	313	}
26717172 LB	314
2a2d31c8 SL	315	static void __setup_broadcast_timer(void *arg)
	316	{
	317	unsigned long reason = (unsigned long)arg;
	318	int cpu = smp_processor_id();
	319
	320	reason = reason ?
	321	CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
	322
	323	clockevents_notify(reason, &cpu);
	324	}
	325
25ac7761 DL	326	static int cpu_hotplug_notify(struct notifier_block *n,
25ac7761 DL	327	unsigned long action, void *hcpu)
2a2d31c8 SL	328	{
2a2d31c8 SL	329	int hotcpu = (unsigned long)hcpu;
25ac7761	330	struct cpuidle_device *dev;
2a2d31c8 SL	331
	332	switch (action & 0xf) {
	333	case CPU_ONLINE:
25ac7761 DL	334
	335	if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
	336	smp_call_function_single(hotcpu, __setup_broadcast_timer,
	337	(void *)true, 1);
	338
	339	/*
	340	* Some systems can hotplug a cpu at runtime after
	341	* the kernel has booted, we have to initialize the
	342	* driver in this case
	343	*/
	344	dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
	345	if (!dev->registered)
	346	intel_idle_cpu_init(hotcpu);
	347
2a2d31c8	348	break;
2a2d31c8 SL	349	}
	350	return NOTIFY_OK;
	351	}
	352
25ac7761 DL	353	static struct notifier_block cpu_hotplug_notifier = {
25ac7761 DL	354	.notifier_call = cpu_hotplug_notify,
2a2d31c8 SL	355	};
2a2d31c8 SL	356
14796fca LB	357	static void auto_demotion_disable(void *dummy)
	358	{
	359	unsigned long long msr_bits;
	360
	361	rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
b66b8b9a	362	msr_bits &= ~(icpu->auto_demotion_disable_flags);
14796fca LB	363	wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
	364	}
	365
b66b8b9a AK	366	static const struct idle_cpu idle_cpu_nehalem = {
b66b8b9a AK	367	.state_table = nehalem_cstates,
b66b8b9a AK	368	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE \| NHM_C3_AUTO_DEMOTE,
	369	};
	370
	371	static const struct idle_cpu idle_cpu_atom = {
	372	.state_table = atom_cstates,
	373	};
	374
	375	static const struct idle_cpu idle_cpu_lincroft = {
	376	.state_table = atom_cstates,
	377	.auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
	378	};
	379
	380	static const struct idle_cpu idle_cpu_snb = {
	381	.state_table = snb_cstates,
	382	};
	383
6edab08c LB	384	static const struct idle_cpu idle_cpu_ivb = {
	385	.state_table = ivb_cstates,
	386	};
	387
b66b8b9a AK	388	#define ICPU(model, cpu) \
	389	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
	390
	391	static const struct x86_cpu_id intel_idle_ids[] = {
	392	ICPU(0x1a, idle_cpu_nehalem),
	393	ICPU(0x1e, idle_cpu_nehalem),
	394	ICPU(0x1f, idle_cpu_nehalem),
8bf11938 BH	395	ICPU(0x25, idle_cpu_nehalem),
	396	ICPU(0x2c, idle_cpu_nehalem),
	397	ICPU(0x2e, idle_cpu_nehalem),
b66b8b9a AK	398	ICPU(0x1c, idle_cpu_atom),
b66b8b9a AK	399	ICPU(0x26, idle_cpu_lincroft),
8bf11938	400	ICPU(0x2f, idle_cpu_nehalem),
b66b8b9a AK	401	ICPU(0x2a, idle_cpu_snb),
b66b8b9a AK	402	ICPU(0x2d, idle_cpu_snb),
6edab08c	403	ICPU(0x3a, idle_cpu_ivb),
23795e58	404	ICPU(0x3e, idle_cpu_ivb),
b66b8b9a AK	405	{}
	406	};
	407	MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
	408
26717172 LB	409	/*
	410	* intel_idle_probe()
	411	*/
	412	static int intel_idle_probe(void)
	413	{
c4236282	414	unsigned int eax, ebx, ecx;
b66b8b9a	415	const struct x86_cpu_id *id;
26717172 LB	416
	417	if (max_cstate == 0) {
	418	pr_debug(PREFIX "disabled\n");
	419	return -EPERM;
	420	}
	421
b66b8b9a AK	422	id = x86_match_cpu(intel_idle_ids);
	423	if (!id) {
	424	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	425	boot_cpu_data.x86 == 6)
	426	pr_debug(PREFIX "does not run on family %d model %d\n",
	427	boot_cpu_data.x86, boot_cpu_data.x86_model);
26717172	428	return -ENODEV;
b66b8b9a	429	}
26717172 LB	430
	431	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
	432	return -ENODEV;
	433
c4236282	434	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
26717172 LB	435
26717172 LB	436	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) \|\|
5c2a9f06 TR	437	!(ecx & CPUID5_ECX_INTERRUPT_BREAK) \|\|
5c2a9f06 TR	438	!mwait_substates)
26717172	439	return -ENODEV;
26717172	440
c4236282	441	pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
26717172	442
b66b8b9a AK	443	icpu = (const struct idle_cpu *)id->driver_data;
b66b8b9a AK	444	cpuidle_state_table = icpu->state_table;
26717172	445
56b9aea3	446	if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
2a2d31c8	447	lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
25ac7761	448	else
39a74fde	449	on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
25ac7761 DL	450
25ac7761 DL	451	register_cpu_notifier(&cpu_hotplug_notifier);
56b9aea3	452
26717172 LB	453	pr_debug(PREFIX "v" INTEL_IDLE_VERSION
	454	" model 0x%X\n", boot_cpu_data.x86_model);
	455
	456	pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
	457	lapic_timer_reliable_states);
	458	return 0;
	459	}
	460
	461	/*
	462	* intel_idle_cpuidle_devices_uninit()
	463	* unregister, free cpuidle_devices
	464	*/
	465	static void intel_idle_cpuidle_devices_uninit(void)
	466	{
	467	int i;
	468	struct cpuidle_device *dev;
	469
	470	for_each_online_cpu(i) {
	471	dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
	472	cpuidle_unregister_device(dev);
	473	}
	474
	475	free_percpu(intel_idle_cpuidle_devices);
	476	return;
	477	}
46bcfad7 DD	478	/*
	479	* intel_idle_cpuidle_driver_init()
	480	* allocate, initialize cpuidle_states
	481	*/
	482	static int intel_idle_cpuidle_driver_init(void)
	483	{
	484	int cstate;
	485	struct cpuidle_driver *drv = &intel_idle_driver;
	486
	487	drv->state_count = 1;
	488
	489	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
	490	int num_substates;
	491
	492	if (cstate > max_cstate) {
	493	printk(PREFIX "max_cstate %d reached\n",
	494	max_cstate);
	495	break;
	496	}
	497
	498	/* does the state exist in CPUID.MWAIT? */
	499	num_substates = (mwait_substates >> ((cstate) * 4))
	500	& MWAIT_SUBSTATE_MASK;
	501	if (num_substates == 0)
	502	continue;
	503	/* is the state not enabled? */
	504	if (cpuidle_state_table[cstate].enter == NULL) {
	505	/* does the driver not know about the state? */
	506	if (*cpuidle_state_table[cstate].name == '\0')
	507	pr_debug(PREFIX "unaware of model 0x%x"
	508	" MWAIT %d please"
	509	" contact lenb@kernel.org",
	510	boot_cpu_data.x86_model, cstate);
	511	continue;
	512	}
	513
	514	if ((cstate > 2) &&
	515	!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
	516	mark_tsc_unstable("TSC halts in idle"
	517	" states deeper than C2");
	518
	519	drv->states[drv->state_count] = /* structure copy */
	520	cpuidle_state_table[cstate];
	521
	522	drv->state_count += 1;
	523	}
	524
b66b8b9a	525	if (icpu->auto_demotion_disable_flags)
39a74fde	526	on_each_cpu(auto_demotion_disable, NULL, 1);
46bcfad7 DD	527
	528	return 0;
	529	}
	530
	531
26717172	532	/*
65b7f839	533	* intel_idle_cpu_init()
26717172	534	* allocate, initialize, register cpuidle_devices
65b7f839	535	* @cpu: cpu/core to initialize
26717172	536	*/
25ac7761	537	static int intel_idle_cpu_init(int cpu)
26717172	538	{
65b7f839	539	int cstate;
26717172 LB	540	struct cpuidle_device *dev;
26717172 LB	541
65b7f839	542	dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
26717172	543
65b7f839	544	dev->state_count = 1;
26717172	545
65b7f839 TR	546	for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
65b7f839 TR	547	int num_substates;
26717172	548
65b7f839	549	if (cstate > max_cstate) {
dc716e96	550	printk(PREFIX "max_cstate %d reached\n", max_cstate);
65b7f839 TR	551	break;
65b7f839 TR	552	}
26717172	553
65b7f839 TR	554	/* does the state exist in CPUID.MWAIT? */
	555	num_substates = (mwait_substates >> ((cstate) * 4))
	556	& MWAIT_SUBSTATE_MASK;
	557	if (num_substates == 0)
	558	continue;
	559	/* is the state not enabled? */
	560	if (cpuidle_state_table[cstate].enter == NULL)
	561	continue;
26717172	562
65b7f839 TR	563	dev->states_usage[dev->state_count].driver_data =
65b7f839 TR	564	(void *)get_driver_data(cstate);
26717172	565
dc716e96 MPS	566	dev->state_count += 1;
	567	}
	568
65b7f839	569	dev->cpu = cpu;
26717172	570
65b7f839 TR	571	if (cpuidle_register_device(dev)) {
	572	pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
	573	intel_idle_cpuidle_devices_uninit();
	574	return -EIO;
26717172 LB	575	}
26717172 LB	576
b66b8b9a	577	if (icpu->auto_demotion_disable_flags)
65b7f839 TR	578	smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
65b7f839 TR	579
26717172 LB	580	return 0;
26717172 LB	581	}
26717172 LB	582
	583	static int __init intel_idle_init(void)
	584	{
65b7f839	585	int retval, i;
26717172	586
d1896049 TR	587	/* Do not load intel_idle at all for now if idle= is passed */
	588	if (boot_option_idle_override != IDLE_NO_OVERRIDE)
	589	return -ENODEV;
	590
26717172 LB	591	retval = intel_idle_probe();
	592	if (retval)
	593	return retval;
	594
46bcfad7	595	intel_idle_cpuidle_driver_init();
26717172 LB	596	retval = cpuidle_register_driver(&intel_idle_driver);
26717172 LB	597	if (retval) {
3735d524	598	struct cpuidle_driver *drv = cpuidle_get_driver();
26717172	599	printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
3735d524	600	drv ? drv->name : "none");
26717172 LB	601	return retval;
	602	}
	603
65b7f839 TR	604	intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
	605	if (intel_idle_cpuidle_devices == NULL)
	606	return -ENOMEM;
	607
	608	for_each_online_cpu(i) {
	609	retval = intel_idle_cpu_init(i);
	610	if (retval) {
	611	cpuidle_unregister_driver(&intel_idle_driver);
	612	return retval;
	613	}
26717172 LB	614	}
	615
	616	return 0;
	617	}
	618
	619	static void __exit intel_idle_exit(void)
	620	{
	621	intel_idle_cpuidle_devices_uninit();
	622	cpuidle_unregister_driver(&intel_idle_driver);
	623
25ac7761 DL	624
25ac7761 DL	625	if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
39a74fde	626	on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
25ac7761	627	unregister_cpu_notifier(&cpu_hotplug_notifier);
2a2d31c8	628
26717172 LB	629	return;
	630	}
	631
	632	module_init(intel_idle_init);
	633	module_exit(intel_idle_exit);
	634
26717172	635	module_param(max_cstate, int, 0444);
26717172 LB	636
	637	MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
	638	MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
	639	MODULE_LICENSE("GPL");