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26717172 LB |
1 | /* |
2 | * intel_idle.c - native hardware idle loop for modern Intel processors | |
3 | * | |
fab04b22 | 4 | * Copyright (c) 2013, Intel Corporation. |
26717172 LB |
5 | * Len Brown <len.brown@intel.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * intel_idle is a cpuidle driver that loads on specific Intel processors | |
23 | * in lieu of the legacy ACPI processor_idle driver. The intent is to | |
24 | * make Linux more efficient on these processors, as intel_idle knows | |
25 | * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Design Assumptions | |
30 | * | |
31 | * All CPUs have same idle states as boot CPU | |
32 | * | |
33 | * Chipset BM_STS (bus master status) bit is a NOP | |
34 | * for preventing entry into deep C-stats | |
35 | */ | |
36 | ||
37 | /* | |
38 | * Known limitations | |
39 | * | |
40 | * The driver currently initializes for_each_online_cpu() upon modprobe. | |
41 | * It it unaware of subsequent processors hot-added to the system. | |
42 | * This means that if you boot with maxcpus=n and later online | |
43 | * processors above n, those processors will use C1 only. | |
44 | * | |
45 | * ACPI has a .suspend hack to turn off deep c-statees during suspend | |
46 | * to avoid complications with the lapic timer workaround. | |
47 | * Have not seen issues with suspend, but may need same workaround here. | |
48 | * | |
49 | * There is currently no kernel-based automatic probing/loading mechanism | |
50 | * if the driver is built as a module. | |
51 | */ | |
52 | ||
53 | /* un-comment DEBUG to enable pr_debug() statements */ | |
54 | #define DEBUG | |
55 | ||
56 | #include <linux/kernel.h> | |
57 | #include <linux/cpuidle.h> | |
58 | #include <linux/clockchips.h> | |
26717172 LB |
59 | #include <trace/events/power.h> |
60 | #include <linux/sched.h> | |
2a2d31c8 SL |
61 | #include <linux/notifier.h> |
62 | #include <linux/cpu.h> | |
7c52d551 | 63 | #include <linux/module.h> |
b66b8b9a | 64 | #include <asm/cpu_device_id.h> |
bc83cccc | 65 | #include <asm/mwait.h> |
14796fca | 66 | #include <asm/msr.h> |
26717172 LB |
67 | |
68 | #define INTEL_IDLE_VERSION "0.4" | |
69 | #define PREFIX "intel_idle: " | |
70 | ||
26717172 LB |
71 | static struct cpuidle_driver intel_idle_driver = { |
72 | .name = "intel_idle", | |
73 | .owner = THIS_MODULE, | |
74 | }; | |
75 | /* intel_idle.max_cstate=0 disables driver */ | |
137ecc77 | 76 | static int max_cstate = CPUIDLE_STATE_MAX - 1; |
26717172 | 77 | |
c4236282 | 78 | static unsigned int mwait_substates; |
26717172 | 79 | |
2a2d31c8 | 80 | #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF |
26717172 | 81 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ |
d13780d4 | 82 | static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ |
26717172 | 83 | |
b66b8b9a AK |
84 | struct idle_cpu { |
85 | struct cpuidle_state *state_table; | |
86 | ||
87 | /* | |
88 | * Hardware C-state auto-demotion may not always be optimal. | |
89 | * Indicate which enable bits to clear here. | |
90 | */ | |
91 | unsigned long auto_demotion_disable_flags; | |
8c058d53 | 92 | bool byt_auto_demotion_disable_flag; |
32e95180 | 93 | bool disable_promotion_to_c1e; |
b66b8b9a AK |
94 | }; |
95 | ||
96 | static const struct idle_cpu *icpu; | |
3265eba0 | 97 | static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; |
46bcfad7 DD |
98 | static int intel_idle(struct cpuidle_device *dev, |
99 | struct cpuidle_driver *drv, int index); | |
5fe2e527 RW |
100 | static void intel_idle_freeze(struct cpuidle_device *dev, |
101 | struct cpuidle_driver *drv, int index); | |
25ac7761 | 102 | static int intel_idle_cpu_init(int cpu); |
26717172 LB |
103 | |
104 | static struct cpuidle_state *cpuidle_state_table; | |
105 | ||
956d033f LB |
106 | /* |
107 | * Set this flag for states where the HW flushes the TLB for us | |
108 | * and so we don't need cross-calls to keep it consistent. | |
109 | * If this flag is set, SW flushes the TLB, so even if the | |
110 | * HW doesn't do the flushing, this flag is safe to use. | |
111 | */ | |
112 | #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 | |
113 | ||
b1beab48 LB |
114 | /* |
115 | * MWAIT takes an 8-bit "hint" in EAX "suggesting" | |
116 | * the C-state (top nibble) and sub-state (bottom nibble) | |
117 | * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. | |
118 | * | |
119 | * We store the hint at the top of our "flags" for each state. | |
120 | */ | |
121 | #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF) | |
122 | #define MWAIT2flg(eax) ((eax & 0xFF) << 24) | |
123 | ||
26717172 LB |
124 | /* |
125 | * States are indexed by the cstate number, | |
126 | * which is also the index into the MWAIT hint array. | |
127 | * Thus C0 is a dummy. | |
128 | */ | |
ba0dc81e | 129 | static struct cpuidle_state nehalem_cstates[] = { |
e022e7eb | 130 | { |
15e123e5 | 131 | .name = "C1-NHM", |
26717172 | 132 | .desc = "MWAIT 0x00", |
b82b6cca | 133 | .flags = MWAIT2flg(0x00), |
26717172 | 134 | .exit_latency = 3, |
26717172 | 135 | .target_residency = 6, |
5fe2e527 RW |
136 | .enter = &intel_idle, |
137 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 LB |
138 | { |
139 | .name = "C1E-NHM", | |
140 | .desc = "MWAIT 0x01", | |
b82b6cca | 141 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
142 | .exit_latency = 10, |
143 | .target_residency = 20, | |
5fe2e527 RW |
144 | .enter = &intel_idle, |
145 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 146 | { |
15e123e5 | 147 | .name = "C3-NHM", |
26717172 | 148 | .desc = "MWAIT 0x10", |
b82b6cca | 149 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 150 | .exit_latency = 20, |
26717172 | 151 | .target_residency = 80, |
5fe2e527 RW |
152 | .enter = &intel_idle, |
153 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 154 | { |
15e123e5 | 155 | .name = "C6-NHM", |
26717172 | 156 | .desc = "MWAIT 0x20", |
b82b6cca | 157 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 158 | .exit_latency = 200, |
26717172 | 159 | .target_residency = 800, |
5fe2e527 RW |
160 | .enter = &intel_idle, |
161 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
162 | { |
163 | .enter = NULL } | |
26717172 LB |
164 | }; |
165 | ||
ba0dc81e | 166 | static struct cpuidle_state snb_cstates[] = { |
e022e7eb | 167 | { |
15e123e5 | 168 | .name = "C1-SNB", |
d13780d4 | 169 | .desc = "MWAIT 0x00", |
b82b6cca | 170 | .flags = MWAIT2flg(0x00), |
32e95180 LB |
171 | .exit_latency = 2, |
172 | .target_residency = 2, | |
5fe2e527 RW |
173 | .enter = &intel_idle, |
174 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 LB |
175 | { |
176 | .name = "C1E-SNB", | |
177 | .desc = "MWAIT 0x01", | |
b82b6cca | 178 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
179 | .exit_latency = 10, |
180 | .target_residency = 20, | |
5fe2e527 RW |
181 | .enter = &intel_idle, |
182 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 183 | { |
15e123e5 | 184 | .name = "C3-SNB", |
d13780d4 | 185 | .desc = "MWAIT 0x10", |
b82b6cca | 186 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 187 | .exit_latency = 80, |
ddbd550d | 188 | .target_residency = 211, |
5fe2e527 RW |
189 | .enter = &intel_idle, |
190 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 191 | { |
15e123e5 | 192 | .name = "C6-SNB", |
d13780d4 | 193 | .desc = "MWAIT 0x20", |
b82b6cca | 194 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 195 | .exit_latency = 104, |
ddbd550d | 196 | .target_residency = 345, |
5fe2e527 RW |
197 | .enter = &intel_idle, |
198 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 199 | { |
15e123e5 | 200 | .name = "C7-SNB", |
d13780d4 | 201 | .desc = "MWAIT 0x30", |
b82b6cca | 202 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 203 | .exit_latency = 109, |
ddbd550d | 204 | .target_residency = 345, |
5fe2e527 RW |
205 | .enter = &intel_idle, |
206 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
207 | { |
208 | .enter = NULL } | |
d13780d4 LB |
209 | }; |
210 | ||
718987d6 LB |
211 | static struct cpuidle_state byt_cstates[] = { |
212 | { | |
213 | .name = "C1-BYT", | |
214 | .desc = "MWAIT 0x00", | |
b82b6cca | 215 | .flags = MWAIT2flg(0x00), |
718987d6 LB |
216 | .exit_latency = 1, |
217 | .target_residency = 1, | |
5fe2e527 RW |
218 | .enter = &intel_idle, |
219 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
220 | { |
221 | .name = "C1E-BYT", | |
222 | .desc = "MWAIT 0x01", | |
b82b6cca | 223 | .flags = MWAIT2flg(0x01), |
718987d6 LB |
224 | .exit_latency = 15, |
225 | .target_residency = 30, | |
5fe2e527 RW |
226 | .enter = &intel_idle, |
227 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
228 | { |
229 | .name = "C6N-BYT", | |
230 | .desc = "MWAIT 0x58", | |
b82b6cca | 231 | .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, |
718987d6 LB |
232 | .exit_latency = 40, |
233 | .target_residency = 275, | |
5fe2e527 RW |
234 | .enter = &intel_idle, |
235 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
236 | { |
237 | .name = "C6S-BYT", | |
238 | .desc = "MWAIT 0x52", | |
b82b6cca | 239 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, |
718987d6 LB |
240 | .exit_latency = 140, |
241 | .target_residency = 560, | |
5fe2e527 RW |
242 | .enter = &intel_idle, |
243 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
244 | { |
245 | .name = "C7-BYT", | |
246 | .desc = "MWAIT 0x60", | |
b82b6cca | 247 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
718987d6 LB |
248 | .exit_latency = 1200, |
249 | .target_residency = 1500, | |
5fe2e527 RW |
250 | .enter = &intel_idle, |
251 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
252 | { |
253 | .name = "C7S-BYT", | |
254 | .desc = "MWAIT 0x64", | |
b82b6cca | 255 | .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, |
718987d6 LB |
256 | .exit_latency = 10000, |
257 | .target_residency = 20000, | |
5fe2e527 RW |
258 | .enter = &intel_idle, |
259 | .enter_freeze = intel_idle_freeze, }, | |
718987d6 LB |
260 | { |
261 | .enter = NULL } | |
262 | }; | |
263 | ||
ba0dc81e | 264 | static struct cpuidle_state ivb_cstates[] = { |
e022e7eb | 265 | { |
6edab08c LB |
266 | .name = "C1-IVB", |
267 | .desc = "MWAIT 0x00", | |
b82b6cca | 268 | .flags = MWAIT2flg(0x00), |
6edab08c LB |
269 | .exit_latency = 1, |
270 | .target_residency = 1, | |
5fe2e527 RW |
271 | .enter = &intel_idle, |
272 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 LB |
273 | { |
274 | .name = "C1E-IVB", | |
275 | .desc = "MWAIT 0x01", | |
b82b6cca | 276 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
277 | .exit_latency = 10, |
278 | .target_residency = 20, | |
5fe2e527 RW |
279 | .enter = &intel_idle, |
280 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 281 | { |
6edab08c LB |
282 | .name = "C3-IVB", |
283 | .desc = "MWAIT 0x10", | |
b82b6cca | 284 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
285 | .exit_latency = 59, |
286 | .target_residency = 156, | |
5fe2e527 RW |
287 | .enter = &intel_idle, |
288 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 289 | { |
6edab08c LB |
290 | .name = "C6-IVB", |
291 | .desc = "MWAIT 0x20", | |
b82b6cca | 292 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
293 | .exit_latency = 80, |
294 | .target_residency = 300, | |
5fe2e527 RW |
295 | .enter = &intel_idle, |
296 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 297 | { |
6edab08c LB |
298 | .name = "C7-IVB", |
299 | .desc = "MWAIT 0x30", | |
b82b6cca | 300 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
301 | .exit_latency = 87, |
302 | .target_residency = 300, | |
5fe2e527 RW |
303 | .enter = &intel_idle, |
304 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
305 | { |
306 | .enter = NULL } | |
6edab08c LB |
307 | }; |
308 | ||
0138d8f0 LB |
309 | static struct cpuidle_state ivt_cstates[] = { |
310 | { | |
311 | .name = "C1-IVT", | |
312 | .desc = "MWAIT 0x00", | |
b82b6cca | 313 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
314 | .exit_latency = 1, |
315 | .target_residency = 1, | |
5fe2e527 RW |
316 | .enter = &intel_idle, |
317 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
318 | { |
319 | .name = "C1E-IVT", | |
320 | .desc = "MWAIT 0x01", | |
b82b6cca | 321 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
322 | .exit_latency = 10, |
323 | .target_residency = 80, | |
5fe2e527 RW |
324 | .enter = &intel_idle, |
325 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
326 | { |
327 | .name = "C3-IVT", | |
328 | .desc = "MWAIT 0x10", | |
b82b6cca | 329 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
330 | .exit_latency = 59, |
331 | .target_residency = 156, | |
5fe2e527 RW |
332 | .enter = &intel_idle, |
333 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
334 | { |
335 | .name = "C6-IVT", | |
336 | .desc = "MWAIT 0x20", | |
b82b6cca | 337 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
338 | .exit_latency = 82, |
339 | .target_residency = 300, | |
5fe2e527 RW |
340 | .enter = &intel_idle, |
341 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
342 | { |
343 | .enter = NULL } | |
344 | }; | |
345 | ||
346 | static struct cpuidle_state ivt_cstates_4s[] = { | |
347 | { | |
348 | .name = "C1-IVT-4S", | |
349 | .desc = "MWAIT 0x00", | |
b82b6cca | 350 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
351 | .exit_latency = 1, |
352 | .target_residency = 1, | |
5fe2e527 RW |
353 | .enter = &intel_idle, |
354 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
355 | { |
356 | .name = "C1E-IVT-4S", | |
357 | .desc = "MWAIT 0x01", | |
b82b6cca | 358 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
359 | .exit_latency = 10, |
360 | .target_residency = 250, | |
5fe2e527 RW |
361 | .enter = &intel_idle, |
362 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
363 | { |
364 | .name = "C3-IVT-4S", | |
365 | .desc = "MWAIT 0x10", | |
b82b6cca | 366 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
367 | .exit_latency = 59, |
368 | .target_residency = 300, | |
5fe2e527 RW |
369 | .enter = &intel_idle, |
370 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
371 | { |
372 | .name = "C6-IVT-4S", | |
373 | .desc = "MWAIT 0x20", | |
b82b6cca | 374 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
375 | .exit_latency = 84, |
376 | .target_residency = 400, | |
5fe2e527 RW |
377 | .enter = &intel_idle, |
378 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
379 | { |
380 | .enter = NULL } | |
381 | }; | |
382 | ||
383 | static struct cpuidle_state ivt_cstates_8s[] = { | |
384 | { | |
385 | .name = "C1-IVT-8S", | |
386 | .desc = "MWAIT 0x00", | |
b82b6cca | 387 | .flags = MWAIT2flg(0x00), |
0138d8f0 LB |
388 | .exit_latency = 1, |
389 | .target_residency = 1, | |
5fe2e527 RW |
390 | .enter = &intel_idle, |
391 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
392 | { |
393 | .name = "C1E-IVT-8S", | |
394 | .desc = "MWAIT 0x01", | |
b82b6cca | 395 | .flags = MWAIT2flg(0x01), |
0138d8f0 LB |
396 | .exit_latency = 10, |
397 | .target_residency = 500, | |
5fe2e527 RW |
398 | .enter = &intel_idle, |
399 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
400 | { |
401 | .name = "C3-IVT-8S", | |
402 | .desc = "MWAIT 0x10", | |
b82b6cca | 403 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
404 | .exit_latency = 59, |
405 | .target_residency = 600, | |
5fe2e527 RW |
406 | .enter = &intel_idle, |
407 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
408 | { |
409 | .name = "C6-IVT-8S", | |
410 | .desc = "MWAIT 0x20", | |
b82b6cca | 411 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
0138d8f0 LB |
412 | .exit_latency = 88, |
413 | .target_residency = 700, | |
5fe2e527 RW |
414 | .enter = &intel_idle, |
415 | .enter_freeze = intel_idle_freeze, }, | |
0138d8f0 LB |
416 | { |
417 | .enter = NULL } | |
418 | }; | |
419 | ||
ba0dc81e | 420 | static struct cpuidle_state hsw_cstates[] = { |
e022e7eb | 421 | { |
85a4d2d4 LB |
422 | .name = "C1-HSW", |
423 | .desc = "MWAIT 0x00", | |
b82b6cca | 424 | .flags = MWAIT2flg(0x00), |
85a4d2d4 LB |
425 | .exit_latency = 2, |
426 | .target_residency = 2, | |
5fe2e527 RW |
427 | .enter = &intel_idle, |
428 | .enter_freeze = intel_idle_freeze, }, | |
32e95180 LB |
429 | { |
430 | .name = "C1E-HSW", | |
431 | .desc = "MWAIT 0x01", | |
b82b6cca | 432 | .flags = MWAIT2flg(0x01), |
32e95180 LB |
433 | .exit_latency = 10, |
434 | .target_residency = 20, | |
5fe2e527 RW |
435 | .enter = &intel_idle, |
436 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 437 | { |
85a4d2d4 LB |
438 | .name = "C3-HSW", |
439 | .desc = "MWAIT 0x10", | |
b82b6cca | 440 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
441 | .exit_latency = 33, |
442 | .target_residency = 100, | |
5fe2e527 RW |
443 | .enter = &intel_idle, |
444 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 445 | { |
85a4d2d4 LB |
446 | .name = "C6-HSW", |
447 | .desc = "MWAIT 0x20", | |
b82b6cca | 448 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
449 | .exit_latency = 133, |
450 | .target_residency = 400, | |
5fe2e527 RW |
451 | .enter = &intel_idle, |
452 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 453 | { |
85a4d2d4 LB |
454 | .name = "C7s-HSW", |
455 | .desc = "MWAIT 0x32", | |
b82b6cca | 456 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, |
85a4d2d4 LB |
457 | .exit_latency = 166, |
458 | .target_residency = 500, | |
5fe2e527 RW |
459 | .enter = &intel_idle, |
460 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb LB |
461 | { |
462 | .name = "C8-HSW", | |
463 | .desc = "MWAIT 0x40", | |
b82b6cca | 464 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
465 | .exit_latency = 300, |
466 | .target_residency = 900, | |
5fe2e527 RW |
467 | .enter = &intel_idle, |
468 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb LB |
469 | { |
470 | .name = "C9-HSW", | |
471 | .desc = "MWAIT 0x50", | |
b82b6cca | 472 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
473 | .exit_latency = 600, |
474 | .target_residency = 1800, | |
5fe2e527 RW |
475 | .enter = &intel_idle, |
476 | .enter_freeze = intel_idle_freeze, }, | |
86239ceb LB |
477 | { |
478 | .name = "C10-HSW", | |
479 | .desc = "MWAIT 0x60", | |
b82b6cca | 480 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
86239ceb LB |
481 | .exit_latency = 2600, |
482 | .target_residency = 7700, | |
5fe2e527 RW |
483 | .enter = &intel_idle, |
484 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
485 | { |
486 | .enter = NULL } | |
85a4d2d4 | 487 | }; |
a138b568 LB |
488 | static struct cpuidle_state bdw_cstates[] = { |
489 | { | |
490 | .name = "C1-BDW", | |
491 | .desc = "MWAIT 0x00", | |
b82b6cca | 492 | .flags = MWAIT2flg(0x00), |
a138b568 LB |
493 | .exit_latency = 2, |
494 | .target_residency = 2, | |
5fe2e527 RW |
495 | .enter = &intel_idle, |
496 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
497 | { |
498 | .name = "C1E-BDW", | |
499 | .desc = "MWAIT 0x01", | |
b82b6cca | 500 | .flags = MWAIT2flg(0x01), |
a138b568 LB |
501 | .exit_latency = 10, |
502 | .target_residency = 20, | |
5fe2e527 RW |
503 | .enter = &intel_idle, |
504 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
505 | { |
506 | .name = "C3-BDW", | |
507 | .desc = "MWAIT 0x10", | |
b82b6cca | 508 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
509 | .exit_latency = 40, |
510 | .target_residency = 100, | |
5fe2e527 RW |
511 | .enter = &intel_idle, |
512 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
513 | { |
514 | .name = "C6-BDW", | |
515 | .desc = "MWAIT 0x20", | |
b82b6cca | 516 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
517 | .exit_latency = 133, |
518 | .target_residency = 400, | |
5fe2e527 RW |
519 | .enter = &intel_idle, |
520 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
521 | { |
522 | .name = "C7s-BDW", | |
523 | .desc = "MWAIT 0x32", | |
b82b6cca | 524 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
525 | .exit_latency = 166, |
526 | .target_residency = 500, | |
5fe2e527 RW |
527 | .enter = &intel_idle, |
528 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
529 | { |
530 | .name = "C8-BDW", | |
531 | .desc = "MWAIT 0x40", | |
b82b6cca | 532 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
533 | .exit_latency = 300, |
534 | .target_residency = 900, | |
5fe2e527 RW |
535 | .enter = &intel_idle, |
536 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
537 | { |
538 | .name = "C9-BDW", | |
539 | .desc = "MWAIT 0x50", | |
b82b6cca | 540 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
541 | .exit_latency = 600, |
542 | .target_residency = 1800, | |
5fe2e527 RW |
543 | .enter = &intel_idle, |
544 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
545 | { |
546 | .name = "C10-BDW", | |
547 | .desc = "MWAIT 0x60", | |
b82b6cca | 548 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, |
a138b568 LB |
549 | .exit_latency = 2600, |
550 | .target_residency = 7700, | |
5fe2e527 RW |
551 | .enter = &intel_idle, |
552 | .enter_freeze = intel_idle_freeze, }, | |
a138b568 LB |
553 | { |
554 | .enter = NULL } | |
555 | }; | |
85a4d2d4 | 556 | |
ba0dc81e | 557 | static struct cpuidle_state atom_cstates[] = { |
e022e7eb | 558 | { |
32e95180 | 559 | .name = "C1E-ATM", |
26717172 | 560 | .desc = "MWAIT 0x00", |
b82b6cca | 561 | .flags = MWAIT2flg(0x00), |
32e95180 LB |
562 | .exit_latency = 10, |
563 | .target_residency = 20, | |
5fe2e527 RW |
564 | .enter = &intel_idle, |
565 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 566 | { |
15e123e5 | 567 | .name = "C2-ATM", |
26717172 | 568 | .desc = "MWAIT 0x10", |
b82b6cca | 569 | .flags = MWAIT2flg(0x10), |
26717172 | 570 | .exit_latency = 20, |
26717172 | 571 | .target_residency = 80, |
5fe2e527 RW |
572 | .enter = &intel_idle, |
573 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 574 | { |
15e123e5 | 575 | .name = "C4-ATM", |
26717172 | 576 | .desc = "MWAIT 0x30", |
b82b6cca | 577 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 578 | .exit_latency = 100, |
26717172 | 579 | .target_residency = 400, |
5fe2e527 RW |
580 | .enter = &intel_idle, |
581 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb | 582 | { |
15e123e5 | 583 | .name = "C6-ATM", |
7fcca7d9 | 584 | .desc = "MWAIT 0x52", |
b82b6cca | 585 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, |
7fcca7d9 | 586 | .exit_latency = 140, |
7fcca7d9 | 587 | .target_residency = 560, |
5fe2e527 RW |
588 | .enter = &intel_idle, |
589 | .enter_freeze = intel_idle_freeze, }, | |
e022e7eb LB |
590 | { |
591 | .enter = NULL } | |
26717172 | 592 | }; |
88390996 | 593 | static struct cpuidle_state avn_cstates[] = { |
fab04b22 LB |
594 | { |
595 | .name = "C1-AVN", | |
596 | .desc = "MWAIT 0x00", | |
b82b6cca | 597 | .flags = MWAIT2flg(0x00), |
fab04b22 LB |
598 | .exit_latency = 2, |
599 | .target_residency = 2, | |
5fe2e527 RW |
600 | .enter = &intel_idle, |
601 | .enter_freeze = intel_idle_freeze, }, | |
fab04b22 LB |
602 | { |
603 | .name = "C6-AVN", | |
604 | .desc = "MWAIT 0x51", | |
b82b6cca | 605 | .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, |
fab04b22 LB |
606 | .exit_latency = 15, |
607 | .target_residency = 45, | |
5fe2e527 RW |
608 | .enter = &intel_idle, |
609 | .enter_freeze = intel_idle_freeze, }, | |
88390996 JL |
610 | { |
611 | .enter = NULL } | |
fab04b22 | 612 | }; |
26717172 | 613 | |
26717172 LB |
614 | /** |
615 | * intel_idle | |
616 | * @dev: cpuidle_device | |
46bcfad7 | 617 | * @drv: cpuidle driver |
e978aa7d | 618 | * @index: index of cpuidle state |
26717172 | 619 | * |
63ff07be | 620 | * Must be called under local_irq_disable(). |
26717172 | 621 | */ |
46bcfad7 DD |
622 | static int intel_idle(struct cpuidle_device *dev, |
623 | struct cpuidle_driver *drv, int index) | |
26717172 LB |
624 | { |
625 | unsigned long ecx = 1; /* break on interrupt flag */ | |
46bcfad7 | 626 | struct cpuidle_state *state = &drv->states[index]; |
b1beab48 | 627 | unsigned long eax = flg2MWAIT(state->flags); |
26717172 | 628 | unsigned int cstate; |
26717172 LB |
629 | int cpu = smp_processor_id(); |
630 | ||
631 | cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; | |
632 | ||
6110a1f4 | 633 | /* |
c8381cc3 LB |
634 | * leave_mm() to avoid costly and often unnecessary wakeups |
635 | * for flushing the user TLB's associated with the active mm. | |
6110a1f4 | 636 | */ |
c8381cc3 | 637 | if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) |
6110a1f4 SS |
638 | leave_mm(cpu); |
639 | ||
26717172 LB |
640 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
641 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
642 | ||
16824255 | 643 | mwait_idle_with_hints(eax, ecx); |
26717172 | 644 | |
26717172 LB |
645 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
646 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
647 | ||
e978aa7d | 648 | return index; |
26717172 LB |
649 | } |
650 | ||
5fe2e527 RW |
651 | /** |
652 | * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle | |
653 | * @dev: cpuidle_device | |
654 | * @drv: cpuidle driver | |
655 | * @index: state index | |
656 | */ | |
657 | static void intel_idle_freeze(struct cpuidle_device *dev, | |
658 | struct cpuidle_driver *drv, int index) | |
659 | { | |
660 | unsigned long ecx = 1; /* break on interrupt flag */ | |
661 | unsigned long eax = flg2MWAIT(drv->states[index].flags); | |
662 | ||
663 | mwait_idle_with_hints(eax, ecx); | |
664 | } | |
665 | ||
2a2d31c8 SL |
666 | static void __setup_broadcast_timer(void *arg) |
667 | { | |
668 | unsigned long reason = (unsigned long)arg; | |
669 | int cpu = smp_processor_id(); | |
670 | ||
671 | reason = reason ? | |
672 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
673 | ||
674 | clockevents_notify(reason, &cpu); | |
675 | } | |
676 | ||
25ac7761 DL |
677 | static int cpu_hotplug_notify(struct notifier_block *n, |
678 | unsigned long action, void *hcpu) | |
2a2d31c8 SL |
679 | { |
680 | int hotcpu = (unsigned long)hcpu; | |
25ac7761 | 681 | struct cpuidle_device *dev; |
2a2d31c8 | 682 | |
e2401453 | 683 | switch (action & ~CPU_TASKS_FROZEN) { |
2a2d31c8 | 684 | case CPU_ONLINE: |
25ac7761 DL |
685 | |
686 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
687 | smp_call_function_single(hotcpu, __setup_broadcast_timer, | |
688 | (void *)true, 1); | |
689 | ||
690 | /* | |
691 | * Some systems can hotplug a cpu at runtime after | |
692 | * the kernel has booted, we have to initialize the | |
693 | * driver in this case | |
694 | */ | |
695 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu); | |
696 | if (!dev->registered) | |
697 | intel_idle_cpu_init(hotcpu); | |
698 | ||
2a2d31c8 | 699 | break; |
2a2d31c8 SL |
700 | } |
701 | return NOTIFY_OK; | |
702 | } | |
703 | ||
25ac7761 DL |
704 | static struct notifier_block cpu_hotplug_notifier = { |
705 | .notifier_call = cpu_hotplug_notify, | |
2a2d31c8 SL |
706 | }; |
707 | ||
14796fca LB |
708 | static void auto_demotion_disable(void *dummy) |
709 | { | |
710 | unsigned long long msr_bits; | |
711 | ||
712 | rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); | |
b66b8b9a | 713 | msr_bits &= ~(icpu->auto_demotion_disable_flags); |
14796fca LB |
714 | wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); |
715 | } | |
32e95180 LB |
716 | static void c1e_promotion_disable(void *dummy) |
717 | { | |
718 | unsigned long long msr_bits; | |
719 | ||
720 | rdmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
721 | msr_bits &= ~0x2; | |
722 | wrmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
723 | } | |
14796fca | 724 | |
b66b8b9a AK |
725 | static const struct idle_cpu idle_cpu_nehalem = { |
726 | .state_table = nehalem_cstates, | |
b66b8b9a | 727 | .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, |
32e95180 | 728 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
729 | }; |
730 | ||
731 | static const struct idle_cpu idle_cpu_atom = { | |
732 | .state_table = atom_cstates, | |
733 | }; | |
734 | ||
735 | static const struct idle_cpu idle_cpu_lincroft = { | |
736 | .state_table = atom_cstates, | |
737 | .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE, | |
738 | }; | |
739 | ||
740 | static const struct idle_cpu idle_cpu_snb = { | |
741 | .state_table = snb_cstates, | |
32e95180 | 742 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
743 | }; |
744 | ||
718987d6 LB |
745 | static const struct idle_cpu idle_cpu_byt = { |
746 | .state_table = byt_cstates, | |
747 | .disable_promotion_to_c1e = true, | |
8c058d53 | 748 | .byt_auto_demotion_disable_flag = true, |
718987d6 LB |
749 | }; |
750 | ||
6edab08c LB |
751 | static const struct idle_cpu idle_cpu_ivb = { |
752 | .state_table = ivb_cstates, | |
32e95180 | 753 | .disable_promotion_to_c1e = true, |
6edab08c LB |
754 | }; |
755 | ||
0138d8f0 LB |
756 | static const struct idle_cpu idle_cpu_ivt = { |
757 | .state_table = ivt_cstates, | |
758 | .disable_promotion_to_c1e = true, | |
759 | }; | |
760 | ||
85a4d2d4 LB |
761 | static const struct idle_cpu idle_cpu_hsw = { |
762 | .state_table = hsw_cstates, | |
32e95180 | 763 | .disable_promotion_to_c1e = true, |
85a4d2d4 LB |
764 | }; |
765 | ||
a138b568 LB |
766 | static const struct idle_cpu idle_cpu_bdw = { |
767 | .state_table = bdw_cstates, | |
768 | .disable_promotion_to_c1e = true, | |
769 | }; | |
770 | ||
fab04b22 LB |
771 | static const struct idle_cpu idle_cpu_avn = { |
772 | .state_table = avn_cstates, | |
773 | .disable_promotion_to_c1e = true, | |
774 | }; | |
775 | ||
b66b8b9a AK |
776 | #define ICPU(model, cpu) \ |
777 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } | |
778 | ||
779 | static const struct x86_cpu_id intel_idle_ids[] = { | |
780 | ICPU(0x1a, idle_cpu_nehalem), | |
781 | ICPU(0x1e, idle_cpu_nehalem), | |
782 | ICPU(0x1f, idle_cpu_nehalem), | |
8bf11938 BH |
783 | ICPU(0x25, idle_cpu_nehalem), |
784 | ICPU(0x2c, idle_cpu_nehalem), | |
785 | ICPU(0x2e, idle_cpu_nehalem), | |
b66b8b9a AK |
786 | ICPU(0x1c, idle_cpu_atom), |
787 | ICPU(0x26, idle_cpu_lincroft), | |
8bf11938 | 788 | ICPU(0x2f, idle_cpu_nehalem), |
b66b8b9a AK |
789 | ICPU(0x2a, idle_cpu_snb), |
790 | ICPU(0x2d, idle_cpu_snb), | |
acead1b0 | 791 | ICPU(0x36, idle_cpu_atom), |
718987d6 | 792 | ICPU(0x37, idle_cpu_byt), |
6edab08c | 793 | ICPU(0x3a, idle_cpu_ivb), |
0138d8f0 | 794 | ICPU(0x3e, idle_cpu_ivt), |
85a4d2d4 LB |
795 | ICPU(0x3c, idle_cpu_hsw), |
796 | ICPU(0x3f, idle_cpu_hsw), | |
797 | ICPU(0x45, idle_cpu_hsw), | |
0b15841b | 798 | ICPU(0x46, idle_cpu_hsw), |
a138b568 LB |
799 | ICPU(0x4d, idle_cpu_avn), |
800 | ICPU(0x3d, idle_cpu_bdw), | |
bea57077 | 801 | ICPU(0x47, idle_cpu_bdw), |
a138b568 LB |
802 | ICPU(0x4f, idle_cpu_bdw), |
803 | ICPU(0x56, idle_cpu_bdw), | |
b66b8b9a AK |
804 | {} |
805 | }; | |
806 | MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); | |
807 | ||
26717172 LB |
808 | /* |
809 | * intel_idle_probe() | |
810 | */ | |
00f3e755 | 811 | static int __init intel_idle_probe(void) |
26717172 | 812 | { |
c4236282 | 813 | unsigned int eax, ebx, ecx; |
b66b8b9a | 814 | const struct x86_cpu_id *id; |
26717172 LB |
815 | |
816 | if (max_cstate == 0) { | |
817 | pr_debug(PREFIX "disabled\n"); | |
818 | return -EPERM; | |
819 | } | |
820 | ||
b66b8b9a AK |
821 | id = x86_match_cpu(intel_idle_ids); |
822 | if (!id) { | |
823 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
824 | boot_cpu_data.x86 == 6) | |
825 | pr_debug(PREFIX "does not run on family %d model %d\n", | |
826 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
26717172 | 827 | return -ENODEV; |
b66b8b9a | 828 | } |
26717172 LB |
829 | |
830 | if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
831 | return -ENODEV; | |
832 | ||
c4236282 | 833 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); |
26717172 LB |
834 | |
835 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || | |
5c2a9f06 TR |
836 | !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || |
837 | !mwait_substates) | |
26717172 | 838 | return -ENODEV; |
26717172 | 839 | |
c4236282 | 840 | pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); |
26717172 | 841 | |
b66b8b9a AK |
842 | icpu = (const struct idle_cpu *)id->driver_data; |
843 | cpuidle_state_table = icpu->state_table; | |
26717172 | 844 | |
56b9aea3 | 845 | if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ |
2a2d31c8 | 846 | lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; |
25ac7761 | 847 | else |
39a74fde | 848 | on_each_cpu(__setup_broadcast_timer, (void *)true, 1); |
25ac7761 | 849 | |
26717172 LB |
850 | pr_debug(PREFIX "v" INTEL_IDLE_VERSION |
851 | " model 0x%X\n", boot_cpu_data.x86_model); | |
852 | ||
853 | pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", | |
854 | lapic_timer_reliable_states); | |
855 | return 0; | |
856 | } | |
857 | ||
858 | /* | |
859 | * intel_idle_cpuidle_devices_uninit() | |
860 | * unregister, free cpuidle_devices | |
861 | */ | |
862 | static void intel_idle_cpuidle_devices_uninit(void) | |
863 | { | |
864 | int i; | |
865 | struct cpuidle_device *dev; | |
866 | ||
867 | for_each_online_cpu(i) { | |
868 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
869 | cpuidle_unregister_device(dev); | |
870 | } | |
871 | ||
872 | free_percpu(intel_idle_cpuidle_devices); | |
873 | return; | |
874 | } | |
0138d8f0 LB |
875 | |
876 | /* | |
877 | * intel_idle_state_table_update() | |
878 | * | |
879 | * Update the default state_table for this CPU-id | |
880 | * | |
881 | * Currently used to access tuned IVT multi-socket targets | |
882 | * Assumption: num_sockets == (max_package_num + 1) | |
883 | */ | |
884 | void intel_idle_state_table_update(void) | |
885 | { | |
886 | /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */ | |
887 | if (boot_cpu_data.x86_model == 0x3e) { /* IVT */ | |
888 | int cpu, package_num, num_sockets = 1; | |
889 | ||
890 | for_each_online_cpu(cpu) { | |
891 | package_num = topology_physical_package_id(cpu); | |
892 | if (package_num + 1 > num_sockets) { | |
893 | num_sockets = package_num + 1; | |
894 | ||
d27dca42 | 895 | if (num_sockets > 4) { |
0138d8f0 LB |
896 | cpuidle_state_table = ivt_cstates_8s; |
897 | return; | |
d27dca42 | 898 | } |
0138d8f0 LB |
899 | } |
900 | } | |
901 | ||
902 | if (num_sockets > 2) | |
903 | cpuidle_state_table = ivt_cstates_4s; | |
904 | /* else, 1 and 2 socket systems use default ivt_cstates */ | |
905 | } | |
906 | return; | |
907 | } | |
908 | ||
46bcfad7 DD |
909 | /* |
910 | * intel_idle_cpuidle_driver_init() | |
911 | * allocate, initialize cpuidle_states | |
912 | */ | |
00f3e755 | 913 | static int __init intel_idle_cpuidle_driver_init(void) |
46bcfad7 DD |
914 | { |
915 | int cstate; | |
916 | struct cpuidle_driver *drv = &intel_idle_driver; | |
917 | ||
0138d8f0 LB |
918 | intel_idle_state_table_update(); |
919 | ||
46bcfad7 DD |
920 | drv->state_count = 1; |
921 | ||
e022e7eb | 922 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
24bfa950 | 923 | int num_substates, mwait_hint, mwait_cstate; |
46bcfad7 | 924 | |
e022e7eb LB |
925 | if (cpuidle_state_table[cstate].enter == NULL) |
926 | break; | |
927 | ||
928 | if (cstate + 1 > max_cstate) { | |
46bcfad7 DD |
929 | printk(PREFIX "max_cstate %d reached\n", |
930 | max_cstate); | |
931 | break; | |
932 | } | |
933 | ||
e022e7eb LB |
934 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
935 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
e022e7eb | 936 | |
24bfa950 | 937 | /* number of sub-states for this state in CPUID.MWAIT */ |
e022e7eb | 938 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
46bcfad7 | 939 | & MWAIT_SUBSTATE_MASK; |
e022e7eb | 940 | |
24bfa950 LB |
941 | /* if NO sub-states for this state in CPUID, skip it */ |
942 | if (num_substates == 0) | |
46bcfad7 | 943 | continue; |
46bcfad7 | 944 | |
e022e7eb | 945 | if (((mwait_cstate + 1) > 2) && |
46bcfad7 DD |
946 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
947 | mark_tsc_unstable("TSC halts in idle" | |
948 | " states deeper than C2"); | |
949 | ||
950 | drv->states[drv->state_count] = /* structure copy */ | |
951 | cpuidle_state_table[cstate]; | |
952 | ||
953 | drv->state_count += 1; | |
954 | } | |
955 | ||
b66b8b9a | 956 | if (icpu->auto_demotion_disable_flags) |
39a74fde | 957 | on_each_cpu(auto_demotion_disable, NULL, 1); |
46bcfad7 | 958 | |
8c058d53 LB |
959 | if (icpu->byt_auto_demotion_disable_flag) { |
960 | wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); | |
961 | wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); | |
962 | } | |
963 | ||
32e95180 LB |
964 | if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */ |
965 | on_each_cpu(c1e_promotion_disable, NULL, 1); | |
966 | ||
46bcfad7 DD |
967 | return 0; |
968 | } | |
969 | ||
970 | ||
26717172 | 971 | /* |
65b7f839 | 972 | * intel_idle_cpu_init() |
26717172 | 973 | * allocate, initialize, register cpuidle_devices |
65b7f839 | 974 | * @cpu: cpu/core to initialize |
26717172 | 975 | */ |
25ac7761 | 976 | static int intel_idle_cpu_init(int cpu) |
26717172 | 977 | { |
26717172 LB |
978 | struct cpuidle_device *dev; |
979 | ||
65b7f839 | 980 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); |
26717172 | 981 | |
65b7f839 | 982 | dev->cpu = cpu; |
26717172 | 983 | |
65b7f839 TR |
984 | if (cpuidle_register_device(dev)) { |
985 | pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu); | |
986 | intel_idle_cpuidle_devices_uninit(); | |
987 | return -EIO; | |
26717172 LB |
988 | } |
989 | ||
b66b8b9a | 990 | if (icpu->auto_demotion_disable_flags) |
65b7f839 TR |
991 | smp_call_function_single(cpu, auto_demotion_disable, NULL, 1); |
992 | ||
dbf87ab8 BZ |
993 | if (icpu->disable_promotion_to_c1e) |
994 | smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1); | |
995 | ||
26717172 LB |
996 | return 0; |
997 | } | |
26717172 LB |
998 | |
999 | static int __init intel_idle_init(void) | |
1000 | { | |
65b7f839 | 1001 | int retval, i; |
26717172 | 1002 | |
d1896049 TR |
1003 | /* Do not load intel_idle at all for now if idle= is passed */ |
1004 | if (boot_option_idle_override != IDLE_NO_OVERRIDE) | |
1005 | return -ENODEV; | |
1006 | ||
26717172 LB |
1007 | retval = intel_idle_probe(); |
1008 | if (retval) | |
1009 | return retval; | |
1010 | ||
46bcfad7 | 1011 | intel_idle_cpuidle_driver_init(); |
26717172 LB |
1012 | retval = cpuidle_register_driver(&intel_idle_driver); |
1013 | if (retval) { | |
3735d524 | 1014 | struct cpuidle_driver *drv = cpuidle_get_driver(); |
26717172 | 1015 | printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", |
3735d524 | 1016 | drv ? drv->name : "none"); |
26717172 LB |
1017 | return retval; |
1018 | } | |
1019 | ||
65b7f839 TR |
1020 | intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); |
1021 | if (intel_idle_cpuidle_devices == NULL) | |
1022 | return -ENOMEM; | |
1023 | ||
07494d54 SB |
1024 | cpu_notifier_register_begin(); |
1025 | ||
65b7f839 TR |
1026 | for_each_online_cpu(i) { |
1027 | retval = intel_idle_cpu_init(i); | |
1028 | if (retval) { | |
07494d54 | 1029 | cpu_notifier_register_done(); |
65b7f839 TR |
1030 | cpuidle_unregister_driver(&intel_idle_driver); |
1031 | return retval; | |
1032 | } | |
26717172 | 1033 | } |
07494d54 SB |
1034 | __register_cpu_notifier(&cpu_hotplug_notifier); |
1035 | ||
1036 | cpu_notifier_register_done(); | |
26717172 LB |
1037 | |
1038 | return 0; | |
1039 | } | |
1040 | ||
1041 | static void __exit intel_idle_exit(void) | |
1042 | { | |
1043 | intel_idle_cpuidle_devices_uninit(); | |
1044 | cpuidle_unregister_driver(&intel_idle_driver); | |
1045 | ||
07494d54 | 1046 | cpu_notifier_register_begin(); |
25ac7761 DL |
1047 | |
1048 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
39a74fde | 1049 | on_each_cpu(__setup_broadcast_timer, (void *)false, 1); |
07494d54 SB |
1050 | __unregister_cpu_notifier(&cpu_hotplug_notifier); |
1051 | ||
1052 | cpu_notifier_register_done(); | |
2a2d31c8 | 1053 | |
26717172 LB |
1054 | return; |
1055 | } | |
1056 | ||
1057 | module_init(intel_idle_init); | |
1058 | module_exit(intel_idle_exit); | |
1059 | ||
26717172 | 1060 | module_param(max_cstate, int, 0444); |
26717172 LB |
1061 | |
1062 | MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); | |
1063 | MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); | |
1064 | MODULE_LICENSE("GPL"); |