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1da177e4 LT |
1 | #ifndef _IEEE1394_CSR_H |
2 | #define _IEEE1394_CSR_H | |
3 | ||
de4394f1 | 4 | #include <linux/spinlock_types.h> |
1da177e4 LT |
5 | |
6 | #include "csr1212.h" | |
de4394f1 | 7 | #include "ieee1394_types.h" |
1da177e4 | 8 | |
e1d118f1 | 9 | #define CSR_REGISTER_BASE 0xfffff0000000ULL |
1da177e4 LT |
10 | |
11 | /* register offsets relative to CSR_REGISTER_BASE */ | |
e1d118f1 SR |
12 | #define CSR_STATE_CLEAR 0x0 |
13 | #define CSR_STATE_SET 0x4 | |
14 | #define CSR_NODE_IDS 0x8 | |
15 | #define CSR_RESET_START 0xc | |
16 | #define CSR_SPLIT_TIMEOUT_HI 0x18 | |
17 | #define CSR_SPLIT_TIMEOUT_LO 0x1c | |
18 | #define CSR_CYCLE_TIME 0x200 | |
19 | #define CSR_BUS_TIME 0x204 | |
20 | #define CSR_BUSY_TIMEOUT 0x210 | |
21 | #define CSR_BUS_MANAGER_ID 0x21c | |
22 | #define CSR_BANDWIDTH_AVAILABLE 0x220 | |
23 | #define CSR_CHANNELS_AVAILABLE 0x224 | |
24 | #define CSR_CHANNELS_AVAILABLE_HI 0x224 | |
25 | #define CSR_CHANNELS_AVAILABLE_LO 0x228 | |
26 | #define CSR_BROADCAST_CHANNEL 0x234 | |
27 | #define CSR_CONFIG_ROM 0x400 | |
28 | #define CSR_CONFIG_ROM_END 0x800 | |
29 | #define CSR_FCP_COMMAND 0xB00 | |
30 | #define CSR_FCP_RESPONSE 0xD00 | |
31 | #define CSR_FCP_END 0xF00 | |
32 | #define CSR_TOPOLOGY_MAP 0x1000 | |
33 | #define CSR_TOPOLOGY_MAP_END 0x1400 | |
34 | #define CSR_SPEED_MAP 0x2000 | |
35 | #define CSR_SPEED_MAP_END 0x3000 | |
1da177e4 LT |
36 | |
37 | /* IEEE 1394 bus specific Configuration ROM Key IDs */ | |
38 | #define IEEE1394_KV_ID_POWER_REQUIREMENTS (0x30) | |
39 | ||
e1d118f1 | 40 | /* IEEE 1394 Bus Information Block specifics */ |
1da177e4 LT |
41 | #define CSR_BUS_INFO_SIZE (5 * sizeof(quadlet_t)) |
42 | ||
e1d118f1 SR |
43 | #define CSR_IRMC_SHIFT 31 |
44 | #define CSR_CMC_SHIFT 30 | |
45 | #define CSR_ISC_SHIFT 29 | |
46 | #define CSR_BMC_SHIFT 28 | |
47 | #define CSR_PMC_SHIFT 27 | |
48 | #define CSR_CYC_CLK_ACC_SHIFT 16 | |
49 | #define CSR_MAX_REC_SHIFT 12 | |
50 | #define CSR_MAX_ROM_SHIFT 8 | |
51 | #define CSR_GENERATION_SHIFT 4 | |
1da177e4 LT |
52 | |
53 | #define CSR_SET_BUS_INFO_GENERATION(csr, gen) \ | |
54 | ((csr)->bus_info_data[2] = \ | |
55 | cpu_to_be32((be32_to_cpu((csr)->bus_info_data[2]) & \ | |
e1d118f1 | 56 | ~(0xf << CSR_GENERATION_SHIFT)) | \ |
1da177e4 LT |
57 | (gen) << CSR_GENERATION_SHIFT)) |
58 | ||
59 | struct csr_control { | |
e1d118f1 SR |
60 | spinlock_t lock; |
61 | ||
62 | quadlet_t state; | |
63 | quadlet_t node_ids; | |
64 | quadlet_t split_timeout_hi, split_timeout_lo; | |
65 | unsigned long expire; /* Calculated from split_timeout */ | |
66 | quadlet_t cycle_time; | |
67 | quadlet_t bus_time; | |
68 | quadlet_t bus_manager_id; | |
69 | quadlet_t bandwidth_available; | |
70 | quadlet_t channels_available_hi, channels_available_lo; | |
1da177e4 LT |
71 | quadlet_t broadcast_channel; |
72 | ||
73 | /* Bus Info */ | |
74 | quadlet_t guid_hi, guid_lo; | |
75 | u8 cyc_clk_acc; | |
76 | u8 max_rec; | |
77 | u8 max_rom; | |
78 | u8 generation; /* Only use values between 0x2 and 0xf */ | |
79 | u8 lnk_spd; | |
80 | ||
81 | unsigned long gen_timestamp[16]; | |
82 | ||
83 | struct csr1212_csr *rom; | |
84 | ||
e1d118f1 SR |
85 | quadlet_t topology_map[256]; |
86 | quadlet_t speed_map[1024]; | |
1da177e4 LT |
87 | }; |
88 | ||
89 | extern struct csr1212_bus_ops csr_bus_ops; | |
90 | ||
91 | int init_csr(void); | |
92 | void cleanup_csr(void); | |
93 | ||
d8831d55 SR |
94 | /* hpsb_update_config_rom() is deprecated */ |
95 | struct hpsb_host; | |
96 | int hpsb_update_config_rom(struct hpsb_host *host, const quadlet_t *new_rom, | |
97 | size_t size, unsigned char rom_version); | |
98 | ||
1da177e4 | 99 | #endif /* _IEEE1394_CSR_H */ |