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1da177e4 LT |
1 | /* |
2 | * pcilynx.c - Texas Instruments PCILynx driver | |
3 | * Copyright (C) 1999,2000 Andreas Bombe <andreas.bombe@munich.netsurf.de>, | |
4 | * Stephan Linz <linz@mazet.de> | |
5 | * Manfred Weihs <weihs@ict.tuwien.ac.at> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software Foundation, | |
19 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * Contributions: | |
24 | * | |
25 | * Manfred Weihs <weihs@ict.tuwien.ac.at> | |
26 | * reading bus info block (containing GUID) from serial | |
27 | * eeprom via i2c and storing it in config ROM | |
28 | * Reworked code for initiating bus resets | |
29 | * (long, short, with or without hold-off) | |
30 | * Enhancements in async and iso send code | |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/kernel.h> |
34 | #include <linux/slab.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/wait.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/moduleparam.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/fs.h> | |
43 | #include <linux/poll.h> | |
44 | #include <linux/kdev_t.h> | |
2554bd2a | 45 | #include <linux/dma-mapping.h> |
1da177e4 LT |
46 | #include <asm/byteorder.h> |
47 | #include <asm/atomic.h> | |
48 | #include <asm/io.h> | |
49 | #include <asm/uaccess.h> | |
50 | #include <asm/irq.h> | |
51 | ||
52 | #include "csr1212.h" | |
53 | #include "ieee1394.h" | |
54 | #include "ieee1394_types.h" | |
55 | #include "hosts.h" | |
56 | #include "ieee1394_core.h" | |
57 | #include "highlevel.h" | |
58 | #include "pcilynx.h" | |
59 | ||
60 | #include <linux/i2c.h> | |
61 | #include <linux/i2c-algo-bit.h> | |
62 | ||
63 | /* print general (card independent) information */ | |
64 | #define PRINT_G(level, fmt, args...) printk(level "pcilynx: " fmt "\n" , ## args) | |
65 | /* print card specific information */ | |
66 | #define PRINT(level, card, fmt, args...) printk(level "pcilynx%d: " fmt "\n" , card , ## args) | |
67 | ||
68 | #ifdef CONFIG_IEEE1394_VERBOSEDEBUG | |
69 | #define PRINT_GD(level, fmt, args...) printk(level "pcilynx: " fmt "\n" , ## args) | |
70 | #define PRINTD(level, card, fmt, args...) printk(level "pcilynx%d: " fmt "\n" , card , ## args) | |
71 | #else | |
72 | #define PRINT_GD(level, fmt, args...) do {} while (0) | |
73 | #define PRINTD(level, card, fmt, args...) do {} while (0) | |
74 | #endif | |
75 | ||
76 | ||
77 | /* Module Parameters */ | |
1934b8b6 | 78 | static int skip_eeprom; |
1da177e4 LT |
79 | module_param(skip_eeprom, int, 0444); |
80 | MODULE_PARM_DESC(skip_eeprom, "Use generic bus info block instead of serial eeprom (default = 0)."); | |
81 | ||
82 | ||
83 | static struct hpsb_host_driver lynx_driver; | |
84 | static unsigned int card_id; | |
85 | ||
86 | ||
87 | ||
88 | /* | |
89 | * I2C stuff | |
90 | */ | |
91 | ||
92 | /* the i2c stuff was inspired by i2c-philips-par.c */ | |
93 | ||
94 | static void bit_setscl(void *data, int state) | |
95 | { | |
96 | if (state) { | |
97 | ((struct ti_lynx *) data)->i2c_driven_state |= 0x00000040; | |
98 | } else { | |
99 | ((struct ti_lynx *) data)->i2c_driven_state &= ~0x00000040; | |
100 | } | |
101 | reg_write((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL, ((struct ti_lynx *) data)->i2c_driven_state); | |
102 | } | |
103 | ||
104 | static void bit_setsda(void *data, int state) | |
105 | { | |
106 | if (state) { | |
107 | ((struct ti_lynx *) data)->i2c_driven_state |= 0x00000010; | |
108 | } else { | |
109 | ((struct ti_lynx *) data)->i2c_driven_state &= ~0x00000010; | |
110 | } | |
111 | reg_write((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL, ((struct ti_lynx *) data)->i2c_driven_state); | |
112 | } | |
113 | ||
114 | static int bit_getscl(void *data) | |
115 | { | |
116 | return reg_read((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL) & 0x00000040; | |
117 | } | |
118 | ||
119 | static int bit_getsda(void *data) | |
120 | { | |
121 | return reg_read((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL) & 0x00000010; | |
122 | } | |
123 | ||
124 | static int bit_reg(struct i2c_client *client) | |
125 | { | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static int bit_unreg(struct i2c_client *client) | |
130 | { | |
131 | return 0; | |
132 | } | |
133 | ||
134 | static struct i2c_algo_bit_data bit_data = { | |
135 | .setsda = bit_setsda, | |
136 | .setscl = bit_setscl, | |
137 | .getsda = bit_getsda, | |
138 | .getscl = bit_getscl, | |
139 | .udelay = 5, | |
1da177e4 LT |
140 | .timeout = 100, |
141 | }; | |
142 | ||
143 | static struct i2c_adapter bit_ops = { | |
144 | .id = 0xAA, //FIXME: probably we should get an id in i2c-id.h | |
145 | .client_register = bit_reg, | |
146 | .client_unregister = bit_unreg, | |
147 | .name = "PCILynx I2C", | |
148 | }; | |
149 | ||
150 | ||
151 | ||
152 | /* | |
153 | * PCL handling functions. | |
154 | */ | |
155 | ||
156 | static pcl_t alloc_pcl(struct ti_lynx *lynx) | |
157 | { | |
158 | u8 m; | |
159 | int i, j; | |
160 | ||
161 | spin_lock(&lynx->lock); | |
162 | /* FIXME - use ffz() to make this readable */ | |
163 | for (i = 0; i < (LOCALRAM_SIZE / 1024); i++) { | |
164 | m = lynx->pcl_bmap[i]; | |
165 | for (j = 0; j < 8; j++) { | |
166 | if (m & 1<<j) { | |
167 | continue; | |
168 | } | |
169 | m |= 1<<j; | |
170 | lynx->pcl_bmap[i] = m; | |
171 | spin_unlock(&lynx->lock); | |
172 | return 8 * i + j; | |
173 | } | |
174 | } | |
175 | spin_unlock(&lynx->lock); | |
176 | ||
177 | return -1; | |
178 | } | |
179 | ||
180 | ||
181 | #if 0 | |
182 | static void free_pcl(struct ti_lynx *lynx, pcl_t pclid) | |
183 | { | |
184 | int off, bit; | |
185 | ||
186 | off = pclid / 8; | |
187 | bit = pclid % 8; | |
188 | ||
189 | if (pclid < 0) { | |
190 | return; | |
191 | } | |
192 | ||
193 | spin_lock(&lynx->lock); | |
194 | if (lynx->pcl_bmap[off] & 1<<bit) { | |
195 | lynx->pcl_bmap[off] &= ~(1<<bit); | |
196 | } else { | |
197 | PRINT(KERN_ERR, lynx->id, | |
198 | "attempted to free unallocated PCL %d", pclid); | |
199 | } | |
200 | spin_unlock(&lynx->lock); | |
201 | } | |
202 | ||
203 | /* functions useful for debugging */ | |
204 | static void pretty_print_pcl(const struct ti_pcl *pcl) | |
205 | { | |
206 | int i; | |
207 | ||
208 | printk("PCL next %08x, userdata %08x, status %08x, remtrans %08x, nextbuf %08x\n", | |
209 | pcl->next, pcl->user_data, pcl->pcl_status, | |
210 | pcl->remaining_transfer_count, pcl->next_data_buffer); | |
211 | ||
212 | printk("PCL"); | |
213 | for (i=0; i<13; i++) { | |
214 | printk(" c%x:%08x d%x:%08x", | |
215 | i, pcl->buffer[i].control, i, pcl->buffer[i].pointer); | |
216 | if (!(i & 0x3) && (i != 12)) printk("\nPCL"); | |
217 | } | |
218 | printk("\n"); | |
219 | } | |
220 | ||
221 | static void print_pcl(const struct ti_lynx *lynx, pcl_t pclid) | |
222 | { | |
223 | struct ti_pcl pcl; | |
224 | ||
225 | get_pcl(lynx, pclid, &pcl); | |
226 | pretty_print_pcl(&pcl); | |
227 | } | |
228 | #endif | |
229 | ||
230 | ||
231 | ||
232 | /*********************************** | |
233 | * IEEE-1394 functionality section * | |
234 | ***********************************/ | |
235 | ||
236 | ||
237 | static int get_phy_reg(struct ti_lynx *lynx, int addr) | |
238 | { | |
239 | int retval; | |
240 | int i = 0; | |
241 | ||
242 | unsigned long flags; | |
243 | ||
244 | if (addr > 15) { | |
245 | PRINT(KERN_ERR, lynx->id, | |
246 | "%s: PHY register address %d out of range", | |
247 | __FUNCTION__, addr); | |
248 | return -1; | |
249 | } | |
250 | ||
251 | spin_lock_irqsave(&lynx->phy_reg_lock, flags); | |
252 | ||
253 | reg_write(lynx, LINK_PHY, LINK_PHY_READ | LINK_PHY_ADDR(addr)); | |
254 | do { | |
255 | retval = reg_read(lynx, LINK_PHY); | |
256 | ||
257 | if (i > 10000) { | |
258 | PRINT(KERN_ERR, lynx->id, "%s: runaway loop, aborting", | |
259 | __FUNCTION__); | |
260 | retval = -1; | |
261 | break; | |
262 | } | |
263 | i++; | |
264 | } while ((retval & 0xf00) != LINK_PHY_RADDR(addr)); | |
265 | ||
266 | reg_write(lynx, LINK_INT_STATUS, LINK_INT_PHY_REG_RCVD); | |
267 | spin_unlock_irqrestore(&lynx->phy_reg_lock, flags); | |
268 | ||
269 | if (retval != -1) { | |
270 | return retval & 0xff; | |
271 | } else { | |
272 | return -1; | |
273 | } | |
274 | } | |
275 | ||
276 | static int set_phy_reg(struct ti_lynx *lynx, int addr, int val) | |
277 | { | |
278 | unsigned long flags; | |
279 | ||
280 | if (addr > 15) { | |
281 | PRINT(KERN_ERR, lynx->id, | |
282 | "%s: PHY register address %d out of range", __FUNCTION__, addr); | |
283 | return -1; | |
284 | } | |
285 | ||
286 | if (val > 0xff) { | |
287 | PRINT(KERN_ERR, lynx->id, | |
288 | "%s: PHY register value %d out of range", __FUNCTION__, val); | |
289 | return -1; | |
290 | } | |
291 | ||
292 | spin_lock_irqsave(&lynx->phy_reg_lock, flags); | |
293 | ||
294 | reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | LINK_PHY_ADDR(addr) | |
295 | | LINK_PHY_WDATA(val)); | |
296 | ||
297 | spin_unlock_irqrestore(&lynx->phy_reg_lock, flags); | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | static int sel_phy_reg_page(struct ti_lynx *lynx, int page) | |
303 | { | |
304 | int reg; | |
305 | ||
306 | if (page > 7) { | |
307 | PRINT(KERN_ERR, lynx->id, | |
308 | "%s: PHY page %d out of range", __FUNCTION__, page); | |
309 | return -1; | |
310 | } | |
311 | ||
312 | reg = get_phy_reg(lynx, 7); | |
313 | if (reg != -1) { | |
314 | reg &= 0x1f; | |
315 | reg |= (page << 5); | |
316 | set_phy_reg(lynx, 7, reg); | |
317 | return 0; | |
318 | } else { | |
319 | return -1; | |
320 | } | |
321 | } | |
322 | ||
323 | #if 0 /* not needed at this time */ | |
324 | static int sel_phy_reg_port(struct ti_lynx *lynx, int port) | |
325 | { | |
326 | int reg; | |
327 | ||
328 | if (port > 15) { | |
329 | PRINT(KERN_ERR, lynx->id, | |
330 | "%s: PHY port %d out of range", __FUNCTION__, port); | |
331 | return -1; | |
332 | } | |
333 | ||
334 | reg = get_phy_reg(lynx, 7); | |
335 | if (reg != -1) { | |
336 | reg &= 0xf0; | |
337 | reg |= port; | |
338 | set_phy_reg(lynx, 7, reg); | |
339 | return 0; | |
340 | } else { | |
341 | return -1; | |
342 | } | |
343 | } | |
344 | #endif | |
345 | ||
346 | static u32 get_phy_vendorid(struct ti_lynx *lynx) | |
347 | { | |
348 | u32 pvid = 0; | |
349 | sel_phy_reg_page(lynx, 1); | |
350 | pvid |= (get_phy_reg(lynx, 10) << 16); | |
351 | pvid |= (get_phy_reg(lynx, 11) << 8); | |
352 | pvid |= get_phy_reg(lynx, 12); | |
353 | PRINT(KERN_INFO, lynx->id, "PHY vendor id 0x%06x", pvid); | |
354 | return pvid; | |
355 | } | |
356 | ||
357 | static u32 get_phy_productid(struct ti_lynx *lynx) | |
358 | { | |
359 | u32 id = 0; | |
360 | sel_phy_reg_page(lynx, 1); | |
361 | id |= (get_phy_reg(lynx, 13) << 16); | |
362 | id |= (get_phy_reg(lynx, 14) << 8); | |
363 | id |= get_phy_reg(lynx, 15); | |
364 | PRINT(KERN_INFO, lynx->id, "PHY product id 0x%06x", id); | |
365 | return id; | |
366 | } | |
367 | ||
368 | static quadlet_t generate_own_selfid(struct ti_lynx *lynx, | |
369 | struct hpsb_host *host) | |
370 | { | |
371 | quadlet_t lsid; | |
372 | char phyreg[7]; | |
373 | int i; | |
374 | ||
375 | phyreg[0] = lynx->phy_reg0; | |
376 | for (i = 1; i < 7; i++) { | |
377 | phyreg[i] = get_phy_reg(lynx, i); | |
378 | } | |
379 | ||
380 | /* FIXME? We assume a TSB21LV03A phy here. This code doesn't support | |
381 | more than 3 ports on the PHY anyway. */ | |
382 | ||
383 | lsid = 0x80400000 | ((phyreg[0] & 0xfc) << 22); | |
384 | lsid |= (phyreg[1] & 0x3f) << 16; /* gap count */ | |
385 | lsid |= (phyreg[2] & 0xc0) << 8; /* max speed */ | |
386 | if (!hpsb_disable_irm) | |
387 | lsid |= (phyreg[6] & 0x01) << 11; /* contender (phy dependent) */ | |
388 | /* lsid |= 1 << 11; *//* set contender (hack) */ | |
389 | lsid |= (phyreg[6] & 0x10) >> 3; /* initiated reset */ | |
390 | ||
391 | for (i = 0; i < (phyreg[2] & 0xf); i++) { /* ports */ | |
392 | if (phyreg[3 + i] & 0x4) { | |
393 | lsid |= (((phyreg[3 + i] & 0x8) | 0x10) >> 3) | |
394 | << (6 - i*2); | |
395 | } else { | |
396 | lsid |= 1 << (6 - i*2); | |
397 | } | |
398 | } | |
399 | ||
400 | cpu_to_be32s(&lsid); | |
401 | PRINT(KERN_DEBUG, lynx->id, "generated own selfid 0x%x", lsid); | |
402 | return lsid; | |
403 | } | |
404 | ||
405 | static void handle_selfid(struct ti_lynx *lynx, struct hpsb_host *host) | |
406 | { | |
407 | quadlet_t *q = lynx->rcv_page; | |
408 | int phyid, isroot, size; | |
409 | quadlet_t lsid = 0; | |
410 | int i; | |
411 | ||
412 | if (lynx->phy_reg0 == -1 || lynx->selfid_size == -1) return; | |
413 | ||
414 | size = lynx->selfid_size; | |
415 | phyid = lynx->phy_reg0; | |
416 | ||
417 | i = (size > 16 ? 16 : size) / 4 - 1; | |
418 | while (i >= 0) { | |
419 | cpu_to_be32s(&q[i]); | |
420 | i--; | |
421 | } | |
422 | ||
423 | if (!lynx->phyic.reg_1394a) { | |
424 | lsid = generate_own_selfid(lynx, host); | |
425 | } | |
426 | ||
427 | isroot = (phyid & 2) != 0; | |
428 | phyid >>= 2; | |
429 | PRINT(KERN_INFO, lynx->id, "SelfID process finished (phyid %d, %s)", | |
430 | phyid, (isroot ? "root" : "not root")); | |
431 | reg_write(lynx, LINK_ID, (0xffc0 | phyid) << 16); | |
432 | ||
433 | if (!lynx->phyic.reg_1394a && !size) { | |
434 | hpsb_selfid_received(host, lsid); | |
435 | } | |
436 | ||
437 | while (size > 0) { | |
438 | struct selfid *sid = (struct selfid *)q; | |
439 | ||
440 | if (!lynx->phyic.reg_1394a && !sid->extended | |
441 | && (sid->phy_id == (phyid + 1))) { | |
442 | hpsb_selfid_received(host, lsid); | |
443 | } | |
444 | ||
445 | if (q[0] == ~q[1]) { | |
446 | PRINT(KERN_DEBUG, lynx->id, "SelfID packet 0x%x rcvd", | |
447 | q[0]); | |
448 | hpsb_selfid_received(host, q[0]); | |
449 | } else { | |
450 | PRINT(KERN_INFO, lynx->id, | |
451 | "inconsistent selfid 0x%x/0x%x", q[0], q[1]); | |
452 | } | |
453 | q += 2; | |
454 | size -= 8; | |
455 | } | |
456 | ||
457 | if (!lynx->phyic.reg_1394a && isroot && phyid != 0) { | |
458 | hpsb_selfid_received(host, lsid); | |
459 | } | |
460 | ||
461 | hpsb_selfid_complete(host, phyid, isroot); | |
462 | ||
463 | if (host->in_bus_reset) return; /* in bus reset again */ | |
464 | ||
465 | if (isroot) reg_set_bits(lynx, LINK_CONTROL, LINK_CONTROL_CYCMASTER); //FIXME: I do not think, we need this here | |
466 | reg_set_bits(lynx, LINK_CONTROL, | |
467 | LINK_CONTROL_RCV_CMP_VALID | LINK_CONTROL_TX_ASYNC_EN | |
468 | | LINK_CONTROL_RX_ASYNC_EN | LINK_CONTROL_CYCTIMEREN); | |
469 | } | |
470 | ||
471 | ||
472 | ||
473 | /* This must be called with the respective queue_lock held. */ | |
474 | static void send_next(struct ti_lynx *lynx, int what) | |
475 | { | |
476 | struct ti_pcl pcl; | |
477 | struct lynx_send_data *d; | |
478 | struct hpsb_packet *packet; | |
479 | ||
480 | d = (what == hpsb_iso ? &lynx->iso_send : &lynx->async); | |
481 | if (!list_empty(&d->pcl_queue)) { | |
482 | PRINT(KERN_ERR, lynx->id, "trying to queue a new packet in nonempty fifo"); | |
483 | BUG(); | |
484 | } | |
485 | ||
486 | packet = driver_packet(d->queue.next); | |
487 | list_move_tail(&packet->driver_list, &d->pcl_queue); | |
488 | ||
489 | d->header_dma = pci_map_single(lynx->dev, packet->header, | |
490 | packet->header_size, PCI_DMA_TODEVICE); | |
491 | if (packet->data_size) { | |
492 | d->data_dma = pci_map_single(lynx->dev, packet->data, | |
493 | packet->data_size, | |
494 | PCI_DMA_TODEVICE); | |
495 | } else { | |
496 | d->data_dma = 0; | |
497 | } | |
498 | ||
499 | pcl.next = PCL_NEXT_INVALID; | |
500 | pcl.async_error_next = PCL_NEXT_INVALID; | |
501 | pcl.pcl_status = 0; | |
502 | pcl.buffer[0].control = packet->speed_code << 14 | packet->header_size; | |
503 | #ifndef __BIG_ENDIAN | |
504 | pcl.buffer[0].control |= PCL_BIGENDIAN; | |
505 | #endif | |
506 | pcl.buffer[0].pointer = d->header_dma; | |
507 | pcl.buffer[1].control = PCL_LAST_BUFF | packet->data_size; | |
508 | pcl.buffer[1].pointer = d->data_dma; | |
509 | ||
510 | switch (packet->type) { | |
511 | case hpsb_async: | |
512 | pcl.buffer[0].control |= PCL_CMD_XMT; | |
513 | break; | |
514 | case hpsb_iso: | |
515 | pcl.buffer[0].control |= PCL_CMD_XMT | PCL_ISOMODE; | |
516 | break; | |
517 | case hpsb_raw: | |
518 | pcl.buffer[0].control |= PCL_CMD_UNFXMT; | |
519 | break; | |
520 | } | |
521 | ||
522 | put_pcl(lynx, d->pcl, &pcl); | |
523 | run_pcl(lynx, d->pcl_start, d->channel); | |
524 | } | |
525 | ||
526 | ||
527 | /* called from subsystem core */ | |
528 | static int lynx_transmit(struct hpsb_host *host, struct hpsb_packet *packet) | |
529 | { | |
530 | struct ti_lynx *lynx = host->hostdata; | |
531 | struct lynx_send_data *d; | |
532 | unsigned long flags; | |
533 | ||
534 | if (packet->data_size >= 4096) { | |
535 | PRINT(KERN_ERR, lynx->id, "transmit packet data too big (%Zd)", | |
536 | packet->data_size); | |
537 | return -EOVERFLOW; | |
538 | } | |
539 | ||
540 | switch (packet->type) { | |
541 | case hpsb_async: | |
542 | case hpsb_raw: | |
543 | d = &lynx->async; | |
544 | break; | |
545 | case hpsb_iso: | |
546 | d = &lynx->iso_send; | |
547 | break; | |
548 | default: | |
549 | PRINT(KERN_ERR, lynx->id, "invalid packet type %d", | |
550 | packet->type); | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | if (packet->tcode == TCODE_WRITEQ | |
555 | || packet->tcode == TCODE_READQ_RESPONSE) { | |
556 | cpu_to_be32s(&packet->header[3]); | |
557 | } | |
558 | ||
559 | spin_lock_irqsave(&d->queue_lock, flags); | |
560 | ||
561 | list_add_tail(&packet->driver_list, &d->queue); | |
562 | if (list_empty(&d->pcl_queue)) | |
563 | send_next(lynx, packet->type); | |
564 | ||
565 | spin_unlock_irqrestore(&d->queue_lock, flags); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | ||
571 | /* called from subsystem core */ | |
572 | static int lynx_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg) | |
573 | { | |
574 | struct ti_lynx *lynx = host->hostdata; | |
575 | int retval = 0; | |
576 | struct hpsb_packet *packet; | |
577 | LIST_HEAD(packet_list); | |
578 | unsigned long flags; | |
579 | int phy_reg; | |
580 | ||
581 | switch (cmd) { | |
582 | case RESET_BUS: | |
583 | if (reg_read(lynx, LINK_INT_STATUS) & LINK_INT_PHY_BUSRESET) { | |
584 | retval = 0; | |
585 | break; | |
586 | } | |
587 | ||
588 | switch (arg) { | |
589 | case SHORT_RESET: | |
590 | if (lynx->phyic.reg_1394a) { | |
591 | phy_reg = get_phy_reg(lynx, 5); | |
592 | if (phy_reg == -1) { | |
593 | PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed"); | |
594 | retval = -1; | |
595 | break; | |
596 | } | |
597 | phy_reg |= 0x40; | |
598 | ||
599 | PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset) on request"); | |
600 | ||
601 | lynx->selfid_size = -1; | |
602 | lynx->phy_reg0 = -1; | |
603 | set_phy_reg(lynx, 5, phy_reg); /* set ISBR */ | |
604 | break; | |
605 | } else { | |
606 | PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy"); | |
607 | /* fall through to long bus reset */ | |
608 | } | |
609 | case LONG_RESET: | |
610 | phy_reg = get_phy_reg(lynx, 1); | |
611 | if (phy_reg == -1) { | |
612 | PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed"); | |
613 | retval = -1; | |
614 | break; | |
615 | } | |
616 | phy_reg |= 0x40; | |
617 | ||
618 | PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset) on request"); | |
619 | ||
620 | lynx->selfid_size = -1; | |
621 | lynx->phy_reg0 = -1; | |
622 | set_phy_reg(lynx, 1, phy_reg); /* clear RHB, set IBR */ | |
623 | break; | |
624 | case SHORT_RESET_NO_FORCE_ROOT: | |
625 | if (lynx->phyic.reg_1394a) { | |
626 | phy_reg = get_phy_reg(lynx, 1); | |
627 | if (phy_reg == -1) { | |
628 | PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed"); | |
629 | retval = -1; | |
630 | break; | |
631 | } | |
632 | if (phy_reg & 0x80) { | |
633 | phy_reg &= ~0x80; | |
634 | set_phy_reg(lynx, 1, phy_reg); /* clear RHB */ | |
635 | } | |
636 | ||
637 | phy_reg = get_phy_reg(lynx, 5); | |
638 | if (phy_reg == -1) { | |
639 | PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed"); | |
640 | retval = -1; | |
641 | break; | |
642 | } | |
643 | phy_reg |= 0x40; | |
644 | ||
645 | PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset, no force_root) on request"); | |
646 | ||
647 | lynx->selfid_size = -1; | |
648 | lynx->phy_reg0 = -1; | |
649 | set_phy_reg(lynx, 5, phy_reg); /* set ISBR */ | |
650 | break; | |
651 | } else { | |
652 | PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy"); | |
653 | /* fall through to long bus reset */ | |
654 | } | |
655 | case LONG_RESET_NO_FORCE_ROOT: | |
656 | phy_reg = get_phy_reg(lynx, 1); | |
657 | if (phy_reg == -1) { | |
658 | PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed"); | |
659 | retval = -1; | |
660 | break; | |
661 | } | |
662 | phy_reg &= ~0x80; | |
663 | phy_reg |= 0x40; | |
664 | ||
665 | PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset, no force_root) on request"); | |
666 | ||
667 | lynx->selfid_size = -1; | |
668 | lynx->phy_reg0 = -1; | |
669 | set_phy_reg(lynx, 1, phy_reg); /* clear RHB, set IBR */ | |
670 | break; | |
671 | case SHORT_RESET_FORCE_ROOT: | |
672 | if (lynx->phyic.reg_1394a) { | |
673 | phy_reg = get_phy_reg(lynx, 1); | |
674 | if (phy_reg == -1) { | |
675 | PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed"); | |
676 | retval = -1; | |
677 | break; | |
678 | } | |
679 | if (!(phy_reg & 0x80)) { | |
680 | phy_reg |= 0x80; | |
681 | set_phy_reg(lynx, 1, phy_reg); /* set RHB */ | |
682 | } | |
683 | ||
684 | phy_reg = get_phy_reg(lynx, 5); | |
685 | if (phy_reg == -1) { | |
686 | PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed"); | |
687 | retval = -1; | |
688 | break; | |
689 | } | |
690 | phy_reg |= 0x40; | |
691 | ||
692 | PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset, force_root set) on request"); | |
693 | ||
694 | lynx->selfid_size = -1; | |
695 | lynx->phy_reg0 = -1; | |
696 | set_phy_reg(lynx, 5, phy_reg); /* set ISBR */ | |
697 | break; | |
698 | } else { | |
699 | PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy"); | |
700 | /* fall through to long bus reset */ | |
701 | } | |
702 | case LONG_RESET_FORCE_ROOT: | |
703 | phy_reg = get_phy_reg(lynx, 1); | |
704 | if (phy_reg == -1) { | |
705 | PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed"); | |
706 | retval = -1; | |
707 | break; | |
708 | } | |
709 | phy_reg |= 0xc0; | |
710 | ||
711 | PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset, force_root set) on request"); | |
712 | ||
713 | lynx->selfid_size = -1; | |
714 | lynx->phy_reg0 = -1; | |
715 | set_phy_reg(lynx, 1, phy_reg); /* set IBR and RHB */ | |
716 | break; | |
717 | default: | |
718 | PRINT(KERN_ERR, lynx->id, "unknown argument for reset_bus command %d", arg); | |
719 | retval = -1; | |
720 | } | |
721 | ||
722 | break; | |
723 | ||
724 | case GET_CYCLE_COUNTER: | |
725 | retval = reg_read(lynx, CYCLE_TIMER); | |
726 | break; | |
727 | ||
728 | case SET_CYCLE_COUNTER: | |
729 | reg_write(lynx, CYCLE_TIMER, arg); | |
730 | break; | |
731 | ||
732 | case SET_BUS_ID: | |
733 | reg_write(lynx, LINK_ID, | |
734 | (arg << 22) | (reg_read(lynx, LINK_ID) & 0x003f0000)); | |
735 | break; | |
736 | ||
737 | case ACT_CYCLE_MASTER: | |
738 | if (arg) { | |
739 | reg_set_bits(lynx, LINK_CONTROL, | |
740 | LINK_CONTROL_CYCMASTER); | |
741 | } else { | |
742 | reg_clear_bits(lynx, LINK_CONTROL, | |
743 | LINK_CONTROL_CYCMASTER); | |
744 | } | |
745 | break; | |
746 | ||
747 | case CANCEL_REQUESTS: | |
748 | spin_lock_irqsave(&lynx->async.queue_lock, flags); | |
749 | ||
750 | reg_write(lynx, DMA_CHAN_CTRL(CHANNEL_ASYNC_SEND), 0); | |
751 | list_splice(&lynx->async.queue, &packet_list); | |
752 | INIT_LIST_HEAD(&lynx->async.queue); | |
753 | ||
754 | if (list_empty(&lynx->async.pcl_queue)) { | |
755 | spin_unlock_irqrestore(&lynx->async.queue_lock, flags); | |
756 | PRINTD(KERN_DEBUG, lynx->id, "no async packet in PCL to cancel"); | |
757 | } else { | |
758 | struct ti_pcl pcl; | |
759 | u32 ack; | |
760 | struct hpsb_packet *packet; | |
761 | ||
762 | PRINT(KERN_INFO, lynx->id, "cancelling async packet, that was already in PCL"); | |
763 | ||
764 | get_pcl(lynx, lynx->async.pcl, &pcl); | |
765 | ||
766 | packet = driver_packet(lynx->async.pcl_queue.next); | |
767 | list_del_init(&packet->driver_list); | |
768 | ||
769 | pci_unmap_single(lynx->dev, lynx->async.header_dma, | |
770 | packet->header_size, PCI_DMA_TODEVICE); | |
771 | if (packet->data_size) { | |
772 | pci_unmap_single(lynx->dev, lynx->async.data_dma, | |
773 | packet->data_size, PCI_DMA_TODEVICE); | |
774 | } | |
775 | ||
776 | spin_unlock_irqrestore(&lynx->async.queue_lock, flags); | |
777 | ||
778 | if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) { | |
779 | if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) { | |
780 | ack = (pcl.pcl_status >> 15) & 0xf; | |
781 | PRINTD(KERN_INFO, lynx->id, "special ack %d", ack); | |
782 | ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR); | |
783 | } else { | |
784 | ack = (pcl.pcl_status >> 15) & 0xf; | |
785 | } | |
786 | } else { | |
787 | PRINT(KERN_INFO, lynx->id, "async packet was not completed"); | |
788 | ack = ACKX_ABORTED; | |
789 | } | |
790 | hpsb_packet_sent(host, packet, ack); | |
791 | } | |
792 | ||
793 | while (!list_empty(&packet_list)) { | |
794 | packet = driver_packet(packet_list.next); | |
795 | list_del_init(&packet->driver_list); | |
796 | hpsb_packet_sent(host, packet, ACKX_ABORTED); | |
797 | } | |
798 | ||
799 | break; | |
800 | ||
801 | case ISO_LISTEN_CHANNEL: | |
802 | spin_lock_irqsave(&lynx->iso_rcv.lock, flags); | |
803 | ||
804 | if (lynx->iso_rcv.chan_count++ == 0) { | |
805 | reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), | |
806 | DMA_WORD1_CMP_ENABLE_MASTER); | |
807 | } | |
808 | ||
809 | spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags); | |
810 | break; | |
811 | ||
812 | case ISO_UNLISTEN_CHANNEL: | |
813 | spin_lock_irqsave(&lynx->iso_rcv.lock, flags); | |
814 | ||
815 | if (--lynx->iso_rcv.chan_count == 0) { | |
816 | reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), | |
817 | 0); | |
818 | } | |
819 | ||
820 | spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags); | |
821 | break; | |
822 | ||
823 | default: | |
824 | PRINT(KERN_ERR, lynx->id, "unknown devctl command %d", cmd); | |
825 | retval = -1; | |
826 | } | |
827 | ||
828 | return retval; | |
829 | } | |
830 | ||
831 | ||
832 | /*************************************** | |
833 | * IEEE-1394 functionality section END * | |
834 | ***************************************/ | |
835 | ||
1da177e4 LT |
836 | |
837 | /******************************************************** | |
838 | * Global stuff (interrupt handler, init/shutdown code) * | |
839 | ********************************************************/ | |
840 | ||
841 | ||
7d12e780 | 842 | static irqreturn_t lynx_irq_handler(int irq, void *dev_id) |
1da177e4 LT |
843 | { |
844 | struct ti_lynx *lynx = (struct ti_lynx *)dev_id; | |
845 | struct hpsb_host *host = lynx->host; | |
846 | u32 intmask; | |
847 | u32 linkint; | |
848 | ||
849 | linkint = reg_read(lynx, LINK_INT_STATUS); | |
850 | intmask = reg_read(lynx, PCI_INT_STATUS); | |
851 | ||
852 | if (!(intmask & PCI_INT_INT_PEND)) | |
853 | return IRQ_NONE; | |
854 | ||
855 | PRINTD(KERN_DEBUG, lynx->id, "interrupt: 0x%08x / 0x%08x", intmask, | |
856 | linkint); | |
857 | ||
858 | reg_write(lynx, LINK_INT_STATUS, linkint); | |
859 | reg_write(lynx, PCI_INT_STATUS, intmask); | |
860 | ||
1da177e4 LT |
861 | if (intmask & PCI_INT_1394) { |
862 | if (linkint & LINK_INT_PHY_TIMEOUT) { | |
863 | PRINT(KERN_INFO, lynx->id, "PHY timeout occurred"); | |
864 | } | |
865 | if (linkint & LINK_INT_PHY_BUSRESET) { | |
866 | PRINT(KERN_INFO, lynx->id, "bus reset interrupt"); | |
867 | lynx->selfid_size = -1; | |
868 | lynx->phy_reg0 = -1; | |
869 | if (!host->in_bus_reset) | |
870 | hpsb_bus_reset(host); | |
871 | } | |
872 | if (linkint & LINK_INT_PHY_REG_RCVD) { | |
873 | u32 reg; | |
874 | ||
875 | spin_lock(&lynx->phy_reg_lock); | |
876 | reg = reg_read(lynx, LINK_PHY); | |
877 | spin_unlock(&lynx->phy_reg_lock); | |
878 | ||
879 | if (!host->in_bus_reset) { | |
880 | PRINT(KERN_INFO, lynx->id, | |
881 | "phy reg received without reset"); | |
882 | } else if (reg & 0xf00) { | |
883 | PRINT(KERN_INFO, lynx->id, | |
884 | "unsolicited phy reg %d received", | |
885 | (reg >> 8) & 0xf); | |
886 | } else { | |
887 | lynx->phy_reg0 = reg & 0xff; | |
888 | handle_selfid(lynx, host); | |
889 | } | |
890 | } | |
891 | if (linkint & LINK_INT_ISO_STUCK) { | |
892 | PRINT(KERN_INFO, lynx->id, "isochronous transmitter stuck"); | |
893 | } | |
894 | if (linkint & LINK_INT_ASYNC_STUCK) { | |
895 | PRINT(KERN_INFO, lynx->id, "asynchronous transmitter stuck"); | |
896 | } | |
897 | if (linkint & LINK_INT_SENT_REJECT) { | |
898 | PRINT(KERN_INFO, lynx->id, "sent reject"); | |
899 | } | |
900 | if (linkint & LINK_INT_TX_INVALID_TC) { | |
901 | PRINT(KERN_INFO, lynx->id, "invalid transaction code"); | |
902 | } | |
903 | if (linkint & LINK_INT_GRF_OVERFLOW) { | |
904 | /* flush FIFO if overflow happens during reset */ | |
905 | if (host->in_bus_reset) | |
906 | reg_write(lynx, FIFO_CONTROL, | |
907 | FIFO_CONTROL_GRF_FLUSH); | |
908 | PRINT(KERN_INFO, lynx->id, "GRF overflow"); | |
909 | } | |
910 | if (linkint & LINK_INT_ITF_UNDERFLOW) { | |
911 | PRINT(KERN_INFO, lynx->id, "ITF underflow"); | |
912 | } | |
913 | if (linkint & LINK_INT_ATF_UNDERFLOW) { | |
914 | PRINT(KERN_INFO, lynx->id, "ATF underflow"); | |
915 | } | |
916 | } | |
917 | ||
918 | if (intmask & PCI_INT_DMA_HLT(CHANNEL_ISO_RCV)) { | |
919 | PRINTD(KERN_DEBUG, lynx->id, "iso receive"); | |
920 | ||
921 | spin_lock(&lynx->iso_rcv.lock); | |
922 | ||
923 | lynx->iso_rcv.stat[lynx->iso_rcv.next] = | |
924 | reg_read(lynx, DMA_CHAN_STAT(CHANNEL_ISO_RCV)); | |
925 | ||
926 | lynx->iso_rcv.used++; | |
927 | lynx->iso_rcv.next = (lynx->iso_rcv.next + 1) % NUM_ISORCV_PCL; | |
928 | ||
929 | if ((lynx->iso_rcv.next == lynx->iso_rcv.last) | |
930 | || !lynx->iso_rcv.chan_count) { | |
931 | PRINTD(KERN_DEBUG, lynx->id, "stopped"); | |
932 | reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), 0); | |
933 | } | |
934 | ||
935 | run_sub_pcl(lynx, lynx->iso_rcv.pcl_start, lynx->iso_rcv.next, | |
936 | CHANNEL_ISO_RCV); | |
937 | ||
938 | spin_unlock(&lynx->iso_rcv.lock); | |
939 | ||
940 | tasklet_schedule(&lynx->iso_rcv.tq); | |
941 | } | |
942 | ||
943 | if (intmask & PCI_INT_DMA_HLT(CHANNEL_ASYNC_SEND)) { | |
944 | PRINTD(KERN_DEBUG, lynx->id, "async sent"); | |
945 | spin_lock(&lynx->async.queue_lock); | |
946 | ||
947 | if (list_empty(&lynx->async.pcl_queue)) { | |
948 | spin_unlock(&lynx->async.queue_lock); | |
949 | PRINT(KERN_WARNING, lynx->id, "async dma halted, but no queued packet (maybe it was cancelled)"); | |
950 | } else { | |
951 | struct ti_pcl pcl; | |
952 | u32 ack; | |
953 | struct hpsb_packet *packet; | |
954 | ||
955 | get_pcl(lynx, lynx->async.pcl, &pcl); | |
956 | ||
957 | packet = driver_packet(lynx->async.pcl_queue.next); | |
958 | list_del_init(&packet->driver_list); | |
959 | ||
960 | pci_unmap_single(lynx->dev, lynx->async.header_dma, | |
961 | packet->header_size, PCI_DMA_TODEVICE); | |
962 | if (packet->data_size) { | |
963 | pci_unmap_single(lynx->dev, lynx->async.data_dma, | |
964 | packet->data_size, PCI_DMA_TODEVICE); | |
965 | } | |
966 | ||
967 | if (!list_empty(&lynx->async.queue)) { | |
968 | send_next(lynx, hpsb_async); | |
969 | } | |
970 | ||
971 | spin_unlock(&lynx->async.queue_lock); | |
972 | ||
973 | if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) { | |
974 | if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) { | |
975 | ack = (pcl.pcl_status >> 15) & 0xf; | |
976 | PRINTD(KERN_INFO, lynx->id, "special ack %d", ack); | |
977 | ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR); | |
978 | } else { | |
979 | ack = (pcl.pcl_status >> 15) & 0xf; | |
980 | } | |
981 | } else { | |
982 | PRINT(KERN_INFO, lynx->id, "async packet was not completed"); | |
983 | ack = ACKX_SEND_ERROR; | |
984 | } | |
985 | hpsb_packet_sent(host, packet, ack); | |
986 | } | |
987 | } | |
988 | ||
989 | if (intmask & PCI_INT_DMA_HLT(CHANNEL_ISO_SEND)) { | |
990 | PRINTD(KERN_DEBUG, lynx->id, "iso sent"); | |
991 | spin_lock(&lynx->iso_send.queue_lock); | |
992 | ||
993 | if (list_empty(&lynx->iso_send.pcl_queue)) { | |
994 | spin_unlock(&lynx->iso_send.queue_lock); | |
995 | PRINT(KERN_ERR, lynx->id, "iso send dma halted, but no queued packet"); | |
996 | } else { | |
997 | struct ti_pcl pcl; | |
998 | u32 ack; | |
999 | struct hpsb_packet *packet; | |
1000 | ||
1001 | get_pcl(lynx, lynx->iso_send.pcl, &pcl); | |
1002 | ||
1003 | packet = driver_packet(lynx->iso_send.pcl_queue.next); | |
1004 | list_del_init(&packet->driver_list); | |
1005 | ||
1006 | pci_unmap_single(lynx->dev, lynx->iso_send.header_dma, | |
1007 | packet->header_size, PCI_DMA_TODEVICE); | |
1008 | if (packet->data_size) { | |
1009 | pci_unmap_single(lynx->dev, lynx->iso_send.data_dma, | |
1010 | packet->data_size, PCI_DMA_TODEVICE); | |
1011 | } | |
1012 | ||
1013 | if (!list_empty(&lynx->iso_send.queue)) { | |
1014 | send_next(lynx, hpsb_iso); | |
1015 | } | |
1016 | ||
1017 | spin_unlock(&lynx->iso_send.queue_lock); | |
1018 | ||
1019 | if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) { | |
1020 | if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) { | |
1021 | ack = (pcl.pcl_status >> 15) & 0xf; | |
1022 | PRINTD(KERN_INFO, lynx->id, "special ack %d", ack); | |
1023 | ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR); | |
1024 | } else { | |
1025 | ack = (pcl.pcl_status >> 15) & 0xf; | |
1026 | } | |
1027 | } else { | |
1028 | PRINT(KERN_INFO, lynx->id, "iso send packet was not completed"); | |
1029 | ack = ACKX_SEND_ERROR; | |
1030 | } | |
1031 | ||
1032 | hpsb_packet_sent(host, packet, ack); //FIXME: maybe we should just use ACK_COMPLETE and ACKX_SEND_ERROR | |
1033 | } | |
1034 | } | |
1035 | ||
1036 | if (intmask & PCI_INT_DMA_HLT(CHANNEL_ASYNC_RCV)) { | |
1037 | /* general receive DMA completed */ | |
1038 | int stat = reg_read(lynx, DMA_CHAN_STAT(CHANNEL_ASYNC_RCV)); | |
1039 | ||
1040 | PRINTD(KERN_DEBUG, lynx->id, "received packet size %d", | |
1041 | stat & 0x1fff); | |
1042 | ||
1043 | if (stat & DMA_CHAN_STAT_SELFID) { | |
1044 | lynx->selfid_size = stat & 0x1fff; | |
1045 | handle_selfid(lynx, host); | |
1046 | } else { | |
1047 | quadlet_t *q_data = lynx->rcv_page; | |
1048 | if ((*q_data >> 4 & 0xf) == TCODE_READQ_RESPONSE | |
1049 | || (*q_data >> 4 & 0xf) == TCODE_WRITEQ) { | |
1050 | cpu_to_be32s(q_data + 3); | |
1051 | } | |
1052 | hpsb_packet_received(host, q_data, stat & 0x1fff, 0); | |
1053 | } | |
1054 | ||
1055 | run_pcl(lynx, lynx->rcv_pcl_start, CHANNEL_ASYNC_RCV); | |
1056 | } | |
1057 | ||
1058 | return IRQ_HANDLED; | |
1059 | } | |
1060 | ||
1061 | ||
1062 | static void iso_rcv_bh(struct ti_lynx *lynx) | |
1063 | { | |
1064 | unsigned int idx; | |
1065 | quadlet_t *data; | |
1066 | unsigned long flags; | |
1067 | ||
1068 | spin_lock_irqsave(&lynx->iso_rcv.lock, flags); | |
1069 | ||
1070 | while (lynx->iso_rcv.used) { | |
1071 | idx = lynx->iso_rcv.last; | |
1072 | spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags); | |
1073 | ||
1074 | data = lynx->iso_rcv.page[idx / ISORCV_PER_PAGE] | |
1075 | + (idx % ISORCV_PER_PAGE) * MAX_ISORCV_SIZE; | |
1076 | ||
1077 | if ((*data >> 16) + 4 != (lynx->iso_rcv.stat[idx] & 0x1fff)) { | |
1078 | PRINT(KERN_ERR, lynx->id, | |
1079 | "iso length mismatch 0x%08x/0x%08x", *data, | |
1080 | lynx->iso_rcv.stat[idx]); | |
1081 | } | |
1082 | ||
1083 | if (lynx->iso_rcv.stat[idx] | |
1084 | & (DMA_CHAN_STAT_PCIERR | DMA_CHAN_STAT_PKTERR)) { | |
1085 | PRINT(KERN_INFO, lynx->id, | |
1086 | "iso receive error on %d to 0x%p", idx, data); | |
1087 | } else { | |
1088 | hpsb_packet_received(lynx->host, data, | |
1089 | lynx->iso_rcv.stat[idx] & 0x1fff, | |
1090 | 0); | |
1091 | } | |
1092 | ||
1093 | spin_lock_irqsave(&lynx->iso_rcv.lock, flags); | |
1094 | lynx->iso_rcv.last = (idx + 1) % NUM_ISORCV_PCL; | |
1095 | lynx->iso_rcv.used--; | |
1096 | } | |
1097 | ||
1098 | if (lynx->iso_rcv.chan_count) { | |
1099 | reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), | |
1100 | DMA_WORD1_CMP_ENABLE_MASTER); | |
1101 | } | |
1102 | spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags); | |
1103 | } | |
1104 | ||
1105 | ||
1106 | static void remove_card(struct pci_dev *dev) | |
1107 | { | |
1108 | struct ti_lynx *lynx; | |
1109 | struct device *lynx_dev; | |
1110 | int i; | |
1111 | ||
1112 | lynx = pci_get_drvdata(dev); | |
1113 | if (!lynx) return; | |
1114 | pci_set_drvdata(dev, NULL); | |
1115 | ||
1116 | lynx_dev = get_device(&lynx->host->device); | |
1117 | ||
1118 | switch (lynx->state) { | |
1119 | case is_host: | |
1120 | reg_write(lynx, PCI_INT_ENABLE, 0); | |
1121 | hpsb_remove_host(lynx->host); | |
1122 | case have_intr: | |
1123 | reg_write(lynx, PCI_INT_ENABLE, 0); | |
1124 | free_irq(lynx->dev->irq, lynx); | |
1125 | ||
1126 | /* Disable IRM Contender and LCtrl */ | |
1127 | if (lynx->phyic.reg_1394a) | |
1128 | set_phy_reg(lynx, 4, ~0xc0 & get_phy_reg(lynx, 4)); | |
1129 | ||
1130 | /* Let all other nodes know to ignore us */ | |
1131 | lynx_devctl(lynx->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT); | |
1132 | ||
1133 | case have_iomappings: | |
1134 | reg_set_bits(lynx, MISC_CONTROL, MISC_CONTROL_SWRESET); | |
1135 | /* Fix buggy cards with autoboot pin not tied low: */ | |
1136 | reg_write(lynx, DMA0_CHAN_CTRL, 0); | |
1137 | iounmap(lynx->registers); | |
1138 | iounmap(lynx->local_rom); | |
1139 | iounmap(lynx->local_ram); | |
1140 | iounmap(lynx->aux_port); | |
1141 | case have_1394_buffers: | |
1142 | for (i = 0; i < ISORCV_PAGES; i++) { | |
1143 | if (lynx->iso_rcv.page[i]) { | |
1144 | pci_free_consistent(lynx->dev, PAGE_SIZE, | |
1145 | lynx->iso_rcv.page[i], | |
1146 | lynx->iso_rcv.page_dma[i]); | |
1147 | } | |
1148 | } | |
1149 | pci_free_consistent(lynx->dev, PAGE_SIZE, lynx->rcv_page, | |
1150 | lynx->rcv_page_dma); | |
1151 | case have_aux_buf: | |
1da177e4 | 1152 | case have_pcl_mem: |
1da177e4 LT |
1153 | pci_free_consistent(lynx->dev, LOCALRAM_SIZE, lynx->pcl_mem, |
1154 | lynx->pcl_mem_dma); | |
1da177e4 LT |
1155 | case clear: |
1156 | /* do nothing - already freed */ | |
1157 | ; | |
1158 | } | |
1159 | ||
1160 | tasklet_kill(&lynx->iso_rcv.tq); | |
1161 | ||
1162 | if (lynx_dev) | |
1163 | put_device(lynx_dev); | |
1164 | } | |
1165 | ||
1166 | ||
1167 | static int __devinit add_card(struct pci_dev *dev, | |
1168 | const struct pci_device_id *devid_is_unused) | |
1169 | { | |
1170 | #define FAIL(fmt, args...) do { \ | |
1171 | PRINT_G(KERN_ERR, fmt , ## args); \ | |
1172 | remove_card(dev); \ | |
1173 | return error; \ | |
1174 | } while (0) | |
1175 | ||
1176 | char irq_buf[16]; | |
1177 | struct hpsb_host *host; | |
1178 | struct ti_lynx *lynx; /* shortcut to currently handled device */ | |
1179 | struct ti_pcl pcl; | |
1180 | u32 *pcli; | |
1181 | int i; | |
1182 | int error; | |
1183 | ||
1184 | error = -ENXIO; | |
1185 | ||
2554bd2a | 1186 | if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) |
1da177e4 LT |
1187 | FAIL("DMA address limits not supported for PCILynx hardware"); |
1188 | if (pci_enable_device(dev)) | |
1189 | FAIL("failed to enable PCILynx hardware"); | |
1190 | pci_set_master(dev); | |
1191 | ||
1192 | error = -ENOMEM; | |
1193 | ||
1194 | host = hpsb_alloc_host(&lynx_driver, sizeof(struct ti_lynx), &dev->dev); | |
1195 | if (!host) FAIL("failed to allocate control structure memory"); | |
1196 | ||
1197 | lynx = host->hostdata; | |
1198 | lynx->id = card_id++; | |
1199 | lynx->dev = dev; | |
1200 | lynx->state = clear; | |
1201 | lynx->host = host; | |
1202 | host->pdev = dev; | |
1203 | pci_set_drvdata(dev, lynx); | |
1204 | ||
1205 | spin_lock_init(&lynx->lock); | |
1206 | spin_lock_init(&lynx->phy_reg_lock); | |
1207 | ||
1da177e4 LT |
1208 | lynx->pcl_mem = pci_alloc_consistent(dev, LOCALRAM_SIZE, |
1209 | &lynx->pcl_mem_dma); | |
1210 | ||
1211 | if (lynx->pcl_mem != NULL) { | |
1212 | lynx->state = have_pcl_mem; | |
1213 | PRINT(KERN_INFO, lynx->id, | |
1214 | "allocated PCL memory %d Bytes @ 0x%p", LOCALRAM_SIZE, | |
1215 | lynx->pcl_mem); | |
1216 | } else { | |
1217 | FAIL("failed to allocate PCL memory area"); | |
1218 | } | |
1da177e4 LT |
1219 | |
1220 | lynx->rcv_page = pci_alloc_consistent(dev, PAGE_SIZE, | |
1221 | &lynx->rcv_page_dma); | |
1222 | if (lynx->rcv_page == NULL) { | |
1223 | FAIL("failed to allocate receive buffer"); | |
1224 | } | |
1225 | lynx->state = have_1394_buffers; | |
1226 | ||
1227 | for (i = 0; i < ISORCV_PAGES; i++) { | |
1228 | lynx->iso_rcv.page[i] = | |
1229 | pci_alloc_consistent(dev, PAGE_SIZE, | |
1230 | &lynx->iso_rcv.page_dma[i]); | |
1231 | if (lynx->iso_rcv.page[i] == NULL) { | |
1232 | FAIL("failed to allocate iso receive buffers"); | |
1233 | } | |
1234 | } | |
1235 | ||
1236 | lynx->registers = ioremap_nocache(pci_resource_start(dev,0), | |
1237 | PCILYNX_MAX_REGISTER); | |
1238 | lynx->local_ram = ioremap(pci_resource_start(dev,1), PCILYNX_MAX_MEMORY); | |
1239 | lynx->aux_port = ioremap(pci_resource_start(dev,2), PCILYNX_MAX_MEMORY); | |
1240 | lynx->local_rom = ioremap(pci_resource_start(dev,PCI_ROM_RESOURCE), | |
1241 | PCILYNX_MAX_MEMORY); | |
1242 | lynx->state = have_iomappings; | |
1243 | ||
1244 | if (lynx->registers == NULL) { | |
1245 | FAIL("failed to remap registers - card not accessible"); | |
1246 | } | |
1247 | ||
1da177e4 LT |
1248 | reg_set_bits(lynx, MISC_CONTROL, MISC_CONTROL_SWRESET); |
1249 | /* Fix buggy cards with autoboot pin not tied low: */ | |
1250 | reg_write(lynx, DMA0_CHAN_CTRL, 0); | |
1251 | ||
1da177e4 | 1252 | sprintf (irq_buf, "%d", dev->irq); |
1da177e4 | 1253 | |
272ee69c | 1254 | if (!request_irq(dev->irq, lynx_irq_handler, IRQF_SHARED, |
1da177e4 LT |
1255 | PCILYNX_DRIVER_NAME, lynx)) { |
1256 | PRINT(KERN_INFO, lynx->id, "allocated interrupt %s", irq_buf); | |
1257 | lynx->state = have_intr; | |
1258 | } else { | |
1259 | FAIL("failed to allocate shared interrupt %s", irq_buf); | |
1260 | } | |
1261 | ||
1262 | /* alloc_pcl return values are not checked, it is expected that the | |
1263 | * provided PCL space is sufficient for the initial allocations */ | |
1da177e4 LT |
1264 | lynx->rcv_pcl = alloc_pcl(lynx); |
1265 | lynx->rcv_pcl_start = alloc_pcl(lynx); | |
1266 | lynx->async.pcl = alloc_pcl(lynx); | |
1267 | lynx->async.pcl_start = alloc_pcl(lynx); | |
1268 | lynx->iso_send.pcl = alloc_pcl(lynx); | |
1269 | lynx->iso_send.pcl_start = alloc_pcl(lynx); | |
1270 | ||
1271 | for (i = 0; i < NUM_ISORCV_PCL; i++) { | |
1272 | lynx->iso_rcv.pcl[i] = alloc_pcl(lynx); | |
1273 | } | |
1274 | lynx->iso_rcv.pcl_start = alloc_pcl(lynx); | |
1275 | ||
1276 | /* all allocations successful - simple init stuff follows */ | |
1277 | ||
1278 | reg_write(lynx, PCI_INT_ENABLE, PCI_INT_DMA_ALL); | |
1279 | ||
1da177e4 LT |
1280 | tasklet_init(&lynx->iso_rcv.tq, (void (*)(unsigned long))iso_rcv_bh, |
1281 | (unsigned long)lynx); | |
1282 | ||
1283 | spin_lock_init(&lynx->iso_rcv.lock); | |
1284 | ||
1285 | spin_lock_init(&lynx->async.queue_lock); | |
1286 | lynx->async.channel = CHANNEL_ASYNC_SEND; | |
1287 | spin_lock_init(&lynx->iso_send.queue_lock); | |
1288 | lynx->iso_send.channel = CHANNEL_ISO_SEND; | |
1289 | ||
1290 | PRINT(KERN_INFO, lynx->id, "remapped memory spaces reg 0x%p, rom 0x%p, " | |
1291 | "ram 0x%p, aux 0x%p", lynx->registers, lynx->local_rom, | |
1292 | lynx->local_ram, lynx->aux_port); | |
1293 | ||
1294 | /* now, looking for PHY register set */ | |
1295 | if ((get_phy_reg(lynx, 2) & 0xe0) == 0xe0) { | |
1296 | lynx->phyic.reg_1394a = 1; | |
1297 | PRINT(KERN_INFO, lynx->id, | |
1298 | "found 1394a conform PHY (using extended register set)"); | |
1299 | lynx->phyic.vendor = get_phy_vendorid(lynx); | |
1300 | lynx->phyic.product = get_phy_productid(lynx); | |
1301 | } else { | |
1302 | lynx->phyic.reg_1394a = 0; | |
1303 | PRINT(KERN_INFO, lynx->id, "found old 1394 PHY"); | |
1304 | } | |
1305 | ||
1306 | lynx->selfid_size = -1; | |
1307 | lynx->phy_reg0 = -1; | |
1308 | ||
1309 | INIT_LIST_HEAD(&lynx->async.queue); | |
1310 | INIT_LIST_HEAD(&lynx->async.pcl_queue); | |
1311 | INIT_LIST_HEAD(&lynx->iso_send.queue); | |
1312 | INIT_LIST_HEAD(&lynx->iso_send.pcl_queue); | |
1313 | ||
1314 | pcl.next = pcl_bus(lynx, lynx->rcv_pcl); | |
1315 | put_pcl(lynx, lynx->rcv_pcl_start, &pcl); | |
1316 | ||
1317 | pcl.next = PCL_NEXT_INVALID; | |
1318 | pcl.async_error_next = PCL_NEXT_INVALID; | |
1319 | ||
1320 | pcl.buffer[0].control = PCL_CMD_RCV | 16; | |
1321 | #ifndef __BIG_ENDIAN | |
1322 | pcl.buffer[0].control |= PCL_BIGENDIAN; | |
1323 | #endif | |
1324 | pcl.buffer[1].control = PCL_LAST_BUFF | 4080; | |
1325 | ||
1326 | pcl.buffer[0].pointer = lynx->rcv_page_dma; | |
1327 | pcl.buffer[1].pointer = lynx->rcv_page_dma + 16; | |
1328 | put_pcl(lynx, lynx->rcv_pcl, &pcl); | |
1329 | ||
1330 | pcl.next = pcl_bus(lynx, lynx->async.pcl); | |
1331 | pcl.async_error_next = pcl_bus(lynx, lynx->async.pcl); | |
1332 | put_pcl(lynx, lynx->async.pcl_start, &pcl); | |
1333 | ||
1334 | pcl.next = pcl_bus(lynx, lynx->iso_send.pcl); | |
1335 | pcl.async_error_next = PCL_NEXT_INVALID; | |
1336 | put_pcl(lynx, lynx->iso_send.pcl_start, &pcl); | |
1337 | ||
1338 | pcl.next = PCL_NEXT_INVALID; | |
1339 | pcl.async_error_next = PCL_NEXT_INVALID; | |
1340 | pcl.buffer[0].control = PCL_CMD_RCV | 4; | |
1341 | #ifndef __BIG_ENDIAN | |
1342 | pcl.buffer[0].control |= PCL_BIGENDIAN; | |
1343 | #endif | |
1344 | pcl.buffer[1].control = PCL_LAST_BUFF | 2044; | |
1345 | ||
1346 | for (i = 0; i < NUM_ISORCV_PCL; i++) { | |
1347 | int page = i / ISORCV_PER_PAGE; | |
1348 | int sec = i % ISORCV_PER_PAGE; | |
1349 | ||
1350 | pcl.buffer[0].pointer = lynx->iso_rcv.page_dma[page] | |
1351 | + sec * MAX_ISORCV_SIZE; | |
1352 | pcl.buffer[1].pointer = pcl.buffer[0].pointer + 4; | |
1353 | put_pcl(lynx, lynx->iso_rcv.pcl[i], &pcl); | |
1354 | } | |
1355 | ||
1356 | pcli = (u32 *)&pcl; | |
1357 | for (i = 0; i < NUM_ISORCV_PCL; i++) { | |
1358 | pcli[i] = pcl_bus(lynx, lynx->iso_rcv.pcl[i]); | |
1359 | } | |
1360 | put_pcl(lynx, lynx->iso_rcv.pcl_start, &pcl); | |
1361 | ||
1362 | /* FIFO sizes from left to right: ITF=48 ATF=48 GRF=160 */ | |
1363 | reg_write(lynx, FIFO_SIZES, 0x003030a0); | |
1364 | /* 20 byte threshold before triggering PCI transfer */ | |
1365 | reg_write(lynx, DMA_GLOBAL_REGISTER, 0x2<<24); | |
1366 | /* threshold on both send FIFOs before transmitting: | |
1367 | FIFO size - cache line size - 1 */ | |
1368 | i = reg_read(lynx, PCI_LATENCY_CACHELINE) & 0xff; | |
1369 | i = 0x30 - i - 1; | |
1370 | reg_write(lynx, FIFO_XMIT_THRESHOLD, (i << 8) | i); | |
1371 | ||
1372 | reg_set_bits(lynx, PCI_INT_ENABLE, PCI_INT_1394); | |
1373 | ||
1374 | reg_write(lynx, LINK_INT_ENABLE, LINK_INT_PHY_TIMEOUT | |
1375 | | LINK_INT_PHY_REG_RCVD | LINK_INT_PHY_BUSRESET | |
1376 | | LINK_INT_ISO_STUCK | LINK_INT_ASYNC_STUCK | |
1377 | | LINK_INT_SENT_REJECT | LINK_INT_TX_INVALID_TC | |
1378 | | LINK_INT_GRF_OVERFLOW | LINK_INT_ITF_UNDERFLOW | |
1379 | | LINK_INT_ATF_UNDERFLOW); | |
1380 | ||
1381 | reg_write(lynx, DMA_WORD0_CMP_VALUE(CHANNEL_ASYNC_RCV), 0); | |
1382 | reg_write(lynx, DMA_WORD0_CMP_ENABLE(CHANNEL_ASYNC_RCV), 0xa<<4); | |
1383 | reg_write(lynx, DMA_WORD1_CMP_VALUE(CHANNEL_ASYNC_RCV), 0); | |
1384 | reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ASYNC_RCV), | |
1385 | DMA_WORD1_CMP_MATCH_LOCAL_NODE | DMA_WORD1_CMP_MATCH_BROADCAST | |
1386 | | DMA_WORD1_CMP_MATCH_EXACT | DMA_WORD1_CMP_MATCH_BUS_BCAST | |
1387 | | DMA_WORD1_CMP_ENABLE_SELF_ID | DMA_WORD1_CMP_ENABLE_MASTER); | |
1388 | ||
1389 | run_pcl(lynx, lynx->rcv_pcl_start, CHANNEL_ASYNC_RCV); | |
1390 | ||
1391 | reg_write(lynx, DMA_WORD0_CMP_VALUE(CHANNEL_ISO_RCV), 0); | |
1392 | reg_write(lynx, DMA_WORD0_CMP_ENABLE(CHANNEL_ISO_RCV), 0x9<<4); | |
1393 | reg_write(lynx, DMA_WORD1_CMP_VALUE(CHANNEL_ISO_RCV), 0); | |
1394 | reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), 0); | |
1395 | ||
1396 | run_sub_pcl(lynx, lynx->iso_rcv.pcl_start, 0, CHANNEL_ISO_RCV); | |
1397 | ||
1398 | reg_write(lynx, LINK_CONTROL, LINK_CONTROL_RCV_CMP_VALID | |
1399 | | LINK_CONTROL_TX_ISO_EN | LINK_CONTROL_RX_ISO_EN | |
1400 | | LINK_CONTROL_TX_ASYNC_EN | LINK_CONTROL_RX_ASYNC_EN | |
1401 | | LINK_CONTROL_RESET_TX | LINK_CONTROL_RESET_RX); | |
1402 | ||
1403 | if (!lynx->phyic.reg_1394a) { | |
1404 | if (!hpsb_disable_irm) { | |
1405 | /* attempt to enable contender bit -FIXME- would this | |
1406 | * work elsewhere? */ | |
1407 | reg_set_bits(lynx, GPIO_CTRL_A, 0x1); | |
1408 | reg_write(lynx, GPIO_DATA_BASE + 0x3c, 0x1); | |
1409 | } | |
1410 | } else { | |
1411 | /* set the contender (if appropriate) and LCtrl bit in the | |
1412 | * extended PHY register set. (Should check that PHY_02_EXTENDED | |
1413 | * is set in register 2?) | |
1414 | */ | |
1415 | i = get_phy_reg(lynx, 4); | |
1416 | i |= PHY_04_LCTRL; | |
1417 | if (hpsb_disable_irm) | |
1934b8b6 | 1418 | i &= ~PHY_04_CONTENDER; |
1da177e4 LT |
1419 | else |
1420 | i |= PHY_04_CONTENDER; | |
1421 | if (i != -1) set_phy_reg(lynx, 4, i); | |
1422 | } | |
1423 | ||
1424 | if (!skip_eeprom) | |
1425 | { | |
1426 | /* needed for i2c communication with serial eeprom */ | |
1427 | struct i2c_adapter *i2c_ad; | |
1428 | struct i2c_algo_bit_data i2c_adapter_data; | |
1429 | ||
1430 | error = -ENOMEM; | |
bfe89d72 | 1431 | i2c_ad = kmemdup(&bit_ops, sizeof(*i2c_ad), GFP_KERNEL); |
1da177e4 LT |
1432 | if (!i2c_ad) FAIL("failed to allocate I2C adapter memory"); |
1433 | ||
1da177e4 LT |
1434 | i2c_adapter_data = bit_data; |
1435 | i2c_ad->algo_data = &i2c_adapter_data; | |
1436 | i2c_adapter_data.data = lynx; | |
12a917f6 | 1437 | i2c_ad->dev.parent = &dev->dev; |
1da177e4 LT |
1438 | |
1439 | PRINTD(KERN_DEBUG, lynx->id,"original eeprom control: %d", | |
1440 | reg_read(lynx, SERIAL_EEPROM_CONTROL)); | |
1441 | ||
1442 | /* reset hardware to sane state */ | |
1443 | lynx->i2c_driven_state = 0x00000070; | |
1444 | reg_write(lynx, SERIAL_EEPROM_CONTROL, lynx->i2c_driven_state); | |
1445 | ||
1446 | if (i2c_bit_add_bus(i2c_ad) < 0) | |
1447 | { | |
1448 | kfree(i2c_ad); | |
1449 | error = -ENXIO; | |
1450 | FAIL("unable to register i2c"); | |
1451 | } | |
1452 | else | |
1453 | { | |
1454 | /* do i2c stuff */ | |
1455 | unsigned char i2c_cmd = 0x10; | |
1456 | struct i2c_msg msg[2] = { { 0x50, 0, 1, &i2c_cmd }, | |
1457 | { 0x50, I2C_M_RD, 20, (unsigned char*) lynx->bus_info_block } | |
1458 | }; | |
1459 | ||
1da177e4 LT |
1460 | /* we use i2c_transfer, because i2c_smbus_read_block_data does not work properly and we |
1461 | do it more efficiently in one transaction rather then using several reads */ | |
1462 | if (i2c_transfer(i2c_ad, msg, 2) < 0) { | |
1463 | PRINT(KERN_ERR, lynx->id, "unable to read bus info block from i2c"); | |
1464 | } else { | |
1465 | int i; | |
1466 | ||
1467 | PRINT(KERN_INFO, lynx->id, "got bus info block from serial eeprom"); | |
1468 | /* FIXME: probably we shoud rewrite the max_rec, max_ROM(1394a), | |
1469 | * generation(1394a) and link_spd(1394a) field and recalculate | |
1470 | * the CRC */ | |
1471 | ||
1472 | for (i = 0; i < 5 ; i++) | |
1473 | PRINTD(KERN_DEBUG, lynx->id, "Businfo block quadlet %i: %08x", | |
1474 | i, be32_to_cpu(lynx->bus_info_block[i])); | |
1475 | ||
1476 | /* info_length, crc_length and 1394 magic number to check, if it is really a bus info block */ | |
1477 | if (((be32_to_cpu(lynx->bus_info_block[0]) & 0xffff0000) == 0x04040000) && | |
1478 | (lynx->bus_info_block[1] == __constant_cpu_to_be32(0x31333934))) | |
1479 | { | |
1480 | PRINT(KERN_DEBUG, lynx->id, "read a valid bus info block from"); | |
1481 | } else { | |
1482 | kfree(i2c_ad); | |
1483 | error = -ENXIO; | |
1484 | FAIL("read something from serial eeprom, but it does not seem to be a valid bus info block"); | |
1485 | } | |
1486 | ||
1487 | } | |
1488 | ||
3269711b | 1489 | i2c_del_adapter(i2c_ad); |
1da177e4 LT |
1490 | kfree(i2c_ad); |
1491 | } | |
1492 | } | |
1493 | ||
1494 | host->csr.guid_hi = be32_to_cpu(lynx->bus_info_block[3]); | |
1495 | host->csr.guid_lo = be32_to_cpu(lynx->bus_info_block[4]); | |
1496 | host->csr.cyc_clk_acc = (be32_to_cpu(lynx->bus_info_block[2]) >> 16) & 0xff; | |
1497 | host->csr.max_rec = (be32_to_cpu(lynx->bus_info_block[2]) >> 12) & 0xf; | |
1498 | if (!lynx->phyic.reg_1394a) | |
1499 | host->csr.lnk_spd = (get_phy_reg(lynx, 2) & 0xc0) >> 6; | |
1500 | else | |
1501 | host->csr.lnk_spd = be32_to_cpu(lynx->bus_info_block[2]) & 0x7; | |
1502 | ||
1503 | if (hpsb_add_host(host)) { | |
1504 | error = -ENOMEM; | |
1505 | FAIL("Failed to register host with highlevel"); | |
1506 | } | |
1507 | ||
1508 | lynx->state = is_host; | |
1509 | ||
1510 | return 0; | |
1511 | #undef FAIL | |
1512 | } | |
1513 | ||
1514 | ||
1515 | static struct pci_device_id pci_table[] = { | |
1516 | { | |
1517 | .vendor = PCI_VENDOR_ID_TI, | |
1518 | .device = PCI_DEVICE_ID_TI_PCILYNX, | |
1519 | .subvendor = PCI_ANY_ID, | |
1520 | .subdevice = PCI_ANY_ID, | |
1521 | }, | |
1522 | { } /* Terminating entry */ | |
1523 | }; | |
1524 | ||
1525 | static struct pci_driver lynx_pci_driver = { | |
1526 | .name = PCILYNX_DRIVER_NAME, | |
1527 | .id_table = pci_table, | |
1528 | .probe = add_card, | |
1529 | .remove = remove_card, | |
1530 | }; | |
1531 | ||
1532 | static struct hpsb_host_driver lynx_driver = { | |
1533 | .owner = THIS_MODULE, | |
1534 | .name = PCILYNX_DRIVER_NAME, | |
1535 | .set_hw_config_rom = NULL, | |
1536 | .transmit_packet = lynx_transmit, | |
1537 | .devctl = lynx_devctl, | |
1538 | .isoctl = NULL, | |
1539 | }; | |
1540 | ||
1541 | MODULE_AUTHOR("Andreas E. Bombe <andreas.bombe@munich.netsurf.de>"); | |
1542 | MODULE_DESCRIPTION("driver for Texas Instruments PCI Lynx IEEE-1394 controller"); | |
1543 | MODULE_LICENSE("GPL"); | |
1544 | MODULE_SUPPORTED_DEVICE("pcilynx"); | |
1545 | MODULE_DEVICE_TABLE(pci, pci_table); | |
1546 | ||
1547 | static int __init pcilynx_init(void) | |
1548 | { | |
1549 | int ret; | |
1550 | ||
1da177e4 LT |
1551 | ret = pci_register_driver(&lynx_pci_driver); |
1552 | if (ret < 0) { | |
1553 | PRINT_G(KERN_ERR, "PCI module init failed"); | |
f72cd138 | 1554 | return ret; |
1da177e4 LT |
1555 | } |
1556 | ||
1557 | return 0; | |
1da177e4 LT |
1558 | } |
1559 | ||
1560 | static void __exit pcilynx_cleanup(void) | |
1561 | { | |
1562 | pci_unregister_driver(&lynx_pci_driver); | |
1da177e4 LT |
1563 | } |
1564 | ||
1565 | ||
1566 | module_init(pcilynx_init); | |
1567 | module_exit(pcilynx_cleanup); |