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Commit | Line | Data |
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fdadbce0 OK |
1 | /* |
2 | * bma180.c - IIO driver for Bosch BMA180 triaxial acceleration sensor | |
3 | * | |
4 | * Copyright 2013 Oleksandr Kravchenko <x0199363@ti.com> | |
5 | * | |
2017cff2 PM |
6 | * Support for BMA250 (c) Peter Meerwald <pmeerw@pmeerw.net> |
7 | * | |
fdadbce0 OK |
8 | * This file is subject to the terms and conditions of version 2 of |
9 | * the GNU General Public License. See the file COPYING in the main | |
10 | * directory of this archive for more details. | |
2017cff2 PM |
11 | * |
12 | * SPI is not supported by driver | |
13 | * BMA180: 7-bit I2C slave address 0x40 or 0x41 | |
14 | * BMA250: 7-bit I2C slave address 0x18 or 0x19 | |
fdadbce0 OK |
15 | */ |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/i2c.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/iio/iio.h> | |
26 | #include <linux/iio/sysfs.h> | |
27 | #include <linux/iio/buffer.h> | |
28 | #include <linux/iio/trigger.h> | |
29 | #include <linux/iio/trigger_consumer.h> | |
30 | #include <linux/iio/triggered_buffer.h> | |
31 | ||
32 | #define BMA180_DRV_NAME "bma180" | |
33 | #define BMA180_IRQ_NAME "bma180_event" | |
34 | ||
1b9030f5 PM |
35 | enum { |
36 | BMA180, | |
2017cff2 | 37 | BMA250, |
1b9030f5 PM |
38 | }; |
39 | ||
c1949ec1 PM |
40 | struct bma180_data; |
41 | ||
1b9030f5 PM |
42 | struct bma180_part_info { |
43 | const struct iio_chan_spec *channels; | |
44 | unsigned num_channels; | |
45 | const int *scale_table; | |
46 | unsigned num_scales; | |
47 | const int *bw_table; | |
48 | unsigned num_bw; | |
2017cff2 PM |
49 | |
50 | u8 int_reset_reg, int_reset_mask; | |
51 | u8 sleep_reg, sleep_mask; | |
52 | u8 bw_reg, bw_mask; | |
53 | u8 scale_reg, scale_mask; | |
54 | u8 power_reg, power_mask, lowpower_val; | |
55 | u8 int_enable_reg, int_enable_mask; | |
56 | u8 softreset_reg; | |
57 | ||
c1949ec1 PM |
58 | int (*chip_config)(struct bma180_data *data); |
59 | void (*chip_disable)(struct bma180_data *data); | |
1b9030f5 PM |
60 | }; |
61 | ||
fdadbce0 OK |
62 | /* Register set */ |
63 | #define BMA180_CHIP_ID 0x00 /* Need to distinguish BMA180 from other */ | |
64 | #define BMA180_ACC_X_LSB 0x02 /* First of 6 registers of accel data */ | |
b81fbab7 | 65 | #define BMA180_TEMP 0x08 |
fdadbce0 OK |
66 | #define BMA180_CTRL_REG0 0x0d |
67 | #define BMA180_RESET 0x10 | |
68 | #define BMA180_BW_TCS 0x20 | |
69 | #define BMA180_CTRL_REG3 0x21 | |
70 | #define BMA180_TCO_Z 0x30 | |
71 | #define BMA180_OFFSET_LSB1 0x35 | |
72 | ||
73 | /* BMA180_CTRL_REG0 bits */ | |
74 | #define BMA180_DIS_WAKE_UP BIT(0) /* Disable wake up mode */ | |
75 | #define BMA180_SLEEP BIT(1) /* 1 - chip will sleep */ | |
76 | #define BMA180_EE_W BIT(4) /* Unlock writing to addr from 0x20 */ | |
77 | #define BMA180_RESET_INT BIT(6) /* Reset pending interrupts */ | |
78 | ||
79 | /* BMA180_CTRL_REG3 bits */ | |
80 | #define BMA180_NEW_DATA_INT BIT(1) /* Intr every new accel data is ready */ | |
81 | ||
82 | /* BMA180_OFFSET_LSB1 skipping mode bit */ | |
83 | #define BMA180_SMP_SKIP BIT(0) | |
84 | ||
85 | /* Bit masks for registers bit fields */ | |
cab767d5 | 86 | #define BMA180_RANGE 0x0e /* Range of measured accel values */ |
fdadbce0 OK |
87 | #define BMA180_BW 0xf0 /* Accel bandwidth */ |
88 | #define BMA180_MODE_CONFIG 0x03 /* Config operation modes */ | |
89 | ||
90 | /* We have to write this value in reset register to do soft reset */ | |
91 | #define BMA180_RESET_VAL 0xb6 | |
92 | ||
9a70b147 | 93 | #define BMA180_ID_REG_VAL 0x03 |
fdadbce0 OK |
94 | |
95 | /* Chip power modes */ | |
fdadbce0 OK |
96 | #define BMA180_LOW_POWER 0x03 |
97 | ||
2017cff2 PM |
98 | #define BMA250_RANGE_REG 0x0f |
99 | #define BMA250_BW_REG 0x10 | |
100 | #define BMA250_POWER_REG 0x11 | |
101 | #define BMA250_RESET_REG 0x14 | |
102 | #define BMA250_INT_ENABLE_REG 0x17 | |
103 | #define BMA250_INT_MAP_REG 0x1a | |
104 | #define BMA250_INT_RESET_REG 0x21 | |
105 | ||
106 | #define BMA250_RANGE_MASK GENMASK(3, 0) /* Range of accel values */ | |
107 | #define BMA250_BW_MASK GENMASK(4, 0) /* Accel bandwidth */ | |
108 | #define BMA250_SUSPEND_MASK BIT(7) /* chip will sleep */ | |
109 | #define BMA250_LOWPOWER_MASK BIT(6) | |
110 | #define BMA250_DATA_INTEN_MASK BIT(4) | |
111 | #define BMA250_INT1_DATA_MASK BIT(0) | |
112 | #define BMA250_INT_RESET_MASK BIT(7) /* Reset pending interrupts */ | |
fdadbce0 | 113 | |
fdadbce0 OK |
114 | struct bma180_data { |
115 | struct i2c_client *client; | |
116 | struct iio_trigger *trig; | |
1b9030f5 | 117 | const struct bma180_part_info *part_info; |
fdadbce0 | 118 | struct mutex mutex; |
c7c69e85 | 119 | bool sleep_state; |
fdadbce0 OK |
120 | int scale; |
121 | int bw; | |
c7c69e85 | 122 | bool pmode; |
b9a6a237 | 123 | u8 buff[16]; /* 3x 16-bit + 8-bit + padding + timestamp */ |
fdadbce0 OK |
124 | }; |
125 | ||
b81fbab7 | 126 | enum bma180_chan { |
fdadbce0 OK |
127 | AXIS_X, |
128 | AXIS_Y, | |
129 | AXIS_Z, | |
b81fbab7 | 130 | TEMP |
fdadbce0 OK |
131 | }; |
132 | ||
cab767d5 PM |
133 | static int bma180_bw_table[] = { 10, 20, 40, 75, 150, 300 }; /* Hz */ |
134 | static int bma180_scale_table[] = { 1275, 1863, 2452, 3727, 4903, 9709, 19417 }; | |
fdadbce0 | 135 | |
2017cff2 PM |
136 | static int bma250_bw_table[] = { 8, 16, 31, 63, 125, 250 }; /* Hz */ |
137 | static int bma250_scale_table[] = { 0, 0, 0, 38344, 0, 76590, 0, 0, 153180, 0, | |
138 | 0, 0, 306458 }; | |
139 | ||
b81fbab7 | 140 | static int bma180_get_data_reg(struct bma180_data *data, enum bma180_chan chan) |
fdadbce0 | 141 | { |
fdadbce0 OK |
142 | int ret; |
143 | ||
144 | if (data->sleep_state) | |
145 | return -EBUSY; | |
146 | ||
b81fbab7 PM |
147 | switch (chan) { |
148 | case TEMP: | |
149 | ret = i2c_smbus_read_byte_data(data->client, BMA180_TEMP); | |
150 | if (ret < 0) | |
151 | dev_err(&data->client->dev, "failed to read temp register\n"); | |
152 | break; | |
153 | default: | |
154 | ret = i2c_smbus_read_word_data(data->client, | |
155 | BMA180_ACC_X_LSB + chan * 2); | |
156 | if (ret < 0) | |
157 | dev_err(&data->client->dev, | |
158 | "failed to read accel_%c register\n", | |
159 | 'x' + chan); | |
160 | } | |
fdadbce0 OK |
161 | |
162 | return ret; | |
163 | } | |
164 | ||
165 | static int bma180_set_bits(struct bma180_data *data, u8 reg, u8 mask, u8 val) | |
166 | { | |
167 | int ret = i2c_smbus_read_byte_data(data->client, reg); | |
168 | u8 reg_val = (ret & ~mask) | (val << (ffs(mask) - 1)); | |
169 | ||
170 | if (ret < 0) | |
171 | return ret; | |
172 | ||
173 | return i2c_smbus_write_byte_data(data->client, reg, reg_val); | |
174 | } | |
175 | ||
176 | static int bma180_reset_intr(struct bma180_data *data) | |
177 | { | |
2017cff2 PM |
178 | int ret = bma180_set_bits(data, data->part_info->int_reset_reg, |
179 | data->part_info->int_reset_mask, 1); | |
fdadbce0 OK |
180 | |
181 | if (ret) | |
182 | dev_err(&data->client->dev, "failed to reset interrupt\n"); | |
183 | ||
184 | return ret; | |
185 | } | |
186 | ||
c7c69e85 | 187 | static int bma180_set_new_data_intr_state(struct bma180_data *data, bool state) |
fdadbce0 | 188 | { |
2017cff2 PM |
189 | int ret = bma180_set_bits(data, data->part_info->int_enable_reg, |
190 | data->part_info->int_enable_mask, state); | |
fdadbce0 OK |
191 | if (ret) |
192 | goto err; | |
193 | ret = bma180_reset_intr(data); | |
194 | if (ret) | |
195 | goto err; | |
196 | ||
197 | return 0; | |
198 | ||
199 | err: | |
200 | dev_err(&data->client->dev, | |
201 | "failed to set new data interrupt state %d\n", state); | |
202 | return ret; | |
203 | } | |
204 | ||
c7c69e85 | 205 | static int bma180_set_sleep_state(struct bma180_data *data, bool state) |
fdadbce0 | 206 | { |
2017cff2 PM |
207 | int ret = bma180_set_bits(data, data->part_info->sleep_reg, |
208 | data->part_info->sleep_mask, state); | |
fdadbce0 OK |
209 | |
210 | if (ret) { | |
211 | dev_err(&data->client->dev, | |
212 | "failed to set sleep state %d\n", state); | |
213 | return ret; | |
214 | } | |
215 | data->sleep_state = state; | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
c7c69e85 | 220 | static int bma180_set_ee_writing_state(struct bma180_data *data, bool state) |
fdadbce0 OK |
221 | { |
222 | int ret = bma180_set_bits(data, BMA180_CTRL_REG0, BMA180_EE_W, state); | |
223 | ||
224 | if (ret) | |
225 | dev_err(&data->client->dev, | |
226 | "failed to set ee writing state %d\n", state); | |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
231 | static int bma180_set_bw(struct bma180_data *data, int val) | |
232 | { | |
233 | int ret, i; | |
234 | ||
235 | if (data->sleep_state) | |
236 | return -EBUSY; | |
237 | ||
1b9030f5 PM |
238 | for (i = 0; i < data->part_info->num_bw; ++i) { |
239 | if (data->part_info->bw_table[i] == val) { | |
2017cff2 PM |
240 | ret = bma180_set_bits(data, data->part_info->bw_reg, |
241 | data->part_info->bw_mask, i); | |
fdadbce0 OK |
242 | if (ret) { |
243 | dev_err(&data->client->dev, | |
244 | "failed to set bandwidth\n"); | |
245 | return ret; | |
246 | } | |
247 | data->bw = val; | |
248 | return 0; | |
249 | } | |
250 | } | |
251 | ||
252 | return -EINVAL; | |
253 | } | |
254 | ||
255 | static int bma180_set_scale(struct bma180_data *data, int val) | |
256 | { | |
257 | int ret, i; | |
258 | ||
259 | if (data->sleep_state) | |
260 | return -EBUSY; | |
261 | ||
1b9030f5 PM |
262 | for (i = 0; i < data->part_info->num_scales; ++i) |
263 | if (data->part_info->scale_table[i] == val) { | |
2017cff2 PM |
264 | ret = bma180_set_bits(data, data->part_info->scale_reg, |
265 | data->part_info->scale_mask, i); | |
fdadbce0 OK |
266 | if (ret) { |
267 | dev_err(&data->client->dev, | |
268 | "failed to set scale\n"); | |
269 | return ret; | |
270 | } | |
271 | data->scale = val; | |
272 | return 0; | |
273 | } | |
274 | ||
275 | return -EINVAL; | |
276 | } | |
277 | ||
c7c69e85 | 278 | static int bma180_set_pmode(struct bma180_data *data, bool mode) |
fdadbce0 | 279 | { |
2017cff2 PM |
280 | u8 reg_val = mode ? data->part_info->lowpower_val : 0; |
281 | int ret = bma180_set_bits(data, data->part_info->power_reg, | |
282 | data->part_info->power_mask, reg_val); | |
fdadbce0 OK |
283 | |
284 | if (ret) { | |
285 | dev_err(&data->client->dev, "failed to set power mode\n"); | |
286 | return ret; | |
287 | } | |
288 | data->pmode = mode; | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static int bma180_soft_reset(struct bma180_data *data) | |
294 | { | |
295 | int ret = i2c_smbus_write_byte_data(data->client, | |
2017cff2 | 296 | data->part_info->softreset_reg, BMA180_RESET_VAL); |
fdadbce0 OK |
297 | |
298 | if (ret) | |
299 | dev_err(&data->client->dev, "failed to reset the chip\n"); | |
300 | ||
301 | return ret; | |
302 | } | |
303 | ||
304 | static int bma180_chip_init(struct bma180_data *data) | |
305 | { | |
306 | /* Try to read chip_id register. It must return 0x03. */ | |
307 | int ret = i2c_smbus_read_byte_data(data->client, BMA180_CHIP_ID); | |
308 | ||
309 | if (ret < 0) | |
c1949ec1 PM |
310 | return ret; |
311 | if (ret != BMA180_ID_REG_VAL) | |
312 | return -ENODEV; | |
fdadbce0 OK |
313 | |
314 | ret = bma180_soft_reset(data); | |
315 | if (ret) | |
c1949ec1 | 316 | return ret; |
fdadbce0 OK |
317 | /* |
318 | * No serial transaction should occur within minimum 10 us | |
319 | * after soft_reset command | |
320 | */ | |
321 | msleep(20); | |
322 | ||
2017cff2 PM |
323 | ret = bma180_set_new_data_intr_state(data, false); |
324 | if (ret) | |
325 | return ret; | |
326 | ||
327 | return bma180_set_pmode(data, false); | |
c1949ec1 PM |
328 | } |
329 | ||
330 | static int bma180_chip_config(struct bma180_data *data) | |
331 | { | |
332 | int ret = bma180_chip_init(data); | |
333 | ||
334 | if (ret) | |
335 | goto err; | |
fdadbce0 OK |
336 | ret = bma180_set_bits(data, BMA180_CTRL_REG0, BMA180_DIS_WAKE_UP, 1); |
337 | if (ret) | |
338 | goto err; | |
c7c69e85 | 339 | ret = bma180_set_ee_writing_state(data, true); |
fdadbce0 OK |
340 | if (ret) |
341 | goto err; | |
2017cff2 | 342 | ret = bma180_set_bits(data, BMA180_OFFSET_LSB1, BMA180_SMP_SKIP, 1); |
fdadbce0 OK |
343 | if (ret) |
344 | goto err; | |
2017cff2 | 345 | ret = bma180_set_bw(data, 20); /* 20 Hz */ |
fdadbce0 OK |
346 | if (ret) |
347 | goto err; | |
2017cff2 | 348 | ret = bma180_set_scale(data, 2452); /* 2 G */ |
fdadbce0 OK |
349 | if (ret) |
350 | goto err; | |
2017cff2 PM |
351 | |
352 | return 0; | |
353 | ||
354 | err: | |
355 | dev_err(&data->client->dev, "failed to config the chip\n"); | |
356 | return ret; | |
357 | } | |
358 | ||
359 | static int bma250_chip_config(struct bma180_data *data) | |
360 | { | |
361 | int ret = bma180_chip_init(data); | |
362 | ||
363 | if (ret) | |
364 | goto err; | |
365 | ret = bma180_set_bw(data, 16); /* 16 Hz */ | |
fdadbce0 OK |
366 | if (ret) |
367 | goto err; | |
2017cff2 PM |
368 | ret = bma180_set_scale(data, 38344); /* 2 G */ |
369 | if (ret) | |
370 | goto err; | |
371 | ret = bma180_set_bits(data, BMA250_INT_MAP_REG, | |
372 | BMA250_INT1_DATA_MASK, 1); | |
fdadbce0 OK |
373 | if (ret) |
374 | goto err; | |
375 | ||
376 | return 0; | |
377 | ||
378 | err: | |
c1949ec1 | 379 | dev_err(&data->client->dev, "failed to config the chip\n"); |
fdadbce0 OK |
380 | return ret; |
381 | } | |
382 | ||
383 | static void bma180_chip_disable(struct bma180_data *data) | |
384 | { | |
c7c69e85 | 385 | if (bma180_set_new_data_intr_state(data, false)) |
fdadbce0 | 386 | goto err; |
c7c69e85 | 387 | if (bma180_set_ee_writing_state(data, false)) |
fdadbce0 | 388 | goto err; |
c7c69e85 | 389 | if (bma180_set_sleep_state(data, true)) |
fdadbce0 OK |
390 | goto err; |
391 | ||
392 | return; | |
393 | ||
394 | err: | |
395 | dev_err(&data->client->dev, "failed to disable the chip\n"); | |
396 | } | |
397 | ||
2017cff2 PM |
398 | static void bma250_chip_disable(struct bma180_data *data) |
399 | { | |
400 | if (bma180_set_new_data_intr_state(data, false)) | |
401 | goto err; | |
402 | if (bma180_set_sleep_state(data, true)) | |
403 | goto err; | |
404 | ||
405 | return; | |
406 | ||
407 | err: | |
408 | dev_err(&data->client->dev, "failed to disable the chip\n"); | |
409 | } | |
410 | ||
402a324e PM |
411 | static ssize_t bma180_show_avail(char *buf, const int *vals, unsigned n, |
412 | bool micros) | |
413 | { | |
414 | size_t len = 0; | |
415 | int i; | |
416 | ||
417 | for (i = 0; i < n; i++) { | |
418 | if (!vals[i]) | |
419 | continue; | |
420 | len += scnprintf(buf + len, PAGE_SIZE - len, | |
421 | micros ? "0.%06d " : "%d ", vals[i]); | |
422 | } | |
423 | buf[len - 1] = '\n'; | |
424 | ||
425 | return len; | |
426 | } | |
427 | ||
428 | static ssize_t bma180_show_filter_freq_avail(struct device *dev, | |
429 | struct device_attribute *attr, char *buf) | |
430 | { | |
431 | struct bma180_data *data = iio_priv(dev_to_iio_dev(dev)); | |
432 | ||
433 | return bma180_show_avail(buf, data->part_info->bw_table, | |
434 | data->part_info->num_bw, false); | |
435 | } | |
436 | ||
437 | static ssize_t bma180_show_scale_avail(struct device *dev, | |
438 | struct device_attribute *attr, char *buf) | |
439 | { | |
440 | struct bma180_data *data = iio_priv(dev_to_iio_dev(dev)); | |
441 | ||
442 | return bma180_show_avail(buf, data->part_info->scale_table, | |
443 | data->part_info->num_scales, true); | |
444 | } | |
445 | ||
446 | static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available, | |
447 | S_IRUGO, bma180_show_filter_freq_avail, NULL, 0); | |
448 | ||
449 | static IIO_DEVICE_ATTR(in_accel_scale_available, | |
450 | S_IRUGO, bma180_show_scale_avail, NULL, 0); | |
fdadbce0 OK |
451 | |
452 | static struct attribute *bma180_attributes[] = { | |
402a324e PM |
453 | &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available. |
454 | dev_attr.attr, | |
455 | &iio_dev_attr_in_accel_scale_available.dev_attr.attr, | |
fdadbce0 OK |
456 | NULL, |
457 | }; | |
458 | ||
459 | static const struct attribute_group bma180_attrs_group = { | |
460 | .attrs = bma180_attributes, | |
461 | }; | |
462 | ||
463 | static int bma180_read_raw(struct iio_dev *indio_dev, | |
464 | struct iio_chan_spec const *chan, int *val, int *val2, | |
465 | long mask) | |
466 | { | |
467 | struct bma180_data *data = iio_priv(indio_dev); | |
468 | int ret; | |
469 | ||
470 | switch (mask) { | |
471 | case IIO_CHAN_INFO_RAW: | |
472 | mutex_lock(&data->mutex); | |
b81fbab7 PM |
473 | if (iio_buffer_enabled(indio_dev)) { |
474 | mutex_unlock(&data->mutex); | |
475 | return -EBUSY; | |
476 | } | |
477 | ret = bma180_get_data_reg(data, chan->scan_index); | |
fdadbce0 OK |
478 | mutex_unlock(&data->mutex); |
479 | if (ret < 0) | |
480 | return ret; | |
b81fbab7 PM |
481 | *val = sign_extend32(ret >> chan->scan_type.shift, |
482 | chan->scan_type.realbits - 1); | |
fdadbce0 OK |
483 | return IIO_VAL_INT; |
484 | case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: | |
485 | *val = data->bw; | |
486 | return IIO_VAL_INT; | |
487 | case IIO_CHAN_INFO_SCALE: | |
b81fbab7 PM |
488 | switch (chan->type) { |
489 | case IIO_ACCEL: | |
490 | *val = 0; | |
491 | *val2 = data->scale; | |
492 | return IIO_VAL_INT_PLUS_MICRO; | |
493 | case IIO_TEMP: | |
494 | *val = 500; | |
495 | return IIO_VAL_INT; | |
496 | default: | |
497 | return -EINVAL; | |
498 | } | |
499 | case IIO_CHAN_INFO_OFFSET: | |
500 | *val = 48; /* 0 LSB @ 24 degree C */ | |
501 | return IIO_VAL_INT; | |
fdadbce0 OK |
502 | default: |
503 | return -EINVAL; | |
504 | } | |
505 | } | |
506 | ||
507 | static int bma180_write_raw(struct iio_dev *indio_dev, | |
508 | struct iio_chan_spec const *chan, int val, int val2, long mask) | |
509 | { | |
510 | struct bma180_data *data = iio_priv(indio_dev); | |
511 | int ret; | |
512 | ||
513 | switch (mask) { | |
514 | case IIO_CHAN_INFO_SCALE: | |
515 | if (val) | |
516 | return -EINVAL; | |
517 | mutex_lock(&data->mutex); | |
518 | ret = bma180_set_scale(data, val2); | |
519 | mutex_unlock(&data->mutex); | |
520 | return ret; | |
521 | case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: | |
9b2a4d35 PM |
522 | if (val2) |
523 | return -EINVAL; | |
fdadbce0 OK |
524 | mutex_lock(&data->mutex); |
525 | ret = bma180_set_bw(data, val); | |
526 | mutex_unlock(&data->mutex); | |
527 | return ret; | |
528 | default: | |
529 | return -EINVAL; | |
530 | } | |
531 | } | |
532 | ||
fdadbce0 OK |
533 | static const struct iio_info bma180_info = { |
534 | .attrs = &bma180_attrs_group, | |
535 | .read_raw = bma180_read_raw, | |
536 | .write_raw = bma180_write_raw, | |
fdadbce0 OK |
537 | .driver_module = THIS_MODULE, |
538 | }; | |
539 | ||
c7c69e85 | 540 | static const char * const bma180_power_modes[] = { "low_noise", "low_power" }; |
fdadbce0 OK |
541 | |
542 | static int bma180_get_power_mode(struct iio_dev *indio_dev, | |
543 | const struct iio_chan_spec *chan) | |
544 | { | |
545 | struct bma180_data *data = iio_priv(indio_dev); | |
546 | ||
547 | return data->pmode; | |
548 | } | |
549 | ||
550 | static int bma180_set_power_mode(struct iio_dev *indio_dev, | |
551 | const struct iio_chan_spec *chan, unsigned int mode) | |
552 | { | |
553 | struct bma180_data *data = iio_priv(indio_dev); | |
554 | int ret; | |
555 | ||
556 | mutex_lock(&data->mutex); | |
557 | ret = bma180_set_pmode(data, mode); | |
558 | mutex_unlock(&data->mutex); | |
559 | ||
560 | return ret; | |
561 | } | |
562 | ||
563 | static const struct iio_enum bma180_power_mode_enum = { | |
564 | .items = bma180_power_modes, | |
565 | .num_items = ARRAY_SIZE(bma180_power_modes), | |
566 | .get = bma180_get_power_mode, | |
567 | .set = bma180_set_power_mode, | |
568 | }; | |
569 | ||
570 | static const struct iio_chan_spec_ext_info bma180_ext_info[] = { | |
571 | IIO_ENUM("power_mode", true, &bma180_power_mode_enum), | |
572 | IIO_ENUM_AVAILABLE("power_mode", &bma180_power_mode_enum), | |
573 | { }, | |
574 | }; | |
575 | ||
6377aa49 | 576 | #define BMA180_ACC_CHANNEL(_axis, _bits) { \ |
fdadbce0 | 577 | .type = IIO_ACCEL, \ |
5585215b PM |
578 | .modified = 1, \ |
579 | .channel2 = IIO_MOD_##_axis, \ | |
5c1449d4 PM |
580 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
581 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ | |
fdadbce0 | 582 | BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ |
5585215b | 583 | .scan_index = AXIS_##_axis, \ |
7d7feae7 JC |
584 | .scan_type = { \ |
585 | .sign = 's', \ | |
6377aa49 | 586 | .realbits = _bits, \ |
7d7feae7 | 587 | .storagebits = 16, \ |
6377aa49 | 588 | .shift = 16 - _bits, \ |
7d7feae7 | 589 | }, \ |
fdadbce0 OK |
590 | .ext_info = bma180_ext_info, \ |
591 | } | |
592 | ||
b81fbab7 PM |
593 | #define BMA180_TEMP_CHANNEL { \ |
594 | .type = IIO_TEMP, \ | |
595 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ | |
596 | BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), \ | |
597 | .scan_index = TEMP, \ | |
598 | .scan_type = { \ | |
599 | .sign = 's', \ | |
600 | .realbits = 8, \ | |
601 | .storagebits = 16, \ | |
602 | }, \ | |
603 | } | |
604 | ||
fdadbce0 | 605 | static const struct iio_chan_spec bma180_channels[] = { |
6377aa49 PM |
606 | BMA180_ACC_CHANNEL(X, 14), |
607 | BMA180_ACC_CHANNEL(Y, 14), | |
608 | BMA180_ACC_CHANNEL(Z, 14), | |
b81fbab7 PM |
609 | BMA180_TEMP_CHANNEL, |
610 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
fdadbce0 OK |
611 | }; |
612 | ||
2017cff2 PM |
613 | static const struct iio_chan_spec bma250_channels[] = { |
614 | BMA180_ACC_CHANNEL(X, 10), | |
615 | BMA180_ACC_CHANNEL(Y, 10), | |
616 | BMA180_ACC_CHANNEL(Z, 10), | |
617 | BMA180_TEMP_CHANNEL, | |
618 | IIO_CHAN_SOFT_TIMESTAMP(4), | |
619 | }; | |
620 | ||
1b9030f5 PM |
621 | static const struct bma180_part_info bma180_part_info[] = { |
622 | [BMA180] = { | |
623 | bma180_channels, ARRAY_SIZE(bma180_channels), | |
624 | bma180_scale_table, ARRAY_SIZE(bma180_scale_table), | |
625 | bma180_bw_table, ARRAY_SIZE(bma180_bw_table), | |
2017cff2 PM |
626 | BMA180_CTRL_REG0, BMA180_RESET_INT, |
627 | BMA180_CTRL_REG0, BMA180_SLEEP, | |
628 | BMA180_BW_TCS, BMA180_BW, | |
629 | BMA180_OFFSET_LSB1, BMA180_RANGE, | |
630 | BMA180_TCO_Z, BMA180_MODE_CONFIG, BMA180_LOW_POWER, | |
631 | BMA180_CTRL_REG3, BMA180_NEW_DATA_INT, | |
632 | BMA180_RESET, | |
c1949ec1 PM |
633 | bma180_chip_config, |
634 | bma180_chip_disable, | |
1b9030f5 | 635 | }, |
2017cff2 PM |
636 | [BMA250] = { |
637 | bma250_channels, ARRAY_SIZE(bma250_channels), | |
638 | bma250_scale_table, ARRAY_SIZE(bma250_scale_table), | |
639 | bma250_bw_table, ARRAY_SIZE(bma250_bw_table), | |
640 | BMA250_INT_RESET_REG, BMA250_INT_RESET_MASK, | |
641 | BMA250_POWER_REG, BMA250_SUSPEND_MASK, | |
642 | BMA250_BW_REG, BMA250_BW_MASK, | |
643 | BMA250_RANGE_REG, BMA250_RANGE_MASK, | |
644 | BMA250_POWER_REG, BMA250_LOWPOWER_MASK, 1, | |
645 | BMA250_INT_ENABLE_REG, BMA250_DATA_INTEN_MASK, | |
646 | BMA250_RESET_REG, | |
647 | bma250_chip_config, | |
648 | bma250_chip_disable, | |
649 | }, | |
1b9030f5 PM |
650 | }; |
651 | ||
fdadbce0 OK |
652 | static irqreturn_t bma180_trigger_handler(int irq, void *p) |
653 | { | |
654 | struct iio_poll_func *pf = p; | |
655 | struct iio_dev *indio_dev = pf->indio_dev; | |
656 | struct bma180_data *data = iio_priv(indio_dev); | |
6bf9d877 | 657 | int64_t time_ns = iio_get_time_ns(); |
fdadbce0 OK |
658 | int bit, ret, i = 0; |
659 | ||
660 | mutex_lock(&data->mutex); | |
fdadbce0 | 661 | |
70dddeee | 662 | for_each_set_bit(bit, indio_dev->active_scan_mask, |
fdadbce0 | 663 | indio_dev->masklength) { |
b81fbab7 | 664 | ret = bma180_get_data_reg(data, bit); |
fdadbce0 OK |
665 | if (ret < 0) { |
666 | mutex_unlock(&data->mutex); | |
667 | goto err; | |
668 | } | |
669 | ((s16 *)data->buff)[i++] = ret; | |
670 | } | |
b81fbab7 | 671 | |
fdadbce0 OK |
672 | mutex_unlock(&data->mutex); |
673 | ||
6bf9d877 | 674 | iio_push_to_buffers_with_timestamp(indio_dev, data->buff, time_ns); |
fdadbce0 OK |
675 | err: |
676 | iio_trigger_notify_done(indio_dev->trig); | |
677 | ||
678 | return IRQ_HANDLED; | |
679 | } | |
680 | ||
681 | static int bma180_data_rdy_trigger_set_state(struct iio_trigger *trig, | |
682 | bool state) | |
683 | { | |
684 | struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); | |
685 | struct bma180_data *data = iio_priv(indio_dev); | |
686 | ||
687 | return bma180_set_new_data_intr_state(data, state); | |
688 | } | |
689 | ||
690 | static int bma180_trig_try_reen(struct iio_trigger *trig) | |
691 | { | |
692 | struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); | |
693 | struct bma180_data *data = iio_priv(indio_dev); | |
694 | ||
695 | return bma180_reset_intr(data); | |
696 | } | |
697 | ||
698 | static const struct iio_trigger_ops bma180_trigger_ops = { | |
699 | .set_trigger_state = bma180_data_rdy_trigger_set_state, | |
700 | .try_reenable = bma180_trig_try_reen, | |
701 | .owner = THIS_MODULE, | |
702 | }; | |
703 | ||
704 | static int bma180_probe(struct i2c_client *client, | |
705 | const struct i2c_device_id *id) | |
706 | { | |
707 | struct bma180_data *data; | |
708 | struct iio_dev *indio_dev; | |
fdadbce0 OK |
709 | int ret; |
710 | ||
711 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); | |
712 | if (!indio_dev) | |
713 | return -ENOMEM; | |
714 | ||
715 | data = iio_priv(indio_dev); | |
716 | i2c_set_clientdata(client, indio_dev); | |
717 | data->client = client; | |
1b9030f5 | 718 | data->part_info = &bma180_part_info[id->driver_data]; |
fdadbce0 | 719 | |
c1949ec1 | 720 | ret = data->part_info->chip_config(data); |
fdadbce0 OK |
721 | if (ret < 0) |
722 | goto err_chip_disable; | |
723 | ||
724 | mutex_init(&data->mutex); | |
fdadbce0 | 725 | indio_dev->dev.parent = &client->dev; |
1b9030f5 PM |
726 | indio_dev->channels = data->part_info->channels; |
727 | indio_dev->num_channels = data->part_info->num_channels; | |
2017cff2 | 728 | indio_dev->name = id->name; |
fdadbce0 OK |
729 | indio_dev->modes = INDIO_DIRECT_MODE; |
730 | indio_dev->info = &bma180_info; | |
731 | ||
16ed8692 PM |
732 | if (client->irq > 0) { |
733 | data->trig = iio_trigger_alloc("%s-dev%d", indio_dev->name, | |
734 | indio_dev->id); | |
735 | if (!data->trig) { | |
736 | ret = -ENOMEM; | |
737 | goto err_chip_disable; | |
738 | } | |
fdadbce0 | 739 | |
16ed8692 PM |
740 | ret = devm_request_irq(&client->dev, client->irq, |
741 | iio_trigger_generic_data_rdy_poll, IRQF_TRIGGER_RISING, | |
2017cff2 | 742 | "bma180_event", data->trig); |
16ed8692 PM |
743 | if (ret) { |
744 | dev_err(&client->dev, "unable to request IRQ\n"); | |
745 | goto err_trigger_free; | |
746 | } | |
fdadbce0 | 747 | |
16ed8692 PM |
748 | data->trig->dev.parent = &client->dev; |
749 | data->trig->ops = &bma180_trigger_ops; | |
750 | iio_trigger_set_drvdata(data->trig, indio_dev); | |
8deab475 | 751 | indio_dev->trig = iio_trigger_get(data->trig); |
fdadbce0 | 752 | |
16ed8692 PM |
753 | ret = iio_trigger_register(data->trig); |
754 | if (ret) | |
755 | goto err_trigger_free; | |
756 | } | |
fdadbce0 OK |
757 | |
758 | ret = iio_triggered_buffer_setup(indio_dev, NULL, | |
759 | bma180_trigger_handler, NULL); | |
760 | if (ret < 0) { | |
761 | dev_err(&client->dev, "unable to setup iio triggered buffer\n"); | |
762 | goto err_trigger_unregister; | |
763 | } | |
764 | ||
765 | ret = iio_device_register(indio_dev); | |
766 | if (ret < 0) { | |
767 | dev_err(&client->dev, "unable to register iio device\n"); | |
768 | goto err_buffer_cleanup; | |
769 | } | |
770 | ||
771 | return 0; | |
772 | ||
773 | err_buffer_cleanup: | |
774 | iio_triggered_buffer_cleanup(indio_dev); | |
775 | err_trigger_unregister: | |
16ed8692 PM |
776 | if (data->trig) |
777 | iio_trigger_unregister(data->trig); | |
fdadbce0 | 778 | err_trigger_free: |
16ed8692 | 779 | iio_trigger_free(data->trig); |
fdadbce0 | 780 | err_chip_disable: |
c1949ec1 | 781 | data->part_info->chip_disable(data); |
fdadbce0 OK |
782 | |
783 | return ret; | |
784 | } | |
785 | ||
786 | static int bma180_remove(struct i2c_client *client) | |
787 | { | |
788 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | |
789 | struct bma180_data *data = iio_priv(indio_dev); | |
790 | ||
791 | iio_device_unregister(indio_dev); | |
792 | iio_triggered_buffer_cleanup(indio_dev); | |
16ed8692 PM |
793 | if (data->trig) { |
794 | iio_trigger_unregister(data->trig); | |
795 | iio_trigger_free(data->trig); | |
796 | } | |
fdadbce0 OK |
797 | |
798 | mutex_lock(&data->mutex); | |
c1949ec1 | 799 | data->part_info->chip_disable(data); |
fdadbce0 OK |
800 | mutex_unlock(&data->mutex); |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | #ifdef CONFIG_PM_SLEEP | |
806 | static int bma180_suspend(struct device *dev) | |
807 | { | |
234efa17 | 808 | struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); |
fdadbce0 OK |
809 | struct bma180_data *data = iio_priv(indio_dev); |
810 | int ret; | |
811 | ||
812 | mutex_lock(&data->mutex); | |
c7c69e85 | 813 | ret = bma180_set_sleep_state(data, true); |
fdadbce0 OK |
814 | mutex_unlock(&data->mutex); |
815 | ||
816 | return ret; | |
817 | } | |
818 | ||
819 | static int bma180_resume(struct device *dev) | |
820 | { | |
234efa17 | 821 | struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); |
fdadbce0 OK |
822 | struct bma180_data *data = iio_priv(indio_dev); |
823 | int ret; | |
824 | ||
825 | mutex_lock(&data->mutex); | |
c7c69e85 | 826 | ret = bma180_set_sleep_state(data, false); |
fdadbce0 OK |
827 | mutex_unlock(&data->mutex); |
828 | ||
829 | return ret; | |
830 | } | |
831 | ||
832 | static SIMPLE_DEV_PM_OPS(bma180_pm_ops, bma180_suspend, bma180_resume); | |
833 | #define BMA180_PM_OPS (&bma180_pm_ops) | |
834 | #else | |
835 | #define BMA180_PM_OPS NULL | |
836 | #endif | |
837 | ||
1b9030f5 | 838 | static struct i2c_device_id bma180_ids[] = { |
2017cff2 PM |
839 | { "bma180", BMA180 }, |
840 | { "bma250", BMA250 }, | |
fdadbce0 OK |
841 | { } |
842 | }; | |
843 | ||
1b9030f5 | 844 | MODULE_DEVICE_TABLE(i2c, bma180_ids); |
fdadbce0 OK |
845 | |
846 | static struct i2c_driver bma180_driver = { | |
847 | .driver = { | |
2017cff2 | 848 | .name = "bma180", |
fdadbce0 OK |
849 | .pm = BMA180_PM_OPS, |
850 | }, | |
851 | .probe = bma180_probe, | |
852 | .remove = bma180_remove, | |
1b9030f5 | 853 | .id_table = bma180_ids, |
fdadbce0 OK |
854 | }; |
855 | ||
856 | module_i2c_driver(bma180_driver); | |
857 | ||
858 | MODULE_AUTHOR("Kravchenko Oleksandr <x0199363@ti.com>"); | |
859 | MODULE_AUTHOR("Texas Instruments, Inc."); | |
2017cff2 | 860 | MODULE_DESCRIPTION("Bosch BMA180/BMA250 triaxial acceleration sensor"); |
fdadbce0 | 861 | MODULE_LICENSE("GPL"); |