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bd7fe5b7 | 1 | /* |
8ecbb3c3 LP |
2 | * 3-axis accelerometer driver supporting following Bosch-Sensortec chips: |
3 | * - BMC150 | |
4 | * - BMI055 | |
5 | * - BMA255 | |
6 | * - BMA250E | |
7 | * - BMA222E | |
8 | * - BMA280 | |
9 | * | |
bd7fe5b7 SP |
10 | * Copyright (c) 2014, Intel Corporation. |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms and conditions of the GNU General Public License, | |
14 | * version 2, as published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/acpi.h> | |
28 | #include <linux/gpio/consumer.h> | |
29 | #include <linux/pm.h> | |
30 | #include <linux/pm_runtime.h> | |
31 | #include <linux/iio/iio.h> | |
32 | #include <linux/iio/sysfs.h> | |
33 | #include <linux/iio/buffer.h> | |
34 | #include <linux/iio/events.h> | |
35 | #include <linux/iio/trigger.h> | |
36 | #include <linux/iio/trigger_consumer.h> | |
37 | #include <linux/iio/triggered_buffer.h> | |
38 | ||
39 | #define BMC150_ACCEL_DRV_NAME "bmc150_accel" | |
40 | #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" | |
41 | #define BMC150_ACCEL_GPIO_NAME "bmc150_accel_int" | |
42 | ||
43 | #define BMC150_ACCEL_REG_CHIP_ID 0x00 | |
bd7fe5b7 SP |
44 | |
45 | #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B | |
46 | #define BMC150_ACCEL_ANY_MOTION_MASK 0x07 | |
8d5a9781 SP |
47 | #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) |
48 | #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) | |
49 | #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) | |
bd7fe5b7 SP |
50 | #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) |
51 | ||
52 | #define BMC150_ACCEL_REG_PMU_LPW 0x11 | |
53 | #define BMC150_ACCEL_PMU_MODE_MASK 0xE0 | |
54 | #define BMC150_ACCEL_PMU_MODE_SHIFT 5 | |
55 | #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 | |
56 | #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 | |
57 | ||
58 | #define BMC150_ACCEL_REG_PMU_RANGE 0x0F | |
59 | ||
60 | #define BMC150_ACCEL_DEF_RANGE_2G 0x03 | |
61 | #define BMC150_ACCEL_DEF_RANGE_4G 0x05 | |
62 | #define BMC150_ACCEL_DEF_RANGE_8G 0x08 | |
63 | #define BMC150_ACCEL_DEF_RANGE_16G 0x0C | |
64 | ||
65 | /* Default BW: 125Hz */ | |
66 | #define BMC150_ACCEL_REG_PMU_BW 0x10 | |
67 | #define BMC150_ACCEL_DEF_BW 125 | |
68 | ||
69 | #define BMC150_ACCEL_REG_INT_MAP_0 0x19 | |
70 | #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) | |
71 | ||
72 | #define BMC150_ACCEL_REG_INT_MAP_1 0x1A | |
3bbec977 OP |
73 | #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) |
74 | #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) | |
75 | #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) | |
bd7fe5b7 SP |
76 | |
77 | #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 | |
78 | #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 | |
79 | #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F | |
80 | #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 | |
81 | ||
82 | #define BMC150_ACCEL_REG_INT_EN_0 0x16 | |
83 | #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) | |
84 | #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) | |
85 | #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) | |
86 | ||
87 | #define BMC150_ACCEL_REG_INT_EN_1 0x17 | |
3bbec977 OP |
88 | #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) |
89 | #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) | |
90 | #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) | |
bd7fe5b7 SP |
91 | |
92 | #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 | |
93 | #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) | |
94 | ||
95 | #define BMC150_ACCEL_REG_INT_5 0x27 | |
96 | #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 | |
97 | ||
98 | #define BMC150_ACCEL_REG_INT_6 0x28 | |
99 | #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF | |
100 | ||
101 | /* Slope duration in terms of number of samples */ | |
9e8e228f | 102 | #define BMC150_ACCEL_DEF_SLOPE_DURATION 1 |
bd7fe5b7 | 103 | /* in terms of multiples of g's/LSB, based on range */ |
9e8e228f | 104 | #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 |
bd7fe5b7 SP |
105 | |
106 | #define BMC150_ACCEL_REG_XOUT_L 0x02 | |
107 | ||
108 | #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 | |
109 | ||
110 | /* Sleep Duration values */ | |
111 | #define BMC150_ACCEL_SLEEP_500_MICRO 0x05 | |
112 | #define BMC150_ACCEL_SLEEP_1_MS 0x06 | |
113 | #define BMC150_ACCEL_SLEEP_2_MS 0x07 | |
114 | #define BMC150_ACCEL_SLEEP_4_MS 0x08 | |
115 | #define BMC150_ACCEL_SLEEP_6_MS 0x09 | |
116 | #define BMC150_ACCEL_SLEEP_10_MS 0x0A | |
117 | #define BMC150_ACCEL_SLEEP_25_MS 0x0B | |
118 | #define BMC150_ACCEL_SLEEP_50_MS 0x0C | |
119 | #define BMC150_ACCEL_SLEEP_100_MS 0x0D | |
120 | #define BMC150_ACCEL_SLEEP_500_MS 0x0E | |
121 | #define BMC150_ACCEL_SLEEP_1_SEC 0x0F | |
122 | ||
123 | #define BMC150_ACCEL_REG_TEMP 0x08 | |
124 | #define BMC150_ACCEL_TEMP_CENTER_VAL 24 | |
125 | ||
126 | #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) | |
127 | #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 | |
128 | ||
3bbec977 OP |
129 | #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E |
130 | #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 | |
131 | #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E | |
132 | #define BMC150_ACCEL_REG_FIFO_DATA 0x3F | |
133 | #define BMC150_ACCEL_FIFO_LENGTH 32 | |
134 | ||
bd7fe5b7 SP |
135 | enum bmc150_accel_axis { |
136 | AXIS_X, | |
137 | AXIS_Y, | |
138 | AXIS_Z, | |
139 | }; | |
140 | ||
141 | enum bmc150_power_modes { | |
142 | BMC150_ACCEL_SLEEP_MODE_NORMAL, | |
143 | BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, | |
144 | BMC150_ACCEL_SLEEP_MODE_LPM, | |
145 | BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, | |
146 | }; | |
147 | ||
8ecbb3c3 LP |
148 | struct bmc150_scale_info { |
149 | int scale; | |
150 | u8 reg_range; | |
151 | }; | |
152 | ||
153 | struct bmc150_accel_chip_info { | |
154 | u8 chip_id; | |
155 | const struct iio_chan_spec *channels; | |
156 | int num_channels; | |
157 | const struct bmc150_scale_info scale_table[4]; | |
158 | }; | |
159 | ||
3e825ec9 OP |
160 | struct bmc150_accel_interrupt { |
161 | const struct bmc150_accel_interrupt_info *info; | |
162 | atomic_t users; | |
163 | }; | |
164 | ||
7d963215 OP |
165 | struct bmc150_accel_trigger { |
166 | struct bmc150_accel_data *data; | |
167 | struct iio_trigger *indio_trig; | |
168 | int (*setup)(struct bmc150_accel_trigger *t, bool state); | |
169 | int intr; | |
170 | bool enabled; | |
171 | }; | |
172 | ||
3e825ec9 OP |
173 | enum bmc150_accel_interrupt_id { |
174 | BMC150_ACCEL_INT_DATA_READY, | |
175 | BMC150_ACCEL_INT_ANY_MOTION, | |
176 | BMC150_ACCEL_INT_WATERMARK, | |
177 | BMC150_ACCEL_INTERRUPTS, | |
178 | }; | |
179 | ||
7d963215 OP |
180 | enum bmc150_accel_trigger_id { |
181 | BMC150_ACCEL_TRIGGER_DATA_READY, | |
182 | BMC150_ACCEL_TRIGGER_ANY_MOTION, | |
183 | BMC150_ACCEL_TRIGGERS, | |
184 | }; | |
185 | ||
bd7fe5b7 SP |
186 | struct bmc150_accel_data { |
187 | struct i2c_client *client; | |
3e825ec9 | 188 | struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS]; |
3e825ec9 | 189 | atomic_t active_intr; |
7d963215 | 190 | struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; |
bd7fe5b7 | 191 | struct mutex mutex; |
3bbec977 | 192 | u8 fifo_mode, watermark; |
bd7fe5b7 SP |
193 | s16 buffer[8]; |
194 | u8 bw_bits; | |
195 | u32 slope_dur; | |
196 | u32 slope_thres; | |
197 | u32 range; | |
198 | int ev_enable_state; | |
c16bff48 | 199 | int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ |
8ecbb3c3 | 200 | const struct bmc150_accel_chip_info *chip_info; |
bd7fe5b7 SP |
201 | }; |
202 | ||
203 | static const struct { | |
204 | int val; | |
205 | int val2; | |
206 | u8 bw_bits; | |
0ba8da96 SK |
207 | } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08}, |
208 | {31, 260000, 0x09}, | |
209 | {62, 500000, 0x0A}, | |
210 | {125, 0, 0x0B}, | |
211 | {250, 0, 0x0C}, | |
212 | {500, 0, 0x0D}, | |
213 | {1000, 0, 0x0E}, | |
214 | {2000, 0, 0x0F} }; | |
bd7fe5b7 SP |
215 | |
216 | static const struct { | |
217 | int bw_bits; | |
218 | int msec; | |
219 | } bmc150_accel_sample_upd_time[] = { {0x08, 64}, | |
220 | {0x09, 32}, | |
221 | {0x0A, 16}, | |
222 | {0x0B, 8}, | |
223 | {0x0C, 4}, | |
224 | {0x0D, 2}, | |
225 | {0x0E, 1}, | |
226 | {0x0F, 1} }; | |
227 | ||
bd7fe5b7 SP |
228 | static const struct { |
229 | int sleep_dur; | |
8ecbb3c3 | 230 | u8 reg_value; |
bd7fe5b7 SP |
231 | } bmc150_accel_sleep_value_table[] = { {0, 0}, |
232 | {500, BMC150_ACCEL_SLEEP_500_MICRO}, | |
233 | {1000, BMC150_ACCEL_SLEEP_1_MS}, | |
234 | {2000, BMC150_ACCEL_SLEEP_2_MS}, | |
235 | {4000, BMC150_ACCEL_SLEEP_4_MS}, | |
236 | {6000, BMC150_ACCEL_SLEEP_6_MS}, | |
237 | {10000, BMC150_ACCEL_SLEEP_10_MS}, | |
238 | {25000, BMC150_ACCEL_SLEEP_25_MS}, | |
239 | {50000, BMC150_ACCEL_SLEEP_50_MS}, | |
240 | {100000, BMC150_ACCEL_SLEEP_100_MS}, | |
241 | {500000, BMC150_ACCEL_SLEEP_500_MS}, | |
242 | {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; | |
243 | ||
bd7fe5b7 SP |
244 | static int bmc150_accel_set_mode(struct bmc150_accel_data *data, |
245 | enum bmc150_power_modes mode, | |
246 | int dur_us) | |
247 | { | |
248 | int i; | |
249 | int ret; | |
250 | u8 lpw_bits; | |
251 | int dur_val = -1; | |
252 | ||
253 | if (dur_us > 0) { | |
254 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); | |
255 | ++i) { | |
256 | if (bmc150_accel_sleep_value_table[i].sleep_dur == | |
257 | dur_us) | |
258 | dur_val = | |
259 | bmc150_accel_sleep_value_table[i].reg_value; | |
260 | } | |
e20008ed | 261 | } else { |
bd7fe5b7 | 262 | dur_val = 0; |
e20008ed | 263 | } |
bd7fe5b7 SP |
264 | |
265 | if (dur_val < 0) | |
266 | return -EINVAL; | |
267 | ||
268 | lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; | |
269 | lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); | |
270 | ||
271 | dev_dbg(&data->client->dev, "Set Mode bits %x\n", lpw_bits); | |
272 | ||
273 | ret = i2c_smbus_write_byte_data(data->client, | |
274 | BMC150_ACCEL_REG_PMU_LPW, lpw_bits); | |
275 | if (ret < 0) { | |
276 | dev_err(&data->client->dev, "Error writing reg_pmu_lpw\n"); | |
277 | return ret; | |
278 | } | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
283 | static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, | |
284 | int val2) | |
285 | { | |
286 | int i; | |
287 | int ret; | |
288 | ||
289 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { | |
290 | if (bmc150_accel_samp_freq_table[i].val == val && | |
e20008ed | 291 | bmc150_accel_samp_freq_table[i].val2 == val2) { |
bd7fe5b7 SP |
292 | ret = i2c_smbus_write_byte_data( |
293 | data->client, | |
294 | BMC150_ACCEL_REG_PMU_BW, | |
295 | bmc150_accel_samp_freq_table[i].bw_bits); | |
296 | if (ret < 0) | |
297 | return ret; | |
298 | ||
299 | data->bw_bits = | |
300 | bmc150_accel_samp_freq_table[i].bw_bits; | |
301 | return 0; | |
302 | } | |
303 | } | |
304 | ||
305 | return -EINVAL; | |
306 | } | |
307 | ||
802a3aef OP |
308 | static int bmc150_accel_update_slope(struct bmc150_accel_data *data) |
309 | { | |
310 | int ret, val; | |
311 | ||
312 | ret = i2c_smbus_write_byte_data(data->client, BMC150_ACCEL_REG_INT_6, | |
313 | data->slope_thres); | |
314 | if (ret < 0) { | |
315 | dev_err(&data->client->dev, "Error writing reg_int_6\n"); | |
316 | return ret; | |
317 | } | |
318 | ||
319 | ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_INT_5); | |
320 | if (ret < 0) { | |
321 | dev_err(&data->client->dev, "Error reading reg_int_5\n"); | |
322 | return ret; | |
323 | } | |
324 | ||
325 | val = (ret & ~BMC150_ACCEL_SLOPE_DUR_MASK) | data->slope_dur; | |
326 | ret = i2c_smbus_write_byte_data(data->client, BMC150_ACCEL_REG_INT_5, | |
327 | val); | |
328 | if (ret < 0) { | |
329 | dev_err(&data->client->dev, "Error write reg_int_5\n"); | |
330 | return ret; | |
331 | } | |
332 | ||
333 | dev_dbg(&data->client->dev, "%s: %x %x\n", __func__, data->slope_thres, | |
334 | data->slope_dur); | |
335 | ||
336 | return ret; | |
337 | } | |
338 | ||
7d963215 OP |
339 | static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t, |
340 | bool state) | |
341 | { | |
342 | if (state) | |
343 | return bmc150_accel_update_slope(t->data); | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
bd7fe5b7 SP |
348 | static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, |
349 | int *val2) | |
350 | { | |
351 | int i; | |
352 | ||
353 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { | |
354 | if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { | |
355 | *val = bmc150_accel_samp_freq_table[i].val; | |
356 | *val2 = bmc150_accel_samp_freq_table[i].val2; | |
357 | return IIO_VAL_INT_PLUS_MICRO; | |
358 | } | |
359 | } | |
360 | ||
361 | return -EINVAL; | |
362 | } | |
363 | ||
6f0a13f2 | 364 | #ifdef CONFIG_PM |
bd7fe5b7 SP |
365 | static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) |
366 | { | |
367 | int i; | |
368 | ||
369 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { | |
370 | if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) | |
371 | return bmc150_accel_sample_upd_time[i].msec; | |
372 | } | |
373 | ||
374 | return BMC150_ACCEL_MAX_STARTUP_TIME_MS; | |
375 | } | |
376 | ||
377 | static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) | |
378 | { | |
379 | int ret; | |
380 | ||
e20008ed | 381 | if (on) { |
bd7fe5b7 | 382 | ret = pm_runtime_get_sync(&data->client->dev); |
e20008ed | 383 | } else { |
bd7fe5b7 SP |
384 | pm_runtime_mark_last_busy(&data->client->dev); |
385 | ret = pm_runtime_put_autosuspend(&data->client->dev); | |
386 | } | |
e20008ed | 387 | |
bd7fe5b7 SP |
388 | if (ret < 0) { |
389 | dev_err(&data->client->dev, | |
390 | "Failed: bmc150_accel_set_power_state for %d\n", on); | |
aaeecd80 SP |
391 | if (on) |
392 | pm_runtime_put_noidle(&data->client->dev); | |
393 | ||
bd7fe5b7 SP |
394 | return ret; |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
b31b05cf LP |
399 | #else |
400 | static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) | |
401 | { | |
402 | return 0; | |
403 | } | |
404 | #endif | |
bd7fe5b7 | 405 | |
8e22f477 OP |
406 | static const struct bmc150_accel_interrupt_info { |
407 | u8 map_reg; | |
408 | u8 map_bitmask; | |
409 | u8 en_reg; | |
410 | u8 en_bitmask; | |
3e825ec9 | 411 | } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = { |
8e22f477 OP |
412 | { /* data ready interrupt */ |
413 | .map_reg = BMC150_ACCEL_REG_INT_MAP_1, | |
414 | .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA, | |
415 | .en_reg = BMC150_ACCEL_REG_INT_EN_1, | |
416 | .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, | |
417 | }, | |
418 | { /* motion interrupt */ | |
419 | .map_reg = BMC150_ACCEL_REG_INT_MAP_0, | |
420 | .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE, | |
421 | .en_reg = BMC150_ACCEL_REG_INT_EN_0, | |
422 | .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | | |
423 | BMC150_ACCEL_INT_EN_BIT_SLP_Y | | |
424 | BMC150_ACCEL_INT_EN_BIT_SLP_Z | |
425 | }, | |
3bbec977 OP |
426 | { /* fifo watermark interrupt */ |
427 | .map_reg = BMC150_ACCEL_REG_INT_MAP_1, | |
428 | .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM, | |
429 | .en_reg = BMC150_ACCEL_REG_INT_EN_1, | |
430 | .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, | |
431 | }, | |
8e22f477 OP |
432 | }; |
433 | ||
3e825ec9 OP |
434 | static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, |
435 | struct bmc150_accel_data *data) | |
436 | { | |
437 | int i; | |
438 | ||
439 | for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++) | |
440 | data->interrupts[i].info = &bmc150_accel_interrupts[i]; | |
441 | } | |
442 | ||
443 | static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, | |
8e22f477 OP |
444 | bool state) |
445 | { | |
3e825ec9 OP |
446 | struct bmc150_accel_interrupt *intr = &data->interrupts[i]; |
447 | const struct bmc150_accel_interrupt_info *info = intr->info; | |
8e22f477 OP |
448 | int ret; |
449 | ||
3e825ec9 OP |
450 | if (state) { |
451 | if (atomic_inc_return(&intr->users) > 1) | |
452 | return 0; | |
453 | } else { | |
454 | if (atomic_dec_return(&intr->users) > 0) | |
455 | return 0; | |
456 | } | |
457 | ||
8e22f477 | 458 | /* |
e20008ed HK |
459 | * We will expect the enable and disable to do operation in reverse |
460 | * order. This will happen here anyway, as our resume operation uses | |
461 | * sync mode runtime pm calls. The suspend operation will be delayed | |
462 | * by autosuspend delay. | |
463 | * So the disable operation will still happen in reverse order of | |
464 | * enable operation. When runtime pm is disabled the mode is always on, | |
465 | * so sequence doesn't matter. | |
8e22f477 OP |
466 | */ |
467 | ret = bmc150_accel_set_power_state(data, state); | |
468 | if (ret < 0) | |
469 | return ret; | |
470 | ||
471 | /* map the interrupt to the appropriate pins */ | |
472 | ret = i2c_smbus_read_byte_data(data->client, info->map_reg); | |
473 | if (ret < 0) { | |
474 | dev_err(&data->client->dev, "Error reading reg_int_map\n"); | |
475 | goto out_fix_power_state; | |
476 | } | |
477 | if (state) | |
478 | ret |= info->map_bitmask; | |
479 | else | |
480 | ret &= ~info->map_bitmask; | |
481 | ||
482 | ret = i2c_smbus_write_byte_data(data->client, info->map_reg, | |
483 | ret); | |
484 | if (ret < 0) { | |
485 | dev_err(&data->client->dev, "Error writing reg_int_map\n"); | |
486 | goto out_fix_power_state; | |
487 | } | |
488 | ||
489 | /* enable/disable the interrupt */ | |
490 | ret = i2c_smbus_read_byte_data(data->client, info->en_reg); | |
491 | if (ret < 0) { | |
492 | dev_err(&data->client->dev, "Error reading reg_int_en\n"); | |
493 | goto out_fix_power_state; | |
494 | } | |
495 | ||
496 | if (state) | |
497 | ret |= info->en_bitmask; | |
498 | else | |
499 | ret &= ~info->en_bitmask; | |
500 | ||
501 | ret = i2c_smbus_write_byte_data(data->client, info->en_reg, ret); | |
502 | if (ret < 0) { | |
503 | dev_err(&data->client->dev, "Error writing reg_int_en\n"); | |
504 | goto out_fix_power_state; | |
505 | } | |
506 | ||
3e825ec9 OP |
507 | if (state) |
508 | atomic_inc(&data->active_intr); | |
509 | else | |
510 | atomic_dec(&data->active_intr); | |
511 | ||
8e22f477 OP |
512 | return 0; |
513 | ||
514 | out_fix_power_state: | |
515 | bmc150_accel_set_power_state(data, false); | |
516 | return ret; | |
517 | } | |
518 | ||
bd7fe5b7 SP |
519 | static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) |
520 | { | |
521 | int ret, i; | |
522 | ||
8ecbb3c3 LP |
523 | for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { |
524 | if (data->chip_info->scale_table[i].scale == val) { | |
bd7fe5b7 | 525 | ret = i2c_smbus_write_byte_data( |
8ecbb3c3 LP |
526 | data->client, |
527 | BMC150_ACCEL_REG_PMU_RANGE, | |
528 | data->chip_info->scale_table[i].reg_range); | |
bd7fe5b7 SP |
529 | if (ret < 0) { |
530 | dev_err(&data->client->dev, | |
531 | "Error writing pmu_range\n"); | |
532 | return ret; | |
533 | } | |
534 | ||
8ecbb3c3 | 535 | data->range = data->chip_info->scale_table[i].reg_range; |
bd7fe5b7 SP |
536 | return 0; |
537 | } | |
538 | } | |
539 | ||
540 | return -EINVAL; | |
541 | } | |
542 | ||
543 | static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) | |
544 | { | |
545 | int ret; | |
546 | ||
547 | mutex_lock(&data->mutex); | |
548 | ||
549 | ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_TEMP); | |
550 | if (ret < 0) { | |
551 | dev_err(&data->client->dev, "Error reading reg_temp\n"); | |
552 | mutex_unlock(&data->mutex); | |
553 | return ret; | |
554 | } | |
555 | *val = sign_extend32(ret, 7); | |
556 | ||
557 | mutex_unlock(&data->mutex); | |
558 | ||
559 | return IIO_VAL_INT; | |
560 | } | |
561 | ||
8ecbb3c3 LP |
562 | static int bmc150_accel_get_axis(struct bmc150_accel_data *data, |
563 | struct iio_chan_spec const *chan, | |
bd7fe5b7 SP |
564 | int *val) |
565 | { | |
566 | int ret; | |
8ecbb3c3 | 567 | int axis = chan->scan_index; |
bd7fe5b7 SP |
568 | |
569 | mutex_lock(&data->mutex); | |
570 | ret = bmc150_accel_set_power_state(data, true); | |
571 | if (ret < 0) { | |
572 | mutex_unlock(&data->mutex); | |
573 | return ret; | |
574 | } | |
575 | ||
576 | ret = i2c_smbus_read_word_data(data->client, | |
577 | BMC150_ACCEL_AXIS_TO_REG(axis)); | |
578 | if (ret < 0) { | |
579 | dev_err(&data->client->dev, "Error reading axis %d\n", axis); | |
580 | bmc150_accel_set_power_state(data, false); | |
581 | mutex_unlock(&data->mutex); | |
582 | return ret; | |
583 | } | |
8ecbb3c3 LP |
584 | *val = sign_extend32(ret >> chan->scan_type.shift, |
585 | chan->scan_type.realbits - 1); | |
bd7fe5b7 SP |
586 | ret = bmc150_accel_set_power_state(data, false); |
587 | mutex_unlock(&data->mutex); | |
588 | if (ret < 0) | |
589 | return ret; | |
590 | ||
591 | return IIO_VAL_INT; | |
592 | } | |
593 | ||
594 | static int bmc150_accel_read_raw(struct iio_dev *indio_dev, | |
595 | struct iio_chan_spec const *chan, | |
596 | int *val, int *val2, long mask) | |
597 | { | |
598 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
599 | int ret; | |
600 | ||
601 | switch (mask) { | |
602 | case IIO_CHAN_INFO_RAW: | |
603 | switch (chan->type) { | |
604 | case IIO_TEMP: | |
605 | return bmc150_accel_get_temp(data, val); | |
606 | case IIO_ACCEL: | |
607 | if (iio_buffer_enabled(indio_dev)) | |
608 | return -EBUSY; | |
609 | else | |
8ecbb3c3 | 610 | return bmc150_accel_get_axis(data, chan, val); |
bd7fe5b7 SP |
611 | default: |
612 | return -EINVAL; | |
613 | } | |
614 | case IIO_CHAN_INFO_OFFSET: | |
615 | if (chan->type == IIO_TEMP) { | |
616 | *val = BMC150_ACCEL_TEMP_CENTER_VAL; | |
617 | return IIO_VAL_INT; | |
e20008ed | 618 | } else { |
bd7fe5b7 | 619 | return -EINVAL; |
e20008ed | 620 | } |
bd7fe5b7 SP |
621 | case IIO_CHAN_INFO_SCALE: |
622 | *val = 0; | |
623 | switch (chan->type) { | |
624 | case IIO_TEMP: | |
625 | *val2 = 500000; | |
626 | return IIO_VAL_INT_PLUS_MICRO; | |
627 | case IIO_ACCEL: | |
628 | { | |
629 | int i; | |
8ecbb3c3 LP |
630 | const struct bmc150_scale_info *si; |
631 | int st_size = ARRAY_SIZE(data->chip_info->scale_table); | |
bd7fe5b7 | 632 | |
8ecbb3c3 LP |
633 | for (i = 0; i < st_size; ++i) { |
634 | si = &data->chip_info->scale_table[i]; | |
635 | if (si->reg_range == data->range) { | |
636 | *val2 = si->scale; | |
bd7fe5b7 SP |
637 | return IIO_VAL_INT_PLUS_MICRO; |
638 | } | |
639 | } | |
640 | return -EINVAL; | |
641 | } | |
642 | default: | |
643 | return -EINVAL; | |
644 | } | |
645 | case IIO_CHAN_INFO_SAMP_FREQ: | |
646 | mutex_lock(&data->mutex); | |
647 | ret = bmc150_accel_get_bw(data, val, val2); | |
648 | mutex_unlock(&data->mutex); | |
649 | return ret; | |
650 | default: | |
651 | return -EINVAL; | |
652 | } | |
653 | } | |
654 | ||
655 | static int bmc150_accel_write_raw(struct iio_dev *indio_dev, | |
656 | struct iio_chan_spec const *chan, | |
657 | int val, int val2, long mask) | |
658 | { | |
659 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
660 | int ret; | |
661 | ||
662 | switch (mask) { | |
663 | case IIO_CHAN_INFO_SAMP_FREQ: | |
664 | mutex_lock(&data->mutex); | |
665 | ret = bmc150_accel_set_bw(data, val, val2); | |
666 | mutex_unlock(&data->mutex); | |
667 | break; | |
668 | case IIO_CHAN_INFO_SCALE: | |
669 | if (val) | |
670 | return -EINVAL; | |
671 | ||
672 | mutex_lock(&data->mutex); | |
673 | ret = bmc150_accel_set_scale(data, val2); | |
674 | mutex_unlock(&data->mutex); | |
675 | return ret; | |
676 | default: | |
677 | ret = -EINVAL; | |
678 | } | |
679 | ||
680 | return ret; | |
681 | } | |
682 | ||
683 | static int bmc150_accel_read_event(struct iio_dev *indio_dev, | |
684 | const struct iio_chan_spec *chan, | |
685 | enum iio_event_type type, | |
686 | enum iio_event_direction dir, | |
687 | enum iio_event_info info, | |
688 | int *val, int *val2) | |
689 | { | |
690 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
691 | ||
692 | *val2 = 0; | |
693 | switch (info) { | |
694 | case IIO_EV_INFO_VALUE: | |
695 | *val = data->slope_thres; | |
696 | break; | |
697 | case IIO_EV_INFO_PERIOD: | |
802a3aef | 698 | *val = data->slope_dur; |
bd7fe5b7 SP |
699 | break; |
700 | default: | |
701 | return -EINVAL; | |
702 | } | |
703 | ||
704 | return IIO_VAL_INT; | |
705 | } | |
706 | ||
707 | static int bmc150_accel_write_event(struct iio_dev *indio_dev, | |
708 | const struct iio_chan_spec *chan, | |
709 | enum iio_event_type type, | |
710 | enum iio_event_direction dir, | |
711 | enum iio_event_info info, | |
712 | int val, int val2) | |
713 | { | |
714 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
715 | ||
716 | if (data->ev_enable_state) | |
717 | return -EBUSY; | |
718 | ||
719 | switch (info) { | |
720 | case IIO_EV_INFO_VALUE: | |
fdd15f65 | 721 | data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; |
bd7fe5b7 SP |
722 | break; |
723 | case IIO_EV_INFO_PERIOD: | |
802a3aef | 724 | data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; |
bd7fe5b7 SP |
725 | break; |
726 | default: | |
727 | return -EINVAL; | |
728 | } | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, | |
734 | const struct iio_chan_spec *chan, | |
735 | enum iio_event_type type, | |
736 | enum iio_event_direction dir) | |
737 | { | |
bd7fe5b7 SP |
738 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
739 | ||
740 | return data->ev_enable_state; | |
741 | } | |
742 | ||
743 | static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, | |
744 | const struct iio_chan_spec *chan, | |
745 | enum iio_event_type type, | |
746 | enum iio_event_direction dir, | |
747 | int state) | |
748 | { | |
749 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
750 | int ret; | |
751 | ||
14ee64f4 | 752 | if (state == data->ev_enable_state) |
bd7fe5b7 SP |
753 | return 0; |
754 | ||
755 | mutex_lock(&data->mutex); | |
756 | ||
3e825ec9 OP |
757 | ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION, |
758 | state); | |
bd7fe5b7 SP |
759 | if (ret < 0) { |
760 | mutex_unlock(&data->mutex); | |
761 | return ret; | |
762 | } | |
763 | ||
764 | data->ev_enable_state = state; | |
765 | mutex_unlock(&data->mutex); | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
770 | static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, | |
e20008ed | 771 | struct iio_trigger *trig) |
bd7fe5b7 SP |
772 | { |
773 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
7d963215 | 774 | int i; |
bd7fe5b7 | 775 | |
7d963215 OP |
776 | for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { |
777 | if (data->triggers[i].indio_trig == trig) | |
778 | return 0; | |
779 | } | |
bd7fe5b7 | 780 | |
7d963215 | 781 | return -EINVAL; |
bd7fe5b7 SP |
782 | } |
783 | ||
3bbec977 OP |
784 | static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, |
785 | struct device_attribute *attr, | |
786 | char *buf) | |
787 | { | |
788 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | |
789 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
790 | int wm; | |
791 | ||
792 | mutex_lock(&data->mutex); | |
793 | wm = data->watermark; | |
794 | mutex_unlock(&data->mutex); | |
795 | ||
796 | return sprintf(buf, "%d\n", wm); | |
797 | } | |
798 | ||
799 | static ssize_t bmc150_accel_get_fifo_state(struct device *dev, | |
800 | struct device_attribute *attr, | |
801 | char *buf) | |
802 | { | |
803 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | |
804 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
805 | bool state; | |
806 | ||
807 | mutex_lock(&data->mutex); | |
808 | state = data->fifo_mode; | |
809 | mutex_unlock(&data->mutex); | |
810 | ||
811 | return sprintf(buf, "%d\n", state); | |
812 | } | |
813 | ||
814 | static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); | |
815 | static IIO_CONST_ATTR(hwfifo_watermark_max, | |
816 | __stringify(BMC150_ACCEL_FIFO_LENGTH)); | |
817 | static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, | |
818 | bmc150_accel_get_fifo_state, NULL, 0); | |
819 | static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, | |
820 | bmc150_accel_get_fifo_watermark, NULL, 0); | |
821 | ||
822 | static const struct attribute *bmc150_accel_fifo_attributes[] = { | |
823 | &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, | |
824 | &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, | |
825 | &iio_dev_attr_hwfifo_watermark.dev_attr.attr, | |
826 | &iio_dev_attr_hwfifo_enabled.dev_attr.attr, | |
827 | NULL, | |
828 | }; | |
829 | ||
830 | static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) | |
831 | { | |
832 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
833 | ||
834 | if (val > BMC150_ACCEL_FIFO_LENGTH) | |
835 | val = BMC150_ACCEL_FIFO_LENGTH; | |
836 | ||
837 | mutex_lock(&data->mutex); | |
838 | data->watermark = val; | |
839 | mutex_unlock(&data->mutex); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | /* | |
845 | * We must read at least one full frame in one burst, otherwise the rest of the | |
846 | * frame data is discarded. | |
847 | */ | |
848 | static int bmc150_accel_fifo_transfer(const struct i2c_client *client, | |
849 | char *buffer, int samples) | |
850 | { | |
851 | int sample_length = 3 * 2; | |
852 | u8 reg_fifo_data = BMC150_ACCEL_REG_FIFO_DATA; | |
853 | int ret = -EIO; | |
854 | ||
855 | if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { | |
856 | struct i2c_msg msg[2] = { | |
857 | { | |
858 | .addr = client->addr, | |
859 | .flags = 0, | |
860 | .buf = ®_fifo_data, | |
861 | .len = sizeof(reg_fifo_data), | |
862 | }, | |
863 | { | |
864 | .addr = client->addr, | |
865 | .flags = I2C_M_RD, | |
866 | .buf = (u8 *)buffer, | |
867 | .len = samples * sample_length, | |
868 | } | |
869 | }; | |
870 | ||
871 | ret = i2c_transfer(client->adapter, msg, 2); | |
872 | if (ret != 2) | |
873 | ret = -EIO; | |
874 | else | |
875 | ret = 0; | |
876 | } else { | |
877 | int i, step = I2C_SMBUS_BLOCK_MAX / sample_length; | |
878 | ||
879 | for (i = 0; i < samples * sample_length; i += step) { | |
880 | ret = i2c_smbus_read_i2c_block_data(client, | |
881 | reg_fifo_data, step, | |
882 | &buffer[i]); | |
883 | if (ret != step) { | |
884 | ret = -EIO; | |
885 | break; | |
886 | } | |
887 | ||
888 | ret = 0; | |
889 | } | |
890 | } | |
891 | ||
892 | if (ret) | |
893 | dev_err(&client->dev, "Error transferring data from fifo\n"); | |
894 | ||
895 | return ret; | |
896 | } | |
897 | ||
898 | static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, | |
899 | unsigned samples, bool irq) | |
900 | { | |
901 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
902 | int ret, i; | |
903 | u8 count; | |
904 | u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; | |
905 | int64_t tstamp; | |
906 | uint64_t sample_period; | |
e20008ed | 907 | |
3bbec977 OP |
908 | ret = i2c_smbus_read_byte_data(data->client, |
909 | BMC150_ACCEL_REG_FIFO_STATUS); | |
910 | if (ret < 0) { | |
911 | dev_err(&data->client->dev, "Error reading reg_fifo_status\n"); | |
912 | return ret; | |
913 | } | |
914 | ||
915 | count = ret & 0x7F; | |
916 | ||
917 | if (!count) | |
918 | return 0; | |
919 | ||
920 | /* | |
921 | * If we getting called from IRQ handler we know the stored timestamp is | |
922 | * fairly accurate for the last stored sample. Otherwise, if we are | |
923 | * called as a result of a read operation from userspace and hence | |
924 | * before the watermark interrupt was triggered, take a timestamp | |
925 | * now. We can fall anywhere in between two samples so the error in this | |
926 | * case is at most one sample period. | |
927 | */ | |
928 | if (!irq) { | |
929 | data->old_timestamp = data->timestamp; | |
930 | data->timestamp = iio_get_time_ns(); | |
931 | } | |
932 | ||
933 | /* | |
934 | * Approximate timestamps for each of the sample based on the sampling | |
935 | * frequency, timestamp for last sample and number of samples. | |
936 | * | |
937 | * Note that we can't use the current bandwidth settings to compute the | |
938 | * sample period because the sample rate varies with the device | |
939 | * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That | |
940 | * small variation adds when we store a large number of samples and | |
941 | * creates significant jitter between the last and first samples in | |
942 | * different batches (e.g. 32ms vs 21ms). | |
943 | * | |
944 | * To avoid this issue we compute the actual sample period ourselves | |
945 | * based on the timestamp delta between the last two flush operations. | |
946 | */ | |
947 | sample_period = (data->timestamp - data->old_timestamp); | |
948 | do_div(sample_period, count); | |
949 | tstamp = data->timestamp - (count - 1) * sample_period; | |
950 | ||
951 | if (samples && count > samples) | |
952 | count = samples; | |
953 | ||
954 | ret = bmc150_accel_fifo_transfer(data->client, (u8 *)buffer, count); | |
955 | if (ret) | |
956 | return ret; | |
957 | ||
958 | /* | |
959 | * Ideally we want the IIO core to handle the demux when running in fifo | |
960 | * mode but not when running in triggered buffer mode. Unfortunately | |
961 | * this does not seem to be possible, so stick with driver demux for | |
962 | * now. | |
963 | */ | |
964 | for (i = 0; i < count; i++) { | |
965 | u16 sample[8]; | |
966 | int j, bit; | |
967 | ||
968 | j = 0; | |
969 | for_each_set_bit(bit, indio_dev->active_scan_mask, | |
970 | indio_dev->masklength) | |
971 | memcpy(&sample[j++], &buffer[i * 3 + bit], 2); | |
972 | ||
973 | iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp); | |
974 | ||
975 | tstamp += sample_period; | |
976 | } | |
977 | ||
978 | return count; | |
979 | } | |
980 | ||
981 | static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) | |
982 | { | |
983 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
984 | int ret; | |
985 | ||
986 | mutex_lock(&data->mutex); | |
987 | ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); | |
988 | mutex_unlock(&data->mutex); | |
989 | ||
990 | return ret; | |
991 | } | |
992 | ||
bd7fe5b7 | 993 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( |
0ba8da96 | 994 | "15.620000 31.260000 62.50000 125 250 500 1000 2000"); |
bd7fe5b7 SP |
995 | |
996 | static struct attribute *bmc150_accel_attributes[] = { | |
997 | &iio_const_attr_sampling_frequency_available.dev_attr.attr, | |
998 | NULL, | |
999 | }; | |
1000 | ||
1001 | static const struct attribute_group bmc150_accel_attrs_group = { | |
1002 | .attrs = bmc150_accel_attributes, | |
1003 | }; | |
1004 | ||
1005 | static const struct iio_event_spec bmc150_accel_event = { | |
1006 | .type = IIO_EV_TYPE_ROC, | |
1174124c | 1007 | .dir = IIO_EV_DIR_EITHER, |
bd7fe5b7 SP |
1008 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | |
1009 | BIT(IIO_EV_INFO_ENABLE) | | |
1010 | BIT(IIO_EV_INFO_PERIOD) | |
1011 | }; | |
1012 | ||
8ecbb3c3 | 1013 | #define BMC150_ACCEL_CHANNEL(_axis, bits) { \ |
bd7fe5b7 SP |
1014 | .type = IIO_ACCEL, \ |
1015 | .modified = 1, \ | |
1016 | .channel2 = IIO_MOD_##_axis, \ | |
1017 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
1018 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ | |
1019 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ | |
1020 | .scan_index = AXIS_##_axis, \ | |
1021 | .scan_type = { \ | |
1022 | .sign = 's', \ | |
8ecbb3c3 | 1023 | .realbits = (bits), \ |
bd7fe5b7 | 1024 | .storagebits = 16, \ |
8ecbb3c3 | 1025 | .shift = 16 - (bits), \ |
bd7fe5b7 SP |
1026 | }, \ |
1027 | .event_spec = &bmc150_accel_event, \ | |
1028 | .num_event_specs = 1 \ | |
1029 | } | |
1030 | ||
8ecbb3c3 LP |
1031 | #define BMC150_ACCEL_CHANNELS(bits) { \ |
1032 | { \ | |
1033 | .type = IIO_TEMP, \ | |
1034 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ | |
1035 | BIT(IIO_CHAN_INFO_SCALE) | \ | |
1036 | BIT(IIO_CHAN_INFO_OFFSET), \ | |
1037 | .scan_index = -1, \ | |
1038 | }, \ | |
1039 | BMC150_ACCEL_CHANNEL(X, bits), \ | |
1040 | BMC150_ACCEL_CHANNEL(Y, bits), \ | |
1041 | BMC150_ACCEL_CHANNEL(Z, bits), \ | |
1042 | IIO_CHAN_SOFT_TIMESTAMP(3), \ | |
1043 | } | |
1044 | ||
1045 | static const struct iio_chan_spec bma222e_accel_channels[] = | |
1046 | BMC150_ACCEL_CHANNELS(8); | |
1047 | static const struct iio_chan_spec bma250e_accel_channels[] = | |
1048 | BMC150_ACCEL_CHANNELS(10); | |
1049 | static const struct iio_chan_spec bmc150_accel_channels[] = | |
1050 | BMC150_ACCEL_CHANNELS(12); | |
1051 | static const struct iio_chan_spec bma280_accel_channels[] = | |
1052 | BMC150_ACCEL_CHANNELS(14); | |
1053 | ||
1054 | enum { | |
1055 | bmc150, | |
1056 | bmi055, | |
1057 | bma255, | |
1058 | bma250e, | |
1059 | bma222e, | |
1060 | bma280, | |
1061 | }; | |
1062 | ||
1063 | static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { | |
1064 | [bmc150] = { | |
1065 | .chip_id = 0xFA, | |
1066 | .channels = bmc150_accel_channels, | |
1067 | .num_channels = ARRAY_SIZE(bmc150_accel_channels), | |
1068 | .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, | |
1069 | {19122, BMC150_ACCEL_DEF_RANGE_4G}, | |
1070 | {38344, BMC150_ACCEL_DEF_RANGE_8G}, | |
1071 | {76590, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1072 | }, | |
1073 | [bmi055] = { | |
1074 | .chip_id = 0xFA, | |
1075 | .channels = bmc150_accel_channels, | |
1076 | .num_channels = ARRAY_SIZE(bmc150_accel_channels), | |
1077 | .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, | |
1078 | {19122, BMC150_ACCEL_DEF_RANGE_4G}, | |
1079 | {38344, BMC150_ACCEL_DEF_RANGE_8G}, | |
1080 | {76590, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1081 | }, | |
1082 | [bma255] = { | |
1083 | .chip_id = 0xFA, | |
1084 | .channels = bmc150_accel_channels, | |
1085 | .num_channels = ARRAY_SIZE(bmc150_accel_channels), | |
1086 | .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, | |
1087 | {19122, BMC150_ACCEL_DEF_RANGE_4G}, | |
1088 | {38344, BMC150_ACCEL_DEF_RANGE_8G}, | |
1089 | {76590, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1090 | }, | |
1091 | [bma250e] = { | |
1092 | .chip_id = 0xF9, | |
1093 | .channels = bma250e_accel_channels, | |
1094 | .num_channels = ARRAY_SIZE(bma250e_accel_channels), | |
1095 | .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G}, | |
1096 | {76590, BMC150_ACCEL_DEF_RANGE_4G}, | |
1097 | {153277, BMC150_ACCEL_DEF_RANGE_8G}, | |
1098 | {306457, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1099 | }, | |
1100 | [bma222e] = { | |
1101 | .chip_id = 0xF8, | |
1102 | .channels = bma222e_accel_channels, | |
1103 | .num_channels = ARRAY_SIZE(bma222e_accel_channels), | |
1104 | .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G}, | |
1105 | {306457, BMC150_ACCEL_DEF_RANGE_4G}, | |
1106 | {612915, BMC150_ACCEL_DEF_RANGE_8G}, | |
1107 | {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1108 | }, | |
1109 | [bma280] = { | |
1110 | .chip_id = 0xFB, | |
1111 | .channels = bma280_accel_channels, | |
1112 | .num_channels = ARRAY_SIZE(bma280_accel_channels), | |
1113 | .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G}, | |
1114 | {4785, BMC150_ACCEL_DEF_RANGE_4G}, | |
1115 | {9581, BMC150_ACCEL_DEF_RANGE_8G}, | |
1116 | {19152, BMC150_ACCEL_DEF_RANGE_16G} }, | |
bd7fe5b7 | 1117 | }, |
bd7fe5b7 SP |
1118 | }; |
1119 | ||
1120 | static const struct iio_info bmc150_accel_info = { | |
1121 | .attrs = &bmc150_accel_attrs_group, | |
1122 | .read_raw = bmc150_accel_read_raw, | |
1123 | .write_raw = bmc150_accel_write_raw, | |
1124 | .read_event_value = bmc150_accel_read_event, | |
1125 | .write_event_value = bmc150_accel_write_event, | |
1126 | .write_event_config = bmc150_accel_write_event_config, | |
1127 | .read_event_config = bmc150_accel_read_event_config, | |
bd7fe5b7 SP |
1128 | .driver_module = THIS_MODULE, |
1129 | }; | |
1130 | ||
3bbec977 OP |
1131 | static const struct iio_info bmc150_accel_info_fifo = { |
1132 | .attrs = &bmc150_accel_attrs_group, | |
1133 | .read_raw = bmc150_accel_read_raw, | |
1134 | .write_raw = bmc150_accel_write_raw, | |
1135 | .read_event_value = bmc150_accel_read_event, | |
1136 | .write_event_value = bmc150_accel_write_event, | |
1137 | .write_event_config = bmc150_accel_write_event_config, | |
1138 | .read_event_config = bmc150_accel_read_event_config, | |
1139 | .validate_trigger = bmc150_accel_validate_trigger, | |
1140 | .hwfifo_set_watermark = bmc150_accel_set_watermark, | |
1141 | .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, | |
1142 | .driver_module = THIS_MODULE, | |
1143 | }; | |
1144 | ||
bd7fe5b7 SP |
1145 | static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) |
1146 | { | |
1147 | struct iio_poll_func *pf = p; | |
1148 | struct iio_dev *indio_dev = pf->indio_dev; | |
1149 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1150 | int bit, ret, i = 0; | |
1151 | ||
1152 | mutex_lock(&data->mutex); | |
70dddeee | 1153 | for_each_set_bit(bit, indio_dev->active_scan_mask, |
bd7fe5b7 SP |
1154 | indio_dev->masklength) { |
1155 | ret = i2c_smbus_read_word_data(data->client, | |
1156 | BMC150_ACCEL_AXIS_TO_REG(bit)); | |
1157 | if (ret < 0) { | |
1158 | mutex_unlock(&data->mutex); | |
1159 | goto err_read; | |
1160 | } | |
1161 | data->buffer[i++] = ret; | |
1162 | } | |
1163 | mutex_unlock(&data->mutex); | |
1164 | ||
1165 | iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, | |
c16bff48 | 1166 | pf->timestamp); |
bd7fe5b7 SP |
1167 | err_read: |
1168 | iio_trigger_notify_done(indio_dev->trig); | |
1169 | ||
1170 | return IRQ_HANDLED; | |
1171 | } | |
1172 | ||
1173 | static int bmc150_accel_trig_try_reen(struct iio_trigger *trig) | |
1174 | { | |
7d963215 OP |
1175 | struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); |
1176 | struct bmc150_accel_data *data = t->data; | |
bd7fe5b7 SP |
1177 | int ret; |
1178 | ||
1179 | /* new data interrupts don't need ack */ | |
7d963215 | 1180 | if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY]) |
bd7fe5b7 SP |
1181 | return 0; |
1182 | ||
1183 | mutex_lock(&data->mutex); | |
1184 | /* clear any latched interrupt */ | |
1185 | ret = i2c_smbus_write_byte_data(data->client, | |
1186 | BMC150_ACCEL_REG_INT_RST_LATCH, | |
1187 | BMC150_ACCEL_INT_MODE_LATCH_INT | | |
1188 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | |
1189 | mutex_unlock(&data->mutex); | |
1190 | if (ret < 0) { | |
1191 | dev_err(&data->client->dev, | |
1192 | "Error writing reg_int_rst_latch\n"); | |
1193 | return ret; | |
1194 | } | |
1195 | ||
1196 | return 0; | |
1197 | } | |
1198 | ||
7d963215 | 1199 | static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, |
e20008ed | 1200 | bool state) |
bd7fe5b7 | 1201 | { |
7d963215 OP |
1202 | struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); |
1203 | struct bmc150_accel_data *data = t->data; | |
bd7fe5b7 SP |
1204 | int ret; |
1205 | ||
1206 | mutex_lock(&data->mutex); | |
1207 | ||
7d963215 OP |
1208 | if (t->enabled == state) { |
1209 | mutex_unlock(&data->mutex); | |
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | if (t->setup) { | |
1214 | ret = t->setup(t, state); | |
1215 | if (ret < 0) { | |
14ee64f4 | 1216 | mutex_unlock(&data->mutex); |
7d963215 | 1217 | return ret; |
14ee64f4 OP |
1218 | } |
1219 | } | |
1220 | ||
7d963215 | 1221 | ret = bmc150_accel_set_interrupt(data, t->intr, state); |
bd7fe5b7 SP |
1222 | if (ret < 0) { |
1223 | mutex_unlock(&data->mutex); | |
1224 | return ret; | |
1225 | } | |
7d963215 OP |
1226 | |
1227 | t->enabled = state; | |
bd7fe5b7 SP |
1228 | |
1229 | mutex_unlock(&data->mutex); | |
1230 | ||
1231 | return ret; | |
1232 | } | |
1233 | ||
1234 | static const struct iio_trigger_ops bmc150_accel_trigger_ops = { | |
7d963215 | 1235 | .set_trigger_state = bmc150_accel_trigger_set_state, |
bd7fe5b7 SP |
1236 | .try_reenable = bmc150_accel_trig_try_reen, |
1237 | .owner = THIS_MODULE, | |
1238 | }; | |
1239 | ||
3bbec977 | 1240 | static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) |
bd7fe5b7 | 1241 | { |
bd7fe5b7 | 1242 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
bd7fe5b7 | 1243 | int dir; |
3bbec977 | 1244 | int ret; |
bd7fe5b7 SP |
1245 | |
1246 | ret = i2c_smbus_read_byte_data(data->client, | |
1247 | BMC150_ACCEL_REG_INT_STATUS_2); | |
1248 | if (ret < 0) { | |
1249 | dev_err(&data->client->dev, "Error reading reg_int_status_2\n"); | |
3bbec977 | 1250 | return ret; |
bd7fe5b7 SP |
1251 | } |
1252 | ||
1253 | if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) | |
1254 | dir = IIO_EV_DIR_FALLING; | |
1255 | else | |
1256 | dir = IIO_EV_DIR_RISING; | |
1257 | ||
8d5a9781 | 1258 | if (ret & BMC150_ACCEL_ANY_MOTION_BIT_X) |
e20008ed HK |
1259 | iio_push_event(indio_dev, |
1260 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | |
1261 | 0, | |
1262 | IIO_MOD_X, | |
1263 | IIO_EV_TYPE_ROC, | |
1264 | dir), | |
1265 | data->timestamp); | |
1266 | ||
8d5a9781 | 1267 | if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Y) |
e20008ed HK |
1268 | iio_push_event(indio_dev, |
1269 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | |
1270 | 0, | |
1271 | IIO_MOD_Y, | |
1272 | IIO_EV_TYPE_ROC, | |
1273 | dir), | |
1274 | data->timestamp); | |
1275 | ||
8d5a9781 | 1276 | if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Z) |
e20008ed HK |
1277 | iio_push_event(indio_dev, |
1278 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | |
1279 | 0, | |
1280 | IIO_MOD_Z, | |
1281 | IIO_EV_TYPE_ROC, | |
1282 | dir), | |
1283 | data->timestamp); | |
1284 | ||
3bbec977 OP |
1285 | return ret; |
1286 | } | |
1287 | ||
1288 | static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) | |
1289 | { | |
1290 | struct iio_dev *indio_dev = private; | |
1291 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1292 | bool ack = false; | |
1293 | int ret; | |
1294 | ||
1295 | mutex_lock(&data->mutex); | |
1296 | ||
1297 | if (data->fifo_mode) { | |
1298 | ret = __bmc150_accel_fifo_flush(indio_dev, | |
1299 | BMC150_ACCEL_FIFO_LENGTH, true); | |
1300 | if (ret > 0) | |
1301 | ack = true; | |
1302 | } | |
1303 | ||
1304 | if (data->ev_enable_state) { | |
1305 | ret = bmc150_accel_handle_roc_event(indio_dev); | |
1306 | if (ret > 0) | |
1307 | ack = true; | |
1308 | } | |
1309 | ||
1310 | if (ack) { | |
bd7fe5b7 SP |
1311 | ret = i2c_smbus_write_byte_data(data->client, |
1312 | BMC150_ACCEL_REG_INT_RST_LATCH, | |
1313 | BMC150_ACCEL_INT_MODE_LATCH_INT | | |
1314 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | |
3bbec977 | 1315 | if (ret) |
e20008ed HK |
1316 | dev_err(&data->client->dev, |
1317 | "Error writing reg_int_rst_latch\n"); | |
1318 | ||
3bbec977 OP |
1319 | ret = IRQ_HANDLED; |
1320 | } else { | |
1321 | ret = IRQ_NONE; | |
1322 | } | |
bd7fe5b7 | 1323 | |
3bbec977 OP |
1324 | mutex_unlock(&data->mutex); |
1325 | ||
1326 | return ret; | |
bd7fe5b7 SP |
1327 | } |
1328 | ||
3bbec977 | 1329 | static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) |
bd7fe5b7 SP |
1330 | { |
1331 | struct iio_dev *indio_dev = private; | |
1332 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
3bbec977 | 1333 | bool ack = false; |
7d963215 | 1334 | int i; |
bd7fe5b7 | 1335 | |
3bbec977 | 1336 | data->old_timestamp = data->timestamp; |
bd7fe5b7 SP |
1337 | data->timestamp = iio_get_time_ns(); |
1338 | ||
7d963215 OP |
1339 | for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { |
1340 | if (data->triggers[i].enabled) { | |
1341 | iio_trigger_poll(data->triggers[i].indio_trig); | |
3bbec977 | 1342 | ack = true; |
7d963215 OP |
1343 | break; |
1344 | } | |
1345 | } | |
bd7fe5b7 | 1346 | |
3bbec977 | 1347 | if (data->ev_enable_state || data->fifo_mode) |
bd7fe5b7 | 1348 | return IRQ_WAKE_THREAD; |
3bbec977 OP |
1349 | |
1350 | if (ack) | |
bd7fe5b7 | 1351 | return IRQ_HANDLED; |
3bbec977 OP |
1352 | |
1353 | return IRQ_NONE; | |
bd7fe5b7 SP |
1354 | } |
1355 | ||
8ecbb3c3 | 1356 | static const char *bmc150_accel_match_acpi_device(struct device *dev, int *data) |
bd7fe5b7 SP |
1357 | { |
1358 | const struct acpi_device_id *id; | |
8ecbb3c3 LP |
1359 | |
1360 | id = acpi_match_device(dev->driver->acpi_match_table, dev); | |
1361 | ||
1362 | if (!id) | |
1363 | return NULL; | |
1364 | ||
e20008ed | 1365 | *data = (int)id->driver_data; |
8ecbb3c3 LP |
1366 | |
1367 | return dev_name(dev); | |
1368 | } | |
1369 | ||
1370 | static int bmc150_accel_gpio_probe(struct i2c_client *client, | |
e20008ed | 1371 | struct bmc150_accel_data *data) |
8ecbb3c3 | 1372 | { |
bd7fe5b7 SP |
1373 | struct device *dev; |
1374 | struct gpio_desc *gpio; | |
1375 | int ret; | |
1376 | ||
1377 | if (!client) | |
1378 | return -EINVAL; | |
1379 | ||
1380 | dev = &client->dev; | |
bd7fe5b7 SP |
1381 | |
1382 | /* data ready gpio interrupt pin */ | |
b457f53a | 1383 | gpio = devm_gpiod_get_index(dev, BMC150_ACCEL_GPIO_NAME, 0, GPIOD_IN); |
bd7fe5b7 | 1384 | if (IS_ERR(gpio)) { |
8ecbb3c3 | 1385 | dev_err(dev, "Failed: gpio get index\n"); |
bd7fe5b7 SP |
1386 | return PTR_ERR(gpio); |
1387 | } | |
1388 | ||
bd7fe5b7 SP |
1389 | ret = gpiod_to_irq(gpio); |
1390 | ||
1391 | dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret); | |
1392 | ||
1393 | return ret; | |
1394 | } | |
1395 | ||
7d963215 OP |
1396 | static const struct { |
1397 | int intr; | |
1398 | const char *name; | |
1399 | int (*setup)(struct bmc150_accel_trigger *t, bool state); | |
1400 | } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = { | |
1401 | { | |
1402 | .intr = 0, | |
1403 | .name = "%s-dev%d", | |
1404 | }, | |
1405 | { | |
1406 | .intr = 1, | |
1407 | .name = "%s-any-motion-dev%d", | |
1408 | .setup = bmc150_accel_any_motion_setup, | |
1409 | }, | |
1410 | }; | |
1411 | ||
1412 | static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data, | |
1413 | int from) | |
1414 | { | |
1415 | int i; | |
1416 | ||
1417 | for (i = from; i >= 0; i++) { | |
1418 | if (data->triggers[i].indio_trig) { | |
1419 | iio_trigger_unregister(data->triggers[i].indio_trig); | |
1420 | data->triggers[i].indio_trig = NULL; | |
1421 | } | |
1422 | } | |
1423 | } | |
1424 | ||
1425 | static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, | |
1426 | struct bmc150_accel_data *data) | |
1427 | { | |
1428 | int i, ret; | |
1429 | ||
1430 | for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { | |
1431 | struct bmc150_accel_trigger *t = &data->triggers[i]; | |
1432 | ||
1433 | t->indio_trig = devm_iio_trigger_alloc(&data->client->dev, | |
1434 | bmc150_accel_triggers[i].name, | |
1435 | indio_dev->name, | |
1436 | indio_dev->id); | |
1437 | if (!t->indio_trig) { | |
1438 | ret = -ENOMEM; | |
1439 | break; | |
1440 | } | |
1441 | ||
1442 | t->indio_trig->dev.parent = &data->client->dev; | |
1443 | t->indio_trig->ops = &bmc150_accel_trigger_ops; | |
1444 | t->intr = bmc150_accel_triggers[i].intr; | |
1445 | t->data = data; | |
1446 | t->setup = bmc150_accel_triggers[i].setup; | |
1447 | iio_trigger_set_drvdata(t->indio_trig, t); | |
1448 | ||
1449 | ret = iio_trigger_register(t->indio_trig); | |
1450 | if (ret) | |
1451 | break; | |
1452 | } | |
1453 | ||
1454 | if (ret) | |
1455 | bmc150_accel_unregister_triggers(data, i - 1); | |
1456 | ||
1457 | return ret; | |
1458 | } | |
1459 | ||
3bbec977 OP |
1460 | #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 |
1461 | #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 | |
1462 | #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 | |
1463 | ||
1464 | static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) | |
1465 | { | |
1466 | u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; | |
1467 | int ret; | |
1468 | ||
1469 | ret = i2c_smbus_write_byte_data(data->client, reg, data->fifo_mode); | |
1470 | if (ret < 0) { | |
1471 | dev_err(&data->client->dev, "Error writing reg_fifo_config1\n"); | |
1472 | return ret; | |
1473 | } | |
1474 | ||
1475 | if (!data->fifo_mode) | |
1476 | return 0; | |
1477 | ||
1478 | ret = i2c_smbus_write_byte_data(data->client, | |
1479 | BMC150_ACCEL_REG_FIFO_CONFIG0, | |
1480 | data->watermark); | |
1481 | if (ret < 0) | |
1482 | dev_err(&data->client->dev, "Error writing reg_fifo_config0\n"); | |
1483 | ||
1484 | return ret; | |
1485 | } | |
1486 | ||
c16bff48 VD |
1487 | static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev) |
1488 | { | |
1489 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1490 | ||
1491 | return bmc150_accel_set_power_state(data, true); | |
1492 | } | |
1493 | ||
3bbec977 OP |
1494 | static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) |
1495 | { | |
1496 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1497 | int ret = 0; | |
1498 | ||
1499 | if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) | |
1500 | return iio_triggered_buffer_postenable(indio_dev); | |
1501 | ||
1502 | mutex_lock(&data->mutex); | |
1503 | ||
1504 | if (!data->watermark) | |
1505 | goto out; | |
1506 | ||
1507 | ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, | |
1508 | true); | |
1509 | if (ret) | |
1510 | goto out; | |
1511 | ||
1512 | data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; | |
1513 | ||
1514 | ret = bmc150_accel_fifo_set_mode(data); | |
1515 | if (ret) { | |
1516 | data->fifo_mode = 0; | |
1517 | bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, | |
1518 | false); | |
1519 | } | |
1520 | ||
1521 | out: | |
1522 | mutex_unlock(&data->mutex); | |
1523 | ||
1524 | return ret; | |
1525 | } | |
1526 | ||
1527 | static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) | |
1528 | { | |
1529 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1530 | ||
1531 | if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) | |
1532 | return iio_triggered_buffer_predisable(indio_dev); | |
1533 | ||
1534 | mutex_lock(&data->mutex); | |
1535 | ||
1536 | if (!data->fifo_mode) | |
1537 | goto out; | |
1538 | ||
1539 | bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); | |
1540 | __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); | |
1541 | data->fifo_mode = 0; | |
1542 | bmc150_accel_fifo_set_mode(data); | |
1543 | ||
1544 | out: | |
1545 | mutex_unlock(&data->mutex); | |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
c16bff48 VD |
1550 | static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev) |
1551 | { | |
1552 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1553 | ||
1554 | return bmc150_accel_set_power_state(data, false); | |
1555 | } | |
1556 | ||
3bbec977 | 1557 | static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { |
c16bff48 | 1558 | .preenable = bmc150_accel_buffer_preenable, |
3bbec977 OP |
1559 | .postenable = bmc150_accel_buffer_postenable, |
1560 | .predisable = bmc150_accel_buffer_predisable, | |
c16bff48 | 1561 | .postdisable = bmc150_accel_buffer_postdisable, |
3bbec977 OP |
1562 | }; |
1563 | ||
c4eaab79 BN |
1564 | static int bmc150_accel_chip_init(struct bmc150_accel_data *data) |
1565 | { | |
1566 | int ret; | |
1567 | ||
1568 | ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_CHIP_ID); | |
1569 | if (ret < 0) { | |
1570 | dev_err(&data->client->dev, "Error: Reading chip id\n"); | |
1571 | return ret; | |
1572 | } | |
1573 | ||
1574 | dev_dbg(&data->client->dev, "Chip Id %x\n", ret); | |
1575 | if (ret != data->chip_info->chip_id) { | |
1576 | dev_err(&data->client->dev, "Invalid chip %x\n", ret); | |
1577 | return -ENODEV; | |
1578 | } | |
1579 | ||
1580 | ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); | |
1581 | if (ret < 0) | |
1582 | return ret; | |
1583 | ||
1584 | /* Set Bandwidth */ | |
1585 | ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); | |
1586 | if (ret < 0) | |
1587 | return ret; | |
1588 | ||
1589 | /* Set Default Range */ | |
1590 | ret = i2c_smbus_write_byte_data(data->client, | |
1591 | BMC150_ACCEL_REG_PMU_RANGE, | |
1592 | BMC150_ACCEL_DEF_RANGE_4G); | |
1593 | if (ret < 0) { | |
1594 | dev_err(&data->client->dev, "Error writing reg_pmu_range\n"); | |
1595 | return ret; | |
1596 | } | |
1597 | ||
1598 | data->range = BMC150_ACCEL_DEF_RANGE_4G; | |
1599 | ||
1600 | /* Set default slope duration and thresholds */ | |
1601 | data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; | |
1602 | data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION; | |
1603 | ret = bmc150_accel_update_slope(data); | |
1604 | if (ret < 0) | |
1605 | return ret; | |
1606 | ||
1607 | /* Set default as latched interrupts */ | |
1608 | ret = i2c_smbus_write_byte_data(data->client, | |
1609 | BMC150_ACCEL_REG_INT_RST_LATCH, | |
1610 | BMC150_ACCEL_INT_MODE_LATCH_INT | | |
1611 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | |
1612 | if (ret < 0) { | |
1613 | dev_err(&data->client->dev, | |
1614 | "Error writing reg_int_rst_latch\n"); | |
1615 | return ret; | |
1616 | } | |
1617 | ||
1618 | return 0; | |
1619 | } | |
1620 | ||
bd7fe5b7 SP |
1621 | static int bmc150_accel_probe(struct i2c_client *client, |
1622 | const struct i2c_device_id *id) | |
1623 | { | |
1624 | struct bmc150_accel_data *data; | |
1625 | struct iio_dev *indio_dev; | |
1626 | int ret; | |
8ecbb3c3 LP |
1627 | const char *name = NULL; |
1628 | int chip_id = 0; | |
bd7fe5b7 SP |
1629 | |
1630 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); | |
1631 | if (!indio_dev) | |
1632 | return -ENOMEM; | |
1633 | ||
1634 | data = iio_priv(indio_dev); | |
1635 | i2c_set_clientdata(client, indio_dev); | |
1636 | data->client = client; | |
1637 | ||
8ecbb3c3 LP |
1638 | if (id) { |
1639 | name = id->name; | |
1640 | chip_id = id->driver_data; | |
1641 | } | |
1642 | ||
1643 | if (ACPI_HANDLE(&client->dev)) | |
1644 | name = bmc150_accel_match_acpi_device(&client->dev, &chip_id); | |
1645 | ||
1646 | data->chip_info = &bmc150_accel_chip_info_tbl[chip_id]; | |
1647 | ||
bd7fe5b7 SP |
1648 | ret = bmc150_accel_chip_init(data); |
1649 | if (ret < 0) | |
1650 | return ret; | |
1651 | ||
1652 | mutex_init(&data->mutex); | |
1653 | ||
1654 | indio_dev->dev.parent = &client->dev; | |
8ecbb3c3 LP |
1655 | indio_dev->channels = data->chip_info->channels; |
1656 | indio_dev->num_channels = data->chip_info->num_channels; | |
1657 | indio_dev->name = name; | |
bd7fe5b7 SP |
1658 | indio_dev->modes = INDIO_DIRECT_MODE; |
1659 | indio_dev->info = &bmc150_accel_info; | |
1660 | ||
c16bff48 VD |
1661 | ret = iio_triggered_buffer_setup(indio_dev, |
1662 | &iio_pollfunc_store_time, | |
1663 | bmc150_accel_trigger_handler, | |
1664 | &bmc150_accel_buffer_ops); | |
1665 | if (ret < 0) { | |
1666 | dev_err(&client->dev, "Failed: iio triggered buffer setup\n"); | |
1667 | return ret; | |
1668 | } | |
1669 | ||
bd7fe5b7 | 1670 | if (client->irq < 0) |
8ecbb3c3 | 1671 | client->irq = bmc150_accel_gpio_probe(client, data); |
bd7fe5b7 | 1672 | |
c176becd | 1673 | if (client->irq > 0) { |
bd7fe5b7 SP |
1674 | ret = devm_request_threaded_irq( |
1675 | &client->dev, client->irq, | |
3bbec977 OP |
1676 | bmc150_accel_irq_handler, |
1677 | bmc150_accel_irq_thread_handler, | |
bd7fe5b7 SP |
1678 | IRQF_TRIGGER_RISING, |
1679 | BMC150_ACCEL_IRQ_NAME, | |
1680 | indio_dev); | |
1681 | if (ret) | |
c16bff48 | 1682 | goto err_buffer_cleanup; |
bd7fe5b7 | 1683 | |
8e22f477 OP |
1684 | /* |
1685 | * Set latched mode interrupt. While certain interrupts are | |
1686 | * non-latched regardless of this settings (e.g. new data) we | |
1687 | * want to use latch mode when we can to prevent interrupt | |
1688 | * flooding. | |
1689 | */ | |
1690 | ret = i2c_smbus_write_byte_data(data->client, | |
1691 | BMC150_ACCEL_REG_INT_RST_LATCH, | |
1692 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | |
1693 | if (ret < 0) { | |
1694 | dev_err(&data->client->dev, "Error writing reg_int_rst_latch\n"); | |
c16bff48 | 1695 | goto err_buffer_cleanup; |
8e22f477 OP |
1696 | } |
1697 | ||
3e825ec9 OP |
1698 | bmc150_accel_interrupts_setup(indio_dev, data); |
1699 | ||
7d963215 | 1700 | ret = bmc150_accel_triggers_setup(indio_dev, data); |
bd7fe5b7 | 1701 | if (ret) |
c16bff48 | 1702 | goto err_buffer_cleanup; |
3bbec977 OP |
1703 | |
1704 | if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) || | |
1705 | i2c_check_functionality(client->adapter, | |
1706 | I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { | |
1707 | indio_dev->modes |= INDIO_BUFFER_SOFTWARE; | |
1708 | indio_dev->info = &bmc150_accel_info_fifo; | |
1709 | indio_dev->buffer->attrs = bmc150_accel_fifo_attributes; | |
1710 | } | |
bd7fe5b7 SP |
1711 | } |
1712 | ||
1713 | ret = iio_device_register(indio_dev); | |
1714 | if (ret < 0) { | |
1715 | dev_err(&client->dev, "Unable to register iio device\n"); | |
c16bff48 | 1716 | goto err_trigger_unregister; |
bd7fe5b7 SP |
1717 | } |
1718 | ||
1719 | ret = pm_runtime_set_active(&client->dev); | |
1720 | if (ret) | |
1721 | goto err_iio_unregister; | |
1722 | ||
1723 | pm_runtime_enable(&client->dev); | |
1724 | pm_runtime_set_autosuspend_delay(&client->dev, | |
1725 | BMC150_AUTO_SUSPEND_DELAY_MS); | |
1726 | pm_runtime_use_autosuspend(&client->dev); | |
1727 | ||
1728 | return 0; | |
1729 | ||
1730 | err_iio_unregister: | |
1731 | iio_device_unregister(indio_dev); | |
bd7fe5b7 | 1732 | err_trigger_unregister: |
7d963215 | 1733 | bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); |
c16bff48 VD |
1734 | err_buffer_cleanup: |
1735 | iio_triggered_buffer_cleanup(indio_dev); | |
bd7fe5b7 SP |
1736 | |
1737 | return ret; | |
1738 | } | |
1739 | ||
1740 | static int bmc150_accel_remove(struct i2c_client *client) | |
1741 | { | |
1742 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | |
1743 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1744 | ||
1745 | pm_runtime_disable(&client->dev); | |
1746 | pm_runtime_set_suspended(&client->dev); | |
1747 | pm_runtime_put_noidle(&client->dev); | |
1748 | ||
1749 | iio_device_unregister(indio_dev); | |
1750 | ||
7d963215 | 1751 | bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); |
bd7fe5b7 | 1752 | |
c16bff48 VD |
1753 | iio_triggered_buffer_cleanup(indio_dev); |
1754 | ||
bd7fe5b7 SP |
1755 | mutex_lock(&data->mutex); |
1756 | bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); | |
1757 | mutex_unlock(&data->mutex); | |
1758 | ||
1759 | return 0; | |
1760 | } | |
1761 | ||
1762 | #ifdef CONFIG_PM_SLEEP | |
1763 | static int bmc150_accel_suspend(struct device *dev) | |
1764 | { | |
1765 | struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); | |
1766 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1767 | ||
1768 | mutex_lock(&data->mutex); | |
1769 | bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); | |
1770 | mutex_unlock(&data->mutex); | |
1771 | ||
1772 | return 0; | |
1773 | } | |
1774 | ||
1775 | static int bmc150_accel_resume(struct device *dev) | |
1776 | { | |
1777 | struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); | |
1778 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1779 | ||
1780 | mutex_lock(&data->mutex); | |
3e825ec9 | 1781 | if (atomic_read(&data->active_intr)) |
bd7fe5b7 | 1782 | bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); |
3bbec977 | 1783 | bmc150_accel_fifo_set_mode(data); |
bd7fe5b7 SP |
1784 | mutex_unlock(&data->mutex); |
1785 | ||
1786 | return 0; | |
1787 | } | |
1788 | #endif | |
1789 | ||
6f0a13f2 | 1790 | #ifdef CONFIG_PM |
bd7fe5b7 SP |
1791 | static int bmc150_accel_runtime_suspend(struct device *dev) |
1792 | { | |
1793 | struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); | |
1794 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
aaeecd80 | 1795 | int ret; |
bd7fe5b7 SP |
1796 | |
1797 | dev_dbg(&data->client->dev, __func__); | |
aaeecd80 SP |
1798 | ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); |
1799 | if (ret < 0) | |
1800 | return -EAGAIN; | |
bd7fe5b7 | 1801 | |
aaeecd80 | 1802 | return 0; |
bd7fe5b7 SP |
1803 | } |
1804 | ||
1805 | static int bmc150_accel_runtime_resume(struct device *dev) | |
1806 | { | |
1807 | struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); | |
1808 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1809 | int ret; | |
1810 | int sleep_val; | |
1811 | ||
1812 | dev_dbg(&data->client->dev, __func__); | |
1813 | ||
1814 | ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); | |
3bbec977 OP |
1815 | if (ret < 0) |
1816 | return ret; | |
1817 | ret = bmc150_accel_fifo_set_mode(data); | |
bd7fe5b7 SP |
1818 | if (ret < 0) |
1819 | return ret; | |
1820 | ||
1821 | sleep_val = bmc150_accel_get_startup_times(data); | |
1822 | if (sleep_val < 20) | |
1823 | usleep_range(sleep_val * 1000, 20000); | |
1824 | else | |
1825 | msleep_interruptible(sleep_val); | |
1826 | ||
1827 | return 0; | |
1828 | } | |
1829 | #endif | |
1830 | ||
1831 | static const struct dev_pm_ops bmc150_accel_pm_ops = { | |
1832 | SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) | |
1833 | SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, | |
1834 | bmc150_accel_runtime_resume, NULL) | |
1835 | }; | |
1836 | ||
1837 | static const struct acpi_device_id bmc150_accel_acpi_match[] = { | |
8ecbb3c3 LP |
1838 | {"BSBA0150", bmc150}, |
1839 | {"BMC150A", bmc150}, | |
1840 | {"BMI055A", bmi055}, | |
1841 | {"BMA0255", bma255}, | |
1842 | {"BMA250E", bma250e}, | |
1843 | {"BMA222E", bma222e}, | |
1844 | {"BMA0280", bma280}, | |
bd7fe5b7 SP |
1845 | { }, |
1846 | }; | |
1847 | MODULE_DEVICE_TABLE(acpi, bmc150_accel_acpi_match); | |
1848 | ||
1849 | static const struct i2c_device_id bmc150_accel_id[] = { | |
8ecbb3c3 LP |
1850 | {"bmc150_accel", bmc150}, |
1851 | {"bmi055_accel", bmi055}, | |
1852 | {"bma255", bma255}, | |
1853 | {"bma250e", bma250e}, | |
1854 | {"bma222e", bma222e}, | |
1855 | {"bma280", bma280}, | |
bd7fe5b7 SP |
1856 | {} |
1857 | }; | |
1858 | ||
1859 | MODULE_DEVICE_TABLE(i2c, bmc150_accel_id); | |
1860 | ||
1861 | static struct i2c_driver bmc150_accel_driver = { | |
1862 | .driver = { | |
1863 | .name = BMC150_ACCEL_DRV_NAME, | |
1864 | .acpi_match_table = ACPI_PTR(bmc150_accel_acpi_match), | |
1865 | .pm = &bmc150_accel_pm_ops, | |
1866 | }, | |
1867 | .probe = bmc150_accel_probe, | |
1868 | .remove = bmc150_accel_remove, | |
1869 | .id_table = bmc150_accel_id, | |
1870 | }; | |
1871 | module_i2c_driver(bmc150_accel_driver); | |
1872 | ||
1873 | MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); | |
1874 | MODULE_LICENSE("GPL v2"); | |
1875 | MODULE_DESCRIPTION("BMC150 accelerometer driver"); |