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iio: mma8452: whitespace cleanup
[mirror_ubuntu-zesty-kernel.git] / drivers / iio / accel / mma8452.c
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c7eeea93 1/*
c5ea1b58
MK		 2 * mma8452.c - Support for following Freescale 3-axis accelerometers:
3 *
4 * MMA8452Q (12 bit)
5 * MMA8453Q (10 bit)
417e008b
MK		 6 * MMA8652FC (12 bit)
7 * MMA8653FC (10 bit)
c7eeea93 8 *
d6223c37 9 * Copyright 2015 Martin Kepplinger <martin.kepplinger@theobroma-systems.com>
c7eeea93
PM		 10 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
11 *
12 * This file is subject to the terms and conditions of version 2 of
13 * the GNU General Public License. See the file COPYING in the main
14 * directory of this archive for more details.
15 *
16 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
17 *
4b04266a 18 * TODO: orientation events, autosleep
c7eeea93
PM		 19 */
20
21#include <linux/module.h>
22#include <linux/i2c.h>
23#include <linux/iio/iio.h>
24#include <linux/iio/sysfs.h>
c7eeea93 25#include <linux/iio/buffer.h>
ae6d9ce0
MF		 26#include <linux/iio/trigger.h>
27#include <linux/iio/trigger_consumer.h>
c7eeea93 28#include <linux/iio/triggered_buffer.h>
28e34278 29#include <linux/iio/events.h>
c7eeea93 30#include <linux/delay.h>
c3cdd6e4 31#include <linux/of_device.h>
d2a3e093 32#include <linux/of_irq.h>
c7eeea93 33
69abff81
HK		 34#define MMA8452_STATUS 0x00
35#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
c5ea1b58 36#define MMA8452_OUT_X 0x01 /* MSB first */
69abff81
HK		 37#define MMA8452_OUT_Y 0x03
38#define MMA8452_OUT_Z 0x05
39#define MMA8452_INT_SRC 0x0c
40#define MMA8452_WHO_AM_I 0x0d
41#define MMA8452_DATA_CFG 0x0e
42#define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
43#define MMA8452_DATA_CFG_FS_2G 0
44#define MMA8452_DATA_CFG_FS_4G 1
45#define MMA8452_DATA_CFG_FS_8G 2
46#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
47#define MMA8452_HP_FILTER_CUTOFF 0x0f
48#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
60f562e7
MK		 49#define MMA8452_FF_MT_CFG 0x15
50#define MMA8452_FF_MT_CFG_OAE BIT(6)
51#define MMA8452_FF_MT_CFG_ELE BIT(7)
52#define MMA8452_FF_MT_SRC 0x16
53#define MMA8452_FF_MT_SRC_XHE BIT(1)
54#define MMA8452_FF_MT_SRC_YHE BIT(3)
55#define MMA8452_FF_MT_SRC_ZHE BIT(5)
56#define MMA8452_FF_MT_THS 0x17
57#define MMA8452_FF_MT_THS_MASK 0x7f
58#define MMA8452_FF_MT_COUNT 0x18
69abff81
HK		 59#define MMA8452_TRANSIENT_CFG 0x1d
60#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
69abff81
HK		 61#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
62#define MMA8452_TRANSIENT_SRC 0x1e
63#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
64#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
65#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
66#define MMA8452_TRANSIENT_THS 0x1f
67#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
68#define MMA8452_TRANSIENT_COUNT 0x20
69#define MMA8452_CTRL_REG1 0x2a
70#define MMA8452_CTRL_ACTIVE BIT(0)
71#define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
72#define MMA8452_CTRL_DR_SHIFT 3
73#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
74#define MMA8452_CTRL_REG2 0x2b
75#define MMA8452_CTRL_REG2_RST BIT(6)
76#define MMA8452_CTRL_REG4 0x2d
77#define MMA8452_CTRL_REG5 0x2e
78#define MMA8452_OFF_X 0x2f
79#define MMA8452_OFF_Y 0x30
80#define MMA8452_OFF_Z 0x31
c7eeea93 81
69abff81 82#define MMA8452_MAX_REG 0x31
2a17698c 83
69abff81 84#define MMA8452_INT_DRDY BIT(0)
60f562e7 85#define MMA8452_INT_FF_MT BIT(2)
69abff81 86#define MMA8452_INT_TRANS BIT(5)
c7eeea93 87
36775d57
MK		 88#define MMA8452_DEVICE_ID 0x2a
89#define MMA8453_DEVICE_ID 0x3a
417e008b
MK		 90#define MMA8652_DEVICE_ID 0x4a
91#define MMA8653_DEVICE_ID 0x5a
c7eeea93
PM		 92
93struct mma8452_data {
94 struct i2c_client *client;
95 struct mutex lock;
96 u8 ctrl_reg1;
97 u8 data_cfg;
c3cdd6e4
MK		 98 const struct mma_chip_info *chip_info;
99};
100
101/**
102 * struct mma_chip_info - chip specific data for Freescale's accelerometers
103 * @chip_id: WHO_AM_I register's value
104 * @channels: struct iio_chan_spec matching the device's
105 * capabilities
106 * @num_channels: number of channels
107 * @mma_scales: scale factors for converting register values
108 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
109 * per mode: m/s^2 and micro m/s^2
110 * @ev_cfg: event config register address
111 * @ev_cfg_ele: latch bit in event config register
112 * @ev_cfg_chan_shift: number of the bit to enable events in X
113 * direction; in event config register
114 * @ev_src: event source register address
115 * @ev_src_xe: bit in event source register that indicates
116 * an event in X direction
117 * @ev_src_ye: bit in event source register that indicates
118 * an event in Y direction
119 * @ev_src_ze: bit in event source register that indicates
120 * an event in Z direction
121 * @ev_ths: event threshold register address
122 * @ev_ths_mask: mask for the threshold value
123 * @ev_count: event count (period) register address
124 *
125 * Since not all chips supported by the driver support comparing high pass
126 * filtered data for events (interrupts), different interrupt sources are
127 * used for different chips and the relevant registers are included here.
128 */
129struct mma_chip_info {
130 u8 chip_id;
131 const struct iio_chan_spec *channels;
132 int num_channels;
133 const int mma_scales[3][2];
134 u8 ev_cfg;
135 u8 ev_cfg_ele;
136 u8 ev_cfg_chan_shift;
137 u8 ev_src;
138 u8 ev_src_xe;
139 u8 ev_src_ye;
140 u8 ev_src_ze;
141 u8 ev_ths;
142 u8 ev_ths_mask;
143 u8 ev_count;
c7eeea93
PM		 144};
145
e60378c1
MK		 146enum {
147 idx_x,
148 idx_y,
149 idx_z,
150 idx_ts,
151};
152
c7eeea93
PM		 153static int mma8452_drdy(struct mma8452_data *data)
154{
155 int tries = 150;
156
157 while (tries-- > 0) {
158 int ret = i2c_smbus_read_byte_data(data->client,
159 MMA8452_STATUS);
160 if (ret < 0)
161 return ret;
162 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
163 return 0;
686027fb 164
c7eeea93
PM		 165 msleep(20);
166 }
167
168 dev_err(&data->client->dev, "data not ready\n");
686027fb 169
c7eeea93
PM		 170 return -EIO;
171}
172
173static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
174{
175 int ret = mma8452_drdy(data);
686027fb 176
c7eeea93
PM		 177 if (ret < 0)
178 return ret;
686027fb
HK		 179
180 return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
181 3 * sizeof(__be16), (u8 *)buf);
c7eeea93
PM		 182}
183
686027fb
HK		 184static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
185 int n)
c7eeea93
PM		 186{
187 size_t len = 0;
188
189 while (n-- > 0)
686027fb
HK		 190 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
191 vals[n][0], vals[n][1]);
c7eeea93
PM		 192
193 /* replace trailing space by newline */
194 buf[len - 1] = '\n';
195
196 return len;
197}
198
199static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
686027fb 200 int val, int val2)
c7eeea93
PM		 201{
202 while (n-- > 0)
203 if (val == vals[n][0] && val2 == vals[n][1])
204 return n;
205
206 return -EINVAL;
207}
208
5dbbd19f
MF		 209static int mma8452_get_odr_index(struct mma8452_data *data)
210{
211 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
212 MMA8452_CTRL_DR_SHIFT;
213}
214
c7eeea93
PM		 215static const int mma8452_samp_freq[8][2] = {
216 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
217 {6, 250000}, {1, 560000}
218};
219
5dbbd19f
MF		 220/* Datasheet table 35 (step time vs sample frequency) */
221static const int mma8452_transient_time_step_us[8] = {
222 1250,
223 2500,
224 5000,
225 10000,
226 20000,
227 20000,
228 20000,
229 20000
230};
231
1e79841a
MF		 232/* Datasheet table 18 (normal mode) */
233static const int mma8452_hp_filter_cutoff[8][4][2] = {
234 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
235 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
236 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
237 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
238 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
239 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
240 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
241 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
242};
243
c7eeea93 244static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
686027fb
HK		 245 struct device_attribute *attr,
246 char *buf)
c7eeea93
PM		 247{
248 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
686027fb 249 ARRAY_SIZE(mma8452_samp_freq));
c7eeea93
PM		 250}
251
252static ssize_t mma8452_show_scale_avail(struct device *dev,
686027fb
HK		 253 struct device_attribute *attr,
254 char *buf)
c7eeea93 255{
c3cdd6e4
MK		 256 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
257 to_i2c_client(dev)));
258
259 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
260 ARRAY_SIZE(data->chip_info->mma_scales));
c7eeea93
PM		 261}
262
1e79841a
MF		 263static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
264 struct device_attribute *attr,
265 char *buf)
266{
267 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
268 struct mma8452_data *data = iio_priv(indio_dev);
269 int i = mma8452_get_odr_index(data);
270
271 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
272 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
273}
274
c7eeea93
PM		 275static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
276static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
686027fb 277 mma8452_show_scale_avail, NULL, 0);
1e79841a 278static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
686027fb 279 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
c7eeea93
PM		 280
281static int mma8452_get_samp_freq_index(struct mma8452_data *data,
686027fb 282 int val, int val2)
c7eeea93
PM		 283{
284 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
686027fb
HK		 285 ARRAY_SIZE(mma8452_samp_freq),
286 val, val2);
c7eeea93
PM		 287}
288
686027fb 289static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
c7eeea93 290{
c3cdd6e4
MK		 291 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
292 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
c7eeea93
PM		 293}
294
1e79841a
MF		 295static int mma8452_get_hp_filter_index(struct mma8452_data *data,
296 int val, int val2)
297{
298 int i = mma8452_get_odr_index(data);
299
300 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
001fceb9 301 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
1e79841a
MF		 302}
303
304static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
305{
306 int i, ret;
307
308 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
309 if (ret < 0)
310 return ret;
311
312 i = mma8452_get_odr_index(data);
313 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
314 *hz = mma8452_hp_filter_cutoff[i][ret][0];
315 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
316
317 return 0;
318}
319
c7eeea93
PM		 320static int mma8452_read_raw(struct iio_dev *indio_dev,
321 struct iio_chan_spec const *chan,
322 int *val, int *val2, long mask)
323{
324 struct mma8452_data *data = iio_priv(indio_dev);
325 __be16 buffer[3];
326 int i, ret;
327
328 switch (mask) {
329 case IIO_CHAN_INFO_RAW:
330 if (iio_buffer_enabled(indio_dev))
331 return -EBUSY;
332
333 mutex_lock(&data->lock);
334 ret = mma8452_read(data, buffer);
335 mutex_unlock(&data->lock);
336 if (ret < 0)
337 return ret;
686027fb 338
c3cdd6e4
MK		 339 *val = sign_extend32(be16_to_cpu(
340 buffer[chan->scan_index]) >> chan->scan_type.shift,
341 chan->scan_type.realbits - 1);
686027fb 342
c7eeea93
PM		 343 return IIO_VAL_INT;
344 case IIO_CHAN_INFO_SCALE:
345 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
c3cdd6e4
MK		 346 *val = data->chip_info->mma_scales[i][0];
347 *val2 = data->chip_info->mma_scales[i][1];
686027fb 348
c7eeea93
PM		 349 return IIO_VAL_INT_PLUS_MICRO;
350 case IIO_CHAN_INFO_SAMP_FREQ:
5dbbd19f 351 i = mma8452_get_odr_index(data);
c7eeea93
PM		 352 *val = mma8452_samp_freq[i][0];
353 *val2 = mma8452_samp_freq[i][1];
686027fb 354
c7eeea93
PM		 355 return IIO_VAL_INT_PLUS_MICRO;
356 case IIO_CHAN_INFO_CALIBBIAS:
686027fb
HK		 357 ret = i2c_smbus_read_byte_data(data->client,
358 MMA8452_OFF_X + chan->scan_index);
c7eeea93
PM		 359 if (ret < 0)
360 return ret;
686027fb 361
c7eeea93 362 *val = sign_extend32(ret, 7);
686027fb 363
c7eeea93 364 return IIO_VAL_INT;
1e79841a
MF		 365 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
366 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
367 ret = mma8452_read_hp_filter(data, val, val2);
368 if (ret < 0)
369 return ret;
370 } else {
371 *val = 0;
372 *val2 = 0;
373 }
686027fb 374
1e79841a 375 return IIO_VAL_INT_PLUS_MICRO;
c7eeea93 376 }
686027fb 377
c7eeea93
PM		 378 return -EINVAL;
379}
380
381static int mma8452_standby(struct mma8452_data *data)
382{
383 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
686027fb 384 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
c7eeea93
PM		 385}
386
387static int mma8452_active(struct mma8452_data *data)
388{
389 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
686027fb 390 data->ctrl_reg1);
c7eeea93
PM		 391}
392
393static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
394{
395 int ret;
396
397 mutex_lock(&data->lock);
398
399 /* config can only be changed when in standby */
400 ret = mma8452_standby(data);
401 if (ret < 0)
402 goto fail;
403
404 ret = i2c_smbus_write_byte_data(data->client, reg, val);
405 if (ret < 0)
406 goto fail;
407
408 ret = mma8452_active(data);
409 if (ret < 0)
410 goto fail;
411
412 ret = 0;
413fail:
414 mutex_unlock(&data->lock);
686027fb 415
c7eeea93
PM		 416 return ret;
417}
418
4b04266a
MK		 419/* returns >0 if in freefall mode, 0 if not or <0 if an error occured */
420static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
421{
422 int val;
423 const struct mma_chip_info *chip = data->chip_info;
424
425 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
426 if (val < 0)
427 return val;
428
429 return !(val & MMA8452_FF_MT_CFG_OAE);
430}
431
432static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
433{
434 int val;
435 const struct mma_chip_info *chip = data->chip_info;
436
437 if ((state && mma8452_freefall_mode_enabled(data)) ||
438 (!state && !(mma8452_freefall_mode_enabled(data))))
439 return 0;
440
441 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
442 if (val < 0)
443 return val;
444
445 if (state) {
446 val |= BIT(idx_x + chip->ev_cfg_chan_shift);
447 val |= BIT(idx_y + chip->ev_cfg_chan_shift);
448 val |= BIT(idx_z + chip->ev_cfg_chan_shift);
449 val &= ~MMA8452_FF_MT_CFG_OAE;
450 } else {
451 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
452 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
453 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
454 val |= MMA8452_FF_MT_CFG_OAE;
455 }
456
457 val = mma8452_change_config(data, chip->ev_cfg, val);
458 if (val)
459 return val;
460
461 return 0;
462}
463
1e79841a
MF		 464static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
465 int val, int val2)
466{
467 int i, reg;
468
469 i = mma8452_get_hp_filter_index(data, val, val2);
470 if (i < 0)
b9fddcdb 471 return i;
1e79841a
MF		 472
473 reg = i2c_smbus_read_byte_data(data->client,
474 MMA8452_HP_FILTER_CUTOFF);
475 if (reg < 0)
476 return reg;
686027fb 477
1e79841a
MF		 478 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
479 reg |= i;
480
481 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
482}
483
c7eeea93
PM		 484static int mma8452_write_raw(struct iio_dev *indio_dev,
485 struct iio_chan_spec const *chan,
486 int val, int val2, long mask)
487{
488 struct mma8452_data *data = iio_priv(indio_dev);
1e79841a 489 int i, ret;
c7eeea93
PM		 490
491 if (iio_buffer_enabled(indio_dev))
492 return -EBUSY;
493
494 switch (mask) {
495 case IIO_CHAN_INFO_SAMP_FREQ:
496 i = mma8452_get_samp_freq_index(data, val, val2);
497 if (i < 0)
b9fddcdb 498 return i;
c7eeea93
PM		 499
500 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
501 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
686027fb 502
c7eeea93 503 return mma8452_change_config(data, MMA8452_CTRL_REG1,
686027fb 504 data->ctrl_reg1);
c7eeea93
PM		 505 case IIO_CHAN_INFO_SCALE:
506 i = mma8452_get_scale_index(data, val, val2);
507 if (i < 0)
b9fddcdb 508 return i;
686027fb 509
c7eeea93
PM		 510 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
511 data->data_cfg |= i;
686027fb 512
c7eeea93 513 return mma8452_change_config(data, MMA8452_DATA_CFG,
686027fb 514 data->data_cfg);
c7eeea93
PM		 515 case IIO_CHAN_INFO_CALIBBIAS:
516 if (val < -128 || val > 127)
517 return -EINVAL;
686027fb
HK		 518
519 return mma8452_change_config(data,
520 MMA8452_OFF_X + chan->scan_index,
521 val);
1e79841a
MF		 522
523 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
524 if (val == 0 && val2 == 0) {
525 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
526 } else {
527 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
528 ret = mma8452_set_hp_filter_frequency(data, val, val2);
529 if (ret < 0)
530 return ret;
531 }
686027fb 532
1e79841a 533 return mma8452_change_config(data, MMA8452_DATA_CFG,
686027fb 534 data->data_cfg);
1e79841a 535
c7eeea93
PM		 536 default:
537 return -EINVAL;
538 }
539}
540
28e34278
MF		 541static int mma8452_read_thresh(struct iio_dev *indio_dev,
542 const struct iio_chan_spec *chan,
543 enum iio_event_type type,
544 enum iio_event_direction dir,
545 enum iio_event_info info,
546 int *val, int *val2)
547{
548 struct mma8452_data *data = iio_priv(indio_dev);
5dbbd19f 549 int ret, us;
28e34278 550
5dbbd19f
MF		 551 switch (info) {
552 case IIO_EV_INFO_VALUE:
553 ret = i2c_smbus_read_byte_data(data->client,
c3cdd6e4 554 data->chip_info->ev_ths);
5dbbd19f
MF		 555 if (ret < 0)
556 return ret;
557
c3cdd6e4 558 *val = ret & data->chip_info->ev_ths_mask;
686027fb 559
5dbbd19f 560 return IIO_VAL_INT;
28e34278 561
5dbbd19f
MF		 562 case IIO_EV_INFO_PERIOD:
563 ret = i2c_smbus_read_byte_data(data->client,
c3cdd6e4 564 data->chip_info->ev_count);
5dbbd19f
MF		 565 if (ret < 0)
566 return ret;
567
568 us = ret * mma8452_transient_time_step_us[
569 mma8452_get_odr_index(data)];
570 *val = us / USEC_PER_SEC;
571 *val2 = us % USEC_PER_SEC;
686027fb 572
5dbbd19f 573 return IIO_VAL_INT_PLUS_MICRO;
28e34278 574
1e79841a
MF		 575 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
576 ret = i2c_smbus_read_byte_data(data->client,
577 MMA8452_TRANSIENT_CFG);
578 if (ret < 0)
579 return ret;
580
581 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
582 *val = 0;
583 *val2 = 0;
584 } else {
585 ret = mma8452_read_hp_filter(data, val, val2);
586 if (ret < 0)
587 return ret;
588 }
686027fb 589
1e79841a
MF		 590 return IIO_VAL_INT_PLUS_MICRO;
591
5dbbd19f
MF		 592 default:
593 return -EINVAL;
594 }
28e34278
MF		 595}
596
597static int mma8452_write_thresh(struct iio_dev *indio_dev,
598 const struct iio_chan_spec *chan,
599 enum iio_event_type type,
600 enum iio_event_direction dir,
601 enum iio_event_info info,
602 int val, int val2)
603{
604 struct mma8452_data *data = iio_priv(indio_dev);
1e79841a 605 int ret, reg, steps;
28e34278 606
5dbbd19f
MF		 607 switch (info) {
608 case IIO_EV_INFO_VALUE:
11218226
HK		 609 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
610 return -EINVAL;
611
c3cdd6e4
MK		 612 return mma8452_change_config(data, data->chip_info->ev_ths,
613 val);
5dbbd19f
MF		 614
615 case IIO_EV_INFO_PERIOD:
616 steps = (val * USEC_PER_SEC + val2) /
617 mma8452_transient_time_step_us[
618 mma8452_get_odr_index(data)];
619
11218226 620 if (steps < 0 || steps > 0xff)
5dbbd19f
MF		 621 return -EINVAL;
622
c3cdd6e4 623 return mma8452_change_config(data, data->chip_info->ev_count,
5dbbd19f 624 steps);
686027fb 625
1e79841a
MF		 626 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
627 reg = i2c_smbus_read_byte_data(data->client,
628 MMA8452_TRANSIENT_CFG);
629 if (reg < 0)
630 return reg;
631
632 if (val == 0 && val2 == 0) {
633 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
634 } else {
635 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
636 ret = mma8452_set_hp_filter_frequency(data, val, val2);
637 if (ret < 0)
638 return ret;
639 }
686027fb 640
1e79841a
MF		 641 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
642
5dbbd19f
MF		 643 default:
644 return -EINVAL;
645 }
28e34278
MF		 646}
647
648static int mma8452_read_event_config(struct iio_dev *indio_dev,
649 const struct iio_chan_spec *chan,
650 enum iio_event_type type,
651 enum iio_event_direction dir)
652{
653 struct mma8452_data *data = iio_priv(indio_dev);
c3cdd6e4 654 const struct mma_chip_info *chip = data->chip_info;
28e34278
MF		 655 int ret;
656
4b04266a
MK		 657 switch (dir) {
658 case IIO_EV_DIR_FALLING:
659 return mma8452_freefall_mode_enabled(data);
660 case IIO_EV_DIR_RISING:
661 if (mma8452_freefall_mode_enabled(data))
662 return 0;
663
664 ret = i2c_smbus_read_byte_data(data->client,
665 data->chip_info->ev_cfg);
666 if (ret < 0)
667 return ret;
28e34278 668
4b04266a
MK		 669 return !!(ret & BIT(chan->scan_index + chip->ev_cfg_chan_shift));
670 default:
671 return -EINVAL;
672 }
28e34278
MF		 673}
674
675static int mma8452_write_event_config(struct iio_dev *indio_dev,
676 const struct iio_chan_spec *chan,
677 enum iio_event_type type,
678 enum iio_event_direction dir,
679 int state)
680{
681 struct mma8452_data *data = iio_priv(indio_dev);
c3cdd6e4 682 const struct mma_chip_info *chip = data->chip_info;
28e34278
MF		 683 int val;
684
4b04266a
MK		 685 switch (dir) {
686 case IIO_EV_DIR_FALLING:
687 return mma8452_set_freefall_mode(data, state);
688 case IIO_EV_DIR_RISING:
689 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
690 if (val < 0)
691 return val;
692
693 if (state) {
694 if (mma8452_freefall_mode_enabled(data)) {
695 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
696 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
697 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
698 val |= MMA8452_FF_MT_CFG_OAE;
699 }
700 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
701 } else {
702 if (mma8452_freefall_mode_enabled(data))
703 return 0;
28e34278 704
4b04266a
MK		 705 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
706 }
28e34278 707
4b04266a 708 val |= chip->ev_cfg_ele;
28e34278 709
4b04266a
MK		 710 return mma8452_change_config(data, chip->ev_cfg, val);
711 default:
712 return -EINVAL;
713 }
28e34278
MF		 714}
715
716static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
717{
718 struct mma8452_data *data = iio_priv(indio_dev);
719 s64 ts = iio_get_time_ns();
720 int src;
721
c3cdd6e4 722 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
28e34278
MF		 723 if (src < 0)
724 return;
725
4b04266a
MK		 726 if (mma8452_freefall_mode_enabled(data)) {
727 iio_push_event(indio_dev,
728 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
729 IIO_MOD_X_AND_Y_AND_Z,
730 IIO_EV_TYPE_MAG,
731 IIO_EV_DIR_FALLING),
732 ts);
733 return;
734 }
735
c3cdd6e4 736 if (src & data->chip_info->ev_src_xe)
28e34278
MF		 737 iio_push_event(indio_dev,
738 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
c5d0db06 739 IIO_EV_TYPE_MAG,
28e34278
MF		 740 IIO_EV_DIR_RISING),
741 ts);
742
c3cdd6e4 743 if (src & data->chip_info->ev_src_ye)
28e34278
MF		 744 iio_push_event(indio_dev,
745 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
c5d0db06 746 IIO_EV_TYPE_MAG,
28e34278
MF		 747 IIO_EV_DIR_RISING),
748 ts);
749
c3cdd6e4 750 if (src & data->chip_info->ev_src_ze)
28e34278
MF		 751 iio_push_event(indio_dev,
752 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
c5d0db06 753 IIO_EV_TYPE_MAG,
28e34278
MF		 754 IIO_EV_DIR_RISING),
755 ts);
756}
757
758static irqreturn_t mma8452_interrupt(int irq, void *p)
759{
760 struct iio_dev *indio_dev = p;
761 struct mma8452_data *data = iio_priv(indio_dev);
60f562e7 762 const struct mma_chip_info *chip = data->chip_info;
ae6d9ce0 763 int ret = IRQ_NONE;
28e34278
MF		 764 int src;
765
766 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
767 if (src < 0)
768 return IRQ_NONE;
769
ae6d9ce0
MF		 770 if (src & MMA8452_INT_DRDY) {
771 iio_trigger_poll_chained(indio_dev->trig);
772 ret = IRQ_HANDLED;
773 }
774
60f562e7
MK		 775 if ((src & MMA8452_INT_TRANS &&
776 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
777 (src & MMA8452_INT_FF_MT &&
778 chip->ev_src == MMA8452_FF_MT_SRC)) {
28e34278 779 mma8452_transient_interrupt(indio_dev);
ae6d9ce0 780 ret = IRQ_HANDLED;
28e34278
MF		 781 }
782
ae6d9ce0 783 return ret;
28e34278
MF		 784}
785
c7eeea93
PM		 786static irqreturn_t mma8452_trigger_handler(int irq, void *p)
787{
788 struct iio_poll_func *pf = p;
789 struct iio_dev *indio_dev = pf->indio_dev;
790 struct mma8452_data *data = iio_priv(indio_dev);
791 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
792 int ret;
793
686027fb 794 ret = mma8452_read(data, (__be16 *)buffer);
c7eeea93
PM		 795 if (ret < 0)
796 goto done;
797
798 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
686027fb 799 iio_get_time_ns());
c7eeea93
PM		 800
801done:
802 iio_trigger_notify_done(indio_dev->trig);
686027fb 803
c7eeea93
PM		 804 return IRQ_HANDLED;
805}
806
2a17698c
MF		 807static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
808 unsigned reg, unsigned writeval,
809 unsigned *readval)
810{
811 int ret;
812 struct mma8452_data *data = iio_priv(indio_dev);
813
814 if (reg > MMA8452_MAX_REG)
815 return -EINVAL;
816
817 if (!readval)
818 return mma8452_change_config(data, reg, writeval);
819
820 ret = i2c_smbus_read_byte_data(data->client, reg);
821 if (ret < 0)
822 return ret;
823
824 *readval = ret;
825
826 return 0;
827}
828
4b04266a
MK		 829static const struct iio_event_spec mma8452_freefall_event[] = {
830 {
831 .type = IIO_EV_TYPE_MAG,
832 .dir = IIO_EV_DIR_FALLING,
833 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
834 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
835 BIT(IIO_EV_INFO_PERIOD) |
836 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
837 },
838};
839
840static const struct iio_event_spec mma8652_freefall_event[] = {
841 {
842 .type = IIO_EV_TYPE_MAG,
843 .dir = IIO_EV_DIR_FALLING,
844 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
845 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
846 BIT(IIO_EV_INFO_PERIOD)
847 },
848};
849
28e34278
MF		 850static const struct iio_event_spec mma8452_transient_event[] = {
851 {
c5d0db06 852 .type = IIO_EV_TYPE_MAG,
28e34278
MF		 853 .dir = IIO_EV_DIR_RISING,
854 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
5dbbd19f 855 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1e79841a
MF		 856 BIT(IIO_EV_INFO_PERIOD) |
857 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
28e34278
MF		 858 },
859};
860
60f562e7
MK		 861static const struct iio_event_spec mma8452_motion_event[] = {
862 {
863 .type = IIO_EV_TYPE_MAG,
864 .dir = IIO_EV_DIR_RISING,
865 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
866 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
867 BIT(IIO_EV_INFO_PERIOD)
868 },
869};
870
28e34278
MF		 871/*
872 * Threshold is configured in fixed 8G/127 steps regardless of
873 * currently selected scale for measurement.
874 */
875static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
876
877static struct attribute *mma8452_event_attributes[] = {
878 &iio_const_attr_accel_transient_scale.dev_attr.attr,
879 NULL,
880};
881
882static struct attribute_group mma8452_event_attribute_group = {
883 .attrs = mma8452_event_attributes,
28e34278
MF		 884};
885
4b04266a
MK		 886#define MMA8452_FREEFALL_CHANNEL(modifier) { \
887 .type = IIO_ACCEL, \
888 .modified = 1, \
889 .channel2 = modifier, \
890 .scan_index = -1, \
891 .event_spec = mma8452_freefall_event, \
892 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
893}
894
895#define MMA8652_FREEFALL_CHANNEL(modifier) { \
896 .type = IIO_ACCEL, \
897 .modified = 1, \
898 .channel2 = modifier, \
899 .scan_index = -1, \
900 .event_spec = mma8652_freefall_event, \
901 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
902}
903
c3cdd6e4 904#define MMA8452_CHANNEL(axis, idx, bits) { \
c7eeea93
PM		 905 .type = IIO_ACCEL, \
906 .modified = 1, \
907 .channel2 = IIO_MOD_##axis, \
908 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
686027fb 909 BIT(IIO_CHAN_INFO_CALIBBIAS), \
c7eeea93 910 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
686027fb
HK		 911 BIT(IIO_CHAN_INFO_SCALE) | \
912 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
c7eeea93
PM		 913 .scan_index = idx, \
914 .scan_type = { \
915 .sign = 's', \
c3cdd6e4 916 .realbits = (bits), \
c7eeea93 917 .storagebits = 16, \
c3cdd6e4 918 .shift = 16 - (bits), \
c7eeea93
PM		 919 .endianness = IIO_BE, \
920 }, \
28e34278
MF		 921 .event_spec = mma8452_transient_event, \
922 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
c7eeea93
PM		 923}
924
417e008b
MK		 925#define MMA8652_CHANNEL(axis, idx, bits) { \
926 .type = IIO_ACCEL, \
927 .modified = 1, \
928 .channel2 = IIO_MOD_##axis, \
929 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
930 BIT(IIO_CHAN_INFO_CALIBBIAS), \
931 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
932 BIT(IIO_CHAN_INFO_SCALE), \
933 .scan_index = idx, \
934 .scan_type = { \
935 .sign = 's', \
936 .realbits = (bits), \
937 .storagebits = 16, \
938 .shift = 16 - (bits), \
939 .endianness = IIO_BE, \
940 }, \
941 .event_spec = mma8452_motion_event, \
942 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
943}
944
c7eeea93 945static const struct iio_chan_spec mma8452_channels[] = {
e60378c1
MK		 946 MMA8452_CHANNEL(X, idx_x, 12),
947 MMA8452_CHANNEL(Y, idx_y, 12),
948 MMA8452_CHANNEL(Z, idx_z, 12),
949 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
4b04266a 950 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
c7eeea93
PM		 951};
952
c5ea1b58 953static const struct iio_chan_spec mma8453_channels[] = {
e60378c1
MK		 954 MMA8452_CHANNEL(X, idx_x, 10),
955 MMA8452_CHANNEL(Y, idx_y, 10),
956 MMA8452_CHANNEL(Z, idx_z, 10),
957 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
4b04266a 958 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
c5ea1b58
MK		 959};
960
417e008b 961static const struct iio_chan_spec mma8652_channels[] = {
e60378c1
MK		 962 MMA8652_CHANNEL(X, idx_x, 12),
963 MMA8652_CHANNEL(Y, idx_y, 12),
964 MMA8652_CHANNEL(Z, idx_z, 12),
965 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
4b04266a 966 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
417e008b
MK		 967};
968
969static const struct iio_chan_spec mma8653_channels[] = {
e60378c1
MK		 970 MMA8652_CHANNEL(X, idx_x, 10),
971 MMA8652_CHANNEL(Y, idx_y, 10),
972 MMA8652_CHANNEL(Z, idx_z, 10),
973 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
4b04266a 974 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
417e008b
MK		 975};
976
c3cdd6e4
MK		 977enum {
978 mma8452,
c5ea1b58 979 mma8453,
417e008b
MK		 980 mma8652,
981 mma8653,
c3cdd6e4
MK		 982};
983
984static const struct mma_chip_info mma_chip_info_table[] = {
985 [mma8452] = {
986 .chip_id = MMA8452_DEVICE_ID,
987 .channels = mma8452_channels,
988 .num_channels = ARRAY_SIZE(mma8452_channels),
989 /*
990 * Hardware has fullscale of -2G, -4G, -8G corresponding to
991 * raw value -2048 for 12 bit or -512 for 10 bit.
992 * The userspace interface uses m/s^2 and we declare micro units
993 * So scale factor for 12 bit here is given by:
994 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
995 */
996 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
997 .ev_cfg = MMA8452_TRANSIENT_CFG,
998 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
999 .ev_cfg_chan_shift = 1,
1000 .ev_src = MMA8452_TRANSIENT_SRC,
1001 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1002 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1003 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1004 .ev_ths = MMA8452_TRANSIENT_THS,
1005 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1006 .ev_count = MMA8452_TRANSIENT_COUNT,
1007 },
c5ea1b58
MK		 1008 [mma8453] = {
1009 .chip_id = MMA8453_DEVICE_ID,
1010 .channels = mma8453_channels,
1011 .num_channels = ARRAY_SIZE(mma8453_channels),
1012 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1013 .ev_cfg = MMA8452_TRANSIENT_CFG,
1014 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1015 .ev_cfg_chan_shift = 1,
1016 .ev_src = MMA8452_TRANSIENT_SRC,
1017 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1018 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1019 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1020 .ev_ths = MMA8452_TRANSIENT_THS,
1021 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1022 .ev_count = MMA8452_TRANSIENT_COUNT,
1023 },
417e008b
MK		 1024 [mma8652] = {
1025 .chip_id = MMA8652_DEVICE_ID,
1026 .channels = mma8652_channels,
1027 .num_channels = ARRAY_SIZE(mma8652_channels),
1028 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1029 .ev_cfg = MMA8452_FF_MT_CFG,
1030 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1031 .ev_cfg_chan_shift = 3,
1032 .ev_src = MMA8452_FF_MT_SRC,
1033 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1034 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1035 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1036 .ev_ths = MMA8452_FF_MT_THS,
1037 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1038 .ev_count = MMA8452_FF_MT_COUNT,
1039 },
1040 [mma8653] = {
1041 .chip_id = MMA8653_DEVICE_ID,
1042 .channels = mma8653_channels,
1043 .num_channels = ARRAY_SIZE(mma8653_channels),
1044 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1045 .ev_cfg = MMA8452_FF_MT_CFG,
1046 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1047 .ev_cfg_chan_shift = 3,
1048 .ev_src = MMA8452_FF_MT_SRC,
1049 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1050 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1051 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1052 .ev_ths = MMA8452_FF_MT_THS,
1053 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1054 .ev_count = MMA8452_FF_MT_COUNT,
1055 },
c3cdd6e4
MK		 1056};
1057
c7eeea93
PM		 1058static struct attribute *mma8452_attributes[] = {
1059 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1060 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1e79841a 1061 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
c7eeea93
PM		 1062 NULL
1063};
1064
1065static const struct attribute_group mma8452_group = {
1066 .attrs = mma8452_attributes,
1067};
1068
1069static const struct iio_info mma8452_info = {
1070 .attrs = &mma8452_group,
1071 .read_raw = &mma8452_read_raw,
1072 .write_raw = &mma8452_write_raw,
28e34278
MF		 1073 .event_attrs = &mma8452_event_attribute_group,
1074 .read_event_value = &mma8452_read_thresh,
1075 .write_event_value = &mma8452_write_thresh,
1076 .read_event_config = &mma8452_read_event_config,
1077 .write_event_config = &mma8452_write_event_config,
2a17698c 1078 .debugfs_reg_access = &mma8452_reg_access_dbg,
c7eeea93
PM		 1079 .driver_module = THIS_MODULE,
1080};
1081
1082static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1083
ae6d9ce0
MF		 1084static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1085 bool state)
1086{
1087 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1088 struct mma8452_data *data = iio_priv(indio_dev);
1089 int reg;
1090
1091 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1092 if (reg < 0)
1093 return reg;
1094
1095 if (state)
1096 reg |= MMA8452_INT_DRDY;
1097 else
1098 reg &= ~MMA8452_INT_DRDY;
1099
1100 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1101}
1102
1103static int mma8452_validate_device(struct iio_trigger *trig,
1104 struct iio_dev *indio_dev)
1105{
1106 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
1107
1108 if (indio != indio_dev)
1109 return -EINVAL;
1110
1111 return 0;
1112}
1113
1114static const struct iio_trigger_ops mma8452_trigger_ops = {
1115 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1116 .validate_device = mma8452_validate_device,
1117 .owner = THIS_MODULE,
1118};
1119
1120static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1121{
1122 struct mma8452_data *data = iio_priv(indio_dev);
1123 struct iio_trigger *trig;
1124 int ret;
1125
1126 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1127 indio_dev->name,
1128 indio_dev->id);
1129 if (!trig)
1130 return -ENOMEM;
1131
1132 trig->dev.parent = &data->client->dev;
1133 trig->ops = &mma8452_trigger_ops;
1134 iio_trigger_set_drvdata(trig, indio_dev);
1135
1136 ret = iio_trigger_register(trig);
1137 if (ret)
1138 return ret;
1139
1140 indio_dev->trig = trig;
686027fb 1141
ae6d9ce0
MF		 1142 return 0;
1143}
1144
1145static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1146{
1147 if (indio_dev->trig)
1148 iio_trigger_unregister(indio_dev->trig);
1149}
1150
ecabae71
MF		 1151static int mma8452_reset(struct i2c_client *client)
1152{
1153 int i;
1154 int ret;
1155
1156 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1157 MMA8452_CTRL_REG2_RST);
1158 if (ret < 0)
1159 return ret;
1160
1161 for (i = 0; i < 10; i++) {
1162 usleep_range(100, 200);
1163 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1164 if (ret == -EIO)
1165 continue; /* I2C comm reset */
1166 if (ret < 0)
1167 return ret;
1168 if (!(ret & MMA8452_CTRL_REG2_RST))
1169 return 0;
1170 }
1171
1172 return -ETIMEDOUT;
1173}
1174
c3cdd6e4
MK		 1175static const struct of_device_id mma8452_dt_ids[] = {
1176 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
c5ea1b58 1177 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
417e008b
MK		 1178 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1179 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
c3cdd6e4
MK		 1180 { }
1181};
1182MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1183
c7eeea93
PM		 1184static int mma8452_probe(struct i2c_client *client,
1185 const struct i2c_device_id *id)
1186{
1187 struct mma8452_data *data;
1188 struct iio_dev *indio_dev;
1189 int ret;
c3cdd6e4 1190 const struct of_device_id *match;
c7eeea93 1191
c3cdd6e4
MK		 1192 match = of_match_device(mma8452_dt_ids, &client->dev);
1193 if (!match) {
1194 dev_err(&client->dev, "unknown device model\n");
1195 return -ENODEV;
1196 }
1197
c7eeea93
PM		 1198 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1199 if (!indio_dev)
1200 return -ENOMEM;
1201
1202 data = iio_priv(indio_dev);
1203 data->client = client;
1204 mutex_init(&data->lock);
c3cdd6e4
MK		 1205 data->chip_info = match->data;
1206
417e008b
MK		 1207 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1208 if (ret < 0)
1209 return ret;
1210
1211 switch (ret) {
1212 case MMA8452_DEVICE_ID:
1213 case MMA8453_DEVICE_ID:
1214 case MMA8652_DEVICE_ID:
1215 case MMA8653_DEVICE_ID:
1216 if (ret == data->chip_info->chip_id)
1217 break;
1218 default:
1219 return -ENODEV;
1220 }
1221
c3cdd6e4
MK		 1222 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1223 match->compatible, data->chip_info->chip_id);
c7eeea93
PM		 1224
1225 i2c_set_clientdata(client, indio_dev);
1226 indio_dev->info = &mma8452_info;
1227 indio_dev->name = id->name;
1228 indio_dev->dev.parent = &client->dev;
1229 indio_dev->modes = INDIO_DIRECT_MODE;
c3cdd6e4
MK		 1230 indio_dev->channels = data->chip_info->channels;
1231 indio_dev->num_channels = data->chip_info->num_channels;
c7eeea93
PM		 1232 indio_dev->available_scan_masks = mma8452_scan_masks;
1233
ecabae71 1234 ret = mma8452_reset(client);
c7eeea93
PM		 1235 if (ret < 0)
1236 return ret;
1237
1238 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1239 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
686027fb 1240 data->data_cfg);
c7eeea93
PM		 1241 if (ret < 0)
1242 return ret;
1243
28e34278
MF		 1244 /*
1245 * By default set transient threshold to max to avoid events if
1246 * enabling without configuring threshold.
1247 */
1248 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1249 MMA8452_TRANSIENT_THS_MASK);
1250 if (ret < 0)
1251 return ret;
1252
1253 if (client->irq) {
1254 /*
60f562e7
MK		 1255 * Although we enable the interrupt sources once and for
1256 * all here the event detection itself is not enabled until
1257 * userspace asks for it by mma8452_write_event_config()
28e34278 1258 */
60f562e7
MK		 1259 int supported_interrupts = MMA8452_INT_DRDY |
1260 MMA8452_INT_TRANS |
1261 MMA8452_INT_FF_MT;
1262 int enabled_interrupts = MMA8452_INT_TRANS |
1263 MMA8452_INT_FF_MT;
d2a3e093 1264 int irq2;
28e34278 1265
d2a3e093
MK		 1266 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1267
1268 if (irq2 == client->irq) {
1269 dev_dbg(&client->dev, "using interrupt line INT2\n");
1270 } else {
1271 ret = i2c_smbus_write_byte_data(client,
1272 MMA8452_CTRL_REG5,
1273 supported_interrupts);
1274 if (ret < 0)
1275 return ret;
1276
1277 dev_dbg(&client->dev, "using interrupt line INT1\n");
1278 }
28e34278
MF		 1279
1280 ret = i2c_smbus_write_byte_data(client,
1281 MMA8452_CTRL_REG4,
ae6d9ce0
MF		 1282 enabled_interrupts);
1283 if (ret < 0)
1284 return ret;
1285
1286 ret = mma8452_trigger_setup(indio_dev);
28e34278
MF		 1287 if (ret < 0)
1288 return ret;
1289 }
1290
ecabae71 1291 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
686027fb 1292 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
ecabae71
MF		 1293 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1294 data->ctrl_reg1);
1295 if (ret < 0)
ae6d9ce0 1296 goto trigger_cleanup;
ecabae71 1297
c7eeea93 1298 ret = iio_triggered_buffer_setup(indio_dev, NULL,
686027fb 1299 mma8452_trigger_handler, NULL);
c7eeea93 1300 if (ret < 0)
ae6d9ce0 1301 goto trigger_cleanup;
c7eeea93 1302
28e34278
MF		 1303 if (client->irq) {
1304 ret = devm_request_threaded_irq(&client->dev,
1305 client->irq,
1306 NULL, mma8452_interrupt,
1307 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1308 client->name, indio_dev);
1309 if (ret)
1310 goto buffer_cleanup;
1311 }
1312
c7eeea93
PM		 1313 ret = iio_device_register(indio_dev);
1314 if (ret < 0)
1315 goto buffer_cleanup;
28e34278 1316
4b04266a
MK		 1317 ret = mma8452_set_freefall_mode(data, false);
1318 if (ret)
1319 return ret;
1320
c7eeea93
PM		 1321 return 0;
1322
1323buffer_cleanup:
1324 iio_triggered_buffer_cleanup(indio_dev);
ae6d9ce0
MF		 1325
1326trigger_cleanup:
1327 mma8452_trigger_cleanup(indio_dev);
1328
c7eeea93
PM		 1329 return ret;
1330}
1331
1332static int mma8452_remove(struct i2c_client *client)
1333{
1334 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1335
1336 iio_device_unregister(indio_dev);
1337 iio_triggered_buffer_cleanup(indio_dev);
ae6d9ce0 1338 mma8452_trigger_cleanup(indio_dev);
c7eeea93
PM		 1339 mma8452_standby(iio_priv(indio_dev));
1340
1341 return 0;
1342}
1343
1344#ifdef CONFIG_PM_SLEEP
1345static int mma8452_suspend(struct device *dev)
1346{
1347 return mma8452_standby(iio_priv(i2c_get_clientdata(
1348 to_i2c_client(dev))));
1349}
1350
1351static int mma8452_resume(struct device *dev)
1352{
1353 return mma8452_active(iio_priv(i2c_get_clientdata(
1354 to_i2c_client(dev))));
1355}
1356
1357static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
1358#define MMA8452_PM_OPS (&mma8452_pm_ops)
1359#else
1360#define MMA8452_PM_OPS NULL
1361#endif
1362
1363static const struct i2c_device_id mma8452_id[] = {
c3cdd6e4 1364 { "mma8452", mma8452 },
c5ea1b58 1365 { "mma8453", mma8453 },
417e008b
MK		 1366 { "mma8652", mma8652 },
1367 { "mma8653", mma8653 },
c7eeea93
PM		 1368 { }
1369};
1370MODULE_DEVICE_TABLE(i2c, mma8452_id);
1371
1372static struct i2c_driver mma8452_driver = {
1373 .driver = {
1374 .name = "mma8452",
a3fb96a8 1375 .of_match_table = of_match_ptr(mma8452_dt_ids),
c7eeea93
PM		 1376 .pm = MMA8452_PM_OPS,
1377 },
1378 .probe = mma8452_probe,
1379 .remove = mma8452_remove,
1380 .id_table = mma8452_id,
1381};
1382module_i2c_driver(mma8452_driver);
1383
1384MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1385MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1386MODULE_LICENSE("GPL");
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