[mirror_ubuntu-zesty-kernel.git] / drivers / iio / accel / mma8452.c

/*
 * mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer
 *
 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
 *
 * This file is subject to the terms and conditions of version 2 of
 * the GNU General Public License.  See the file COPYING in the main
 * directory of this archive for more details.
 *
 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
 *
 * TODO: interrupt, thresholding, orientation / freefall events, autosleep
 */

#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/delay.h>

#define MMA8452_STATUS 0x00
#define MMA8452_OUT_X 0x01 /* MSB first, 12-bit  */
#define MMA8452_OUT_Y 0x03
#define MMA8452_OUT_Z 0x05
#define MMA8452_WHO_AM_I 0x0d
#define MMA8452_DATA_CFG 0x0e
#define MMA8452_OFF_X 0x2f
#define MMA8452_OFF_Y 0x30
#define MMA8452_OFF_Z 0x31
#define MMA8452_CTRL_REG1 0x2a
#define MMA8452_CTRL_REG2 0x2b
#define MMA8452_CTRL_REG2_RST		BIT(6)

#define MMA8452_MAX_REG 0x31

#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))

#define MMA8452_CTRL_DR_MASK (BIT(5) | BIT(4) | BIT(3))
#define MMA8452_CTRL_DR_SHIFT 3
#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
#define MMA8452_CTRL_ACTIVE BIT(0)

#define MMA8452_DATA_CFG_FS_MASK (BIT(1) | BIT(0))
#define MMA8452_DATA_CFG_FS_2G 0
#define MMA8452_DATA_CFG_FS_4G 1
#define MMA8452_DATA_CFG_FS_8G 2

#define MMA8452_DEVICE_ID 0x2a

struct mma8452_data {
	struct i2c_client *client;
	struct mutex lock;
	u8 ctrl_reg1;
	u8 data_cfg;
};

static int mma8452_drdy(struct mma8452_data *data)
{
	int tries = 150;

	while (tries-- > 0) {
		int ret = i2c_smbus_read_byte_data(data->client,
			MMA8452_STATUS);
		if (ret < 0)
			return ret;
		if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
			return 0;
		msleep(20);
	}

	dev_err(&data->client->dev, "data not ready\n");
	return -EIO;
}

static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
{
	int ret = mma8452_drdy(data);
	if (ret < 0)
		return ret;
	return i2c_smbus_read_i2c_block_data(data->client,
		MMA8452_OUT_X, 3 * sizeof(__be16), (u8 *) buf);
}

static ssize_t mma8452_show_int_plus_micros(char *buf,
	const int (*vals)[2], int n)
{
	size_t len = 0;

	while (n-- > 0)
		len += scnprintf(buf + len, PAGE_SIZE - len,
			"%d.%06d ", vals[n][0], vals[n][1]);

	/* replace trailing space by newline */
	buf[len - 1] = '\n';

	return len;
}

static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
					int val, int val2)
{
	while (n-- > 0)
		if (val == vals[n][0] && val2 == vals[n][1])
			return n;

	return -EINVAL;
}

static const int mma8452_samp_freq[8][2] = {
	{800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
	{6, 250000}, {1, 560000}
};

/*
 * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
 * The userspace interface uses m/s^2 and we declare micro units
 * So scale factor is given by:
 * 	g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
 */
static const int mma8452_scales[3][2] = {
	{0, 9577}, {0, 19154}, {0, 38307}
};

static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
		ARRAY_SIZE(mma8452_samp_freq));
}

static ssize_t mma8452_show_scale_avail(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	return mma8452_show_int_plus_micros(buf, mma8452_scales,
		ARRAY_SIZE(mma8452_scales));
}

static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
	mma8452_show_scale_avail, NULL, 0);

static int mma8452_get_samp_freq_index(struct mma8452_data *data,
	int val, int val2)
{
	return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
		ARRAY_SIZE(mma8452_samp_freq), val, val2);
}

static int mma8452_get_scale_index(struct mma8452_data *data,
	int val, int val2)
{
	return mma8452_get_int_plus_micros_index(mma8452_scales,
		ARRAY_SIZE(mma8452_scales), val, val2);
}

static int mma8452_read_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan,
			    int *val, int *val2, long mask)
{
	struct mma8452_data *data = iio_priv(indio_dev);
	__be16 buffer[3];
	int i, ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		if (iio_buffer_enabled(indio_dev))
			return -EBUSY;

		mutex_lock(&data->lock);
		ret = mma8452_read(data, buffer);
		mutex_unlock(&data->lock);
		if (ret < 0)
			return ret;
		*val = sign_extend32(
			be16_to_cpu(buffer[chan->scan_index]) >> 4, 11);
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
		*val = mma8452_scales[i][0];
		*val2 = mma8452_scales[i][1];
		return IIO_VAL_INT_PLUS_MICRO;
	case IIO_CHAN_INFO_SAMP_FREQ:
		i = (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
			MMA8452_CTRL_DR_SHIFT;
		*val = mma8452_samp_freq[i][0];
		*val2 = mma8452_samp_freq[i][1];
		return IIO_VAL_INT_PLUS_MICRO;
	case IIO_CHAN_INFO_CALIBBIAS:
		ret = i2c_smbus_read_byte_data(data->client, MMA8452_OFF_X +
			chan->scan_index);
		if (ret < 0)
			return ret;
		*val = sign_extend32(ret, 7);
		return IIO_VAL_INT;
	}
	return -EINVAL;
}

static int mma8452_standby(struct mma8452_data *data)
{
	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
		data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
}

static int mma8452_active(struct mma8452_data *data)
{
	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
		data->ctrl_reg1);
}

static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
{
	int ret;

	mutex_lock(&data->lock);

	/* config can only be changed when in standby */
	ret = mma8452_standby(data);
	if (ret < 0)
		goto fail;

	ret = i2c_smbus_write_byte_data(data->client, reg, val);
	if (ret < 0)
		goto fail;

	ret = mma8452_active(data);
	if (ret < 0)
		goto fail;

	ret = 0;
fail:
	mutex_unlock(&data->lock);
	return ret;
}

static int mma8452_write_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan,
			     int val, int val2, long mask)
{
	struct mma8452_data *data = iio_priv(indio_dev);
	int i;

	if (iio_buffer_enabled(indio_dev))
		return -EBUSY;

	switch (mask) {
	case IIO_CHAN_INFO_SAMP_FREQ:
		i = mma8452_get_samp_freq_index(data, val, val2);
		if (i < 0)
			return -EINVAL;

		data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
		data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
		return mma8452_change_config(data, MMA8452_CTRL_REG1,
			data->ctrl_reg1);
	case IIO_CHAN_INFO_SCALE:
		i = mma8452_get_scale_index(data, val, val2);
		if (i < 0)
			return -EINVAL;
		data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
		data->data_cfg |= i;
		return mma8452_change_config(data, MMA8452_DATA_CFG,
			data->data_cfg);
	case IIO_CHAN_INFO_CALIBBIAS:
		if (val < -128 || val > 127)
			return -EINVAL;
		return mma8452_change_config(data, MMA8452_OFF_X +
			chan->scan_index, val);
	default:
		return -EINVAL;
	}
}

static irqreturn_t mma8452_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct mma8452_data *data = iio_priv(indio_dev);
	u8 buffer[16]; /* 3 16-bit channels + padding + ts */
	int ret;

	ret = mma8452_read(data, (__be16 *) buffer);
	if (ret < 0)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, buffer,
		iio_get_time_ns());

done:
	iio_trigger_notify_done(indio_dev->trig);
	return IRQ_HANDLED;
}

static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
				  unsigned reg, unsigned writeval,
				  unsigned *readval)
{
	int ret;
	struct mma8452_data *data = iio_priv(indio_dev);

	if (reg > MMA8452_MAX_REG)
		return -EINVAL;

	if (!readval)
		return mma8452_change_config(data, reg, writeval);

	ret = i2c_smbus_read_byte_data(data->client, reg);
	if (ret < 0)
		return ret;

	*readval = ret;

	return 0;
}

#define MMA8452_CHANNEL(axis, idx) { \
	.type = IIO_ACCEL, \
	.modified = 1, \
	.channel2 = IIO_MOD_##axis, \
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
		BIT(IIO_CHAN_INFO_CALIBBIAS), \
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
		BIT(IIO_CHAN_INFO_SCALE), \
	.scan_index = idx, \
	.scan_type = { \
		.sign = 's', \
		.realbits = 12, \
		.storagebits = 16, \
		.shift = 4, \
		.endianness = IIO_BE, \
	}, \
}

static const struct iio_chan_spec mma8452_channels[] = {
	MMA8452_CHANNEL(X, 0),
	MMA8452_CHANNEL(Y, 1),
	MMA8452_CHANNEL(Z, 2),
	IIO_CHAN_SOFT_TIMESTAMP(3),
};

static struct attribute *mma8452_attributes[] = {
	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
	&iio_dev_attr_in_accel_scale_available.dev_attr.attr,
	NULL
};

static const struct attribute_group mma8452_group = {
	.attrs = mma8452_attributes,
};

static const struct iio_info mma8452_info = {
	.attrs = &mma8452_group,
	.read_raw = &mma8452_read_raw,
	.write_raw = &mma8452_write_raw,
	.debugfs_reg_access = &mma8452_reg_access_dbg,
	.driver_module = THIS_MODULE,
};

static const unsigned long mma8452_scan_masks[] = {0x7, 0};

static int mma8452_reset(struct i2c_client *client)
{
	int i;
	int ret;

	ret = i2c_smbus_write_byte_data(client,	MMA8452_CTRL_REG2,
					MMA8452_CTRL_REG2_RST);
	if (ret < 0)
		return ret;

	for (i = 0; i < 10; i++) {
		usleep_range(100, 200);
		ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
		if (ret == -EIO)
			continue; /* I2C comm reset */
		if (ret < 0)
			return ret;
		if (!(ret & MMA8452_CTRL_REG2_RST))
			return 0;
	}

	return -ETIMEDOUT;
}

static int mma8452_probe(struct i2c_client *client,
			 const struct i2c_device_id *id)
{
	struct mma8452_data *data;
	struct iio_dev *indio_dev;
	int ret;

	ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
	if (ret < 0)
		return ret;
	if (ret != MMA8452_DEVICE_ID)
		return -ENODEV;

	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
	if (!indio_dev)
		return -ENOMEM;

	data = iio_priv(indio_dev);
	data->client = client;
	mutex_init(&data->lock);

	i2c_set_clientdata(client, indio_dev);
	indio_dev->info = &mma8452_info;
	indio_dev->name = id->name;
	indio_dev->dev.parent = &client->dev;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = mma8452_channels;
	indio_dev->num_channels = ARRAY_SIZE(mma8452_channels);
	indio_dev->available_scan_masks = mma8452_scan_masks;

	ret = mma8452_reset(client);
	if (ret < 0)
		return ret;

	data->data_cfg = MMA8452_DATA_CFG_FS_2G;
	ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
		data->data_cfg);
	if (ret < 0)
		return ret;

	data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
		(MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
	ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
					data->ctrl_reg1);
	if (ret < 0)
		return ret;

	ret = iio_triggered_buffer_setup(indio_dev, NULL,
		mma8452_trigger_handler, NULL);
	if (ret < 0)
		return ret;

	ret = iio_device_register(indio_dev);
	if (ret < 0)
		goto buffer_cleanup;
	return 0;

buffer_cleanup:
	iio_triggered_buffer_cleanup(indio_dev);
	return ret;
}

static int mma8452_remove(struct i2c_client *client)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(client);

	iio_device_unregister(indio_dev);
	iio_triggered_buffer_cleanup(indio_dev);
	mma8452_standby(iio_priv(indio_dev));

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mma8452_suspend(struct device *dev)
{
	return mma8452_standby(iio_priv(i2c_get_clientdata(
		to_i2c_client(dev))));
}

static int mma8452_resume(struct device *dev)
{
	return mma8452_active(iio_priv(i2c_get_clientdata(
		to_i2c_client(dev))));
}

static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
#define MMA8452_PM_OPS (&mma8452_pm_ops)
#else
#define MMA8452_PM_OPS NULL
#endif

static const struct i2c_device_id mma8452_id[] = {
	{ "mma8452", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, mma8452_id);

static const struct of_device_id mma8452_dt_ids[] = {
	{ .compatible = "fsl,mma8452" },
	{ }
};

static struct i2c_driver mma8452_driver = {
	.driver = {
		.name	= "mma8452",
		.of_match_table = of_match_ptr(mma8452_dt_ids),
		.pm	= MMA8452_PM_OPS,
	},
	.probe = mma8452_probe,
	.remove = mma8452_remove,
	.id_table = mma8452_id,
};
module_i2c_driver(mma8452_driver);

MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
c7eeea93 PM	1	/*
	2	* mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer
	3	*
	4	* Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
	5	*
	6	* This file is subject to the terms and conditions of version 2 of
	7	* the GNU General Public License. See the file COPYING in the main
	8	* directory of this archive for more details.
	9	*
	10	* 7-bit I2C slave address 0x1c/0x1d (pin selectable)
	11	*
	12	* TODO: interrupt, thresholding, orientation / freefall events, autosleep
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/i2c.h>
	17	#include <linux/iio/iio.h>
	18	#include <linux/iio/sysfs.h>
	19	#include <linux/iio/trigger_consumer.h>
	20	#include <linux/iio/buffer.h>
	21	#include <linux/iio/triggered_buffer.h>
	22	#include <linux/delay.h>
	23
	24	#define MMA8452_STATUS 0x00
	25	#define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
	26	#define MMA8452_OUT_Y 0x03
	27	#define MMA8452_OUT_Z 0x05
	28	#define MMA8452_WHO_AM_I 0x0d
	29	#define MMA8452_DATA_CFG 0x0e
	30	#define MMA8452_OFF_X 0x2f
	31	#define MMA8452_OFF_Y 0x30
	32	#define MMA8452_OFF_Z 0x31
	33	#define MMA8452_CTRL_REG1 0x2a
	34	#define MMA8452_CTRL_REG2 0x2b
ecabae71	35	#define MMA8452_CTRL_REG2_RST BIT(6)
c7eeea93	36
2a17698c MF	37	#define MMA8452_MAX_REG 0x31
2a17698c MF	38
c7eeea93 PM	39	#define MMA8452_STATUS_DRDY (BIT(2) \| BIT(1) \| BIT(0))
	40
	41	#define MMA8452_CTRL_DR_MASK (BIT(5) \| BIT(4) \| BIT(3))
	42	#define MMA8452_CTRL_DR_SHIFT 3
	43	#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
	44	#define MMA8452_CTRL_ACTIVE BIT(0)
	45
	46	#define MMA8452_DATA_CFG_FS_MASK (BIT(1) \| BIT(0))
	47	#define MMA8452_DATA_CFG_FS_2G 0
	48	#define MMA8452_DATA_CFG_FS_4G 1
	49	#define MMA8452_DATA_CFG_FS_8G 2
	50
	51	#define MMA8452_DEVICE_ID 0x2a
	52
	53	struct mma8452_data {
	54	struct i2c_client *client;
	55	struct mutex lock;
	56	u8 ctrl_reg1;
	57	u8 data_cfg;
	58	};
	59
	60	static int mma8452_drdy(struct mma8452_data *data)
	61	{
	62	int tries = 150;
	63
	64	while (tries-- > 0) {
	65	int ret = i2c_smbus_read_byte_data(data->client,
	66	MMA8452_STATUS);
	67	if (ret < 0)
	68	return ret;
	69	if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
	70	return 0;
	71	msleep(20);
	72	}
	73
	74	dev_err(&data->client->dev, "data not ready\n");
	75	return -EIO;
	76	}
	77
	78	static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
	79	{
	80	int ret = mma8452_drdy(data);
	81	if (ret < 0)
	82	return ret;
	83	return i2c_smbus_read_i2c_block_data(data->client,
	84	MMA8452_OUT_X, 3 * sizeof(__be16), (u8 *) buf);
	85	}
	86
	87	static ssize_t mma8452_show_int_plus_micros(char *buf,
	88	const int (*vals)[2], int n)
	89	{
	90	size_t len = 0;
	91
	92	while (n-- > 0)
	93	len += scnprintf(buf + len, PAGE_SIZE - len,
	94	"%d.%06d ", vals[n][0], vals[n][1]);
	95
	96	/* replace trailing space by newline */
	97	buf[len - 1] = '\n';
	98
	99	return len;
	100	}
	101
	102	static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
103	int val, int val2)
104	{
105	while (n-- > 0)
106	if (val == vals[n][0] && val2 == vals[n][1])
107	return n;
108
109	return -EINVAL;
110	}
111
112	static const int mma8452_samp_freq[8][2] = {
113	{800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
114	{6, 250000}, {1, 560000}
115	};
116
c876109e	117	/*
71702e6e MF	118	* Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
	119	* The userspace interface uses m/s^2 and we declare micro units
	120	* So scale factor is given by:
	121	* g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
	122	*/
c7eeea93	123	static const int mma8452_scales[3][2] = {
71702e6e	124	{0, 9577}, {0, 19154}, {0, 38307}
c7eeea93 PM	125	};
	126
	127	static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
	128	struct device_attribute attr, char buf)
	129	{
	130	return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
	131	ARRAY_SIZE(mma8452_samp_freq));
	132	}
	133
	134	static ssize_t mma8452_show_scale_avail(struct device *dev,
	135	struct device_attribute attr, char buf)
	136	{
	137	return mma8452_show_int_plus_micros(buf, mma8452_scales,
	138	ARRAY_SIZE(mma8452_scales));
	139	}
	140
	141	static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
	142	static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
	143	mma8452_show_scale_avail, NULL, 0);
	144
	145	static int mma8452_get_samp_freq_index(struct mma8452_data *data,
	146	int val, int val2)
	147	{
	148	return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
	149	ARRAY_SIZE(mma8452_samp_freq), val, val2);
	150	}
	151
	152	static int mma8452_get_scale_index(struct mma8452_data *data,
	153	int val, int val2)
	154	{
	155	return mma8452_get_int_plus_micros_index(mma8452_scales,
	156	ARRAY_SIZE(mma8452_scales), val, val2);
	157	}
	158
	159	static int mma8452_read_raw(struct iio_dev *indio_dev,
	160	struct iio_chan_spec const *chan,
	161	int val, int val2, long mask)
	162	{
	163	struct mma8452_data *data = iio_priv(indio_dev);
	164	__be16 buffer[3];
	165	int i, ret;
	166
	167	switch (mask) {
	168	case IIO_CHAN_INFO_RAW:
	169	if (iio_buffer_enabled(indio_dev))
	170	return -EBUSY;
	171
	172	mutex_lock(&data->lock);
	173	ret = mma8452_read(data, buffer);
	174	mutex_unlock(&data->lock);
	175	if (ret < 0)
	176	return ret;
	177	*val = sign_extend32(
	178	be16_to_cpu(buffer[chan->scan_index]) >> 4, 11);
	179	return IIO_VAL_INT;
	180	case IIO_CHAN_INFO_SCALE:
	181	i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
	182	*val = mma8452_scales[i][0];
	183	*val2 = mma8452_scales[i][1];
	184	return IIO_VAL_INT_PLUS_MICRO;
	185	case IIO_CHAN_INFO_SAMP_FREQ:
	186	i = (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
	187	MMA8452_CTRL_DR_SHIFT;
	188	*val = mma8452_samp_freq[i][0];
189	*val2 = mma8452_samp_freq[i][1];
190	return IIO_VAL_INT_PLUS_MICRO;
191	case IIO_CHAN_INFO_CALIBBIAS:
192	ret = i2c_smbus_read_byte_data(data->client, MMA8452_OFF_X +
193	chan->scan_index);
194	if (ret < 0)
195	return ret;
196	*val = sign_extend32(ret, 7);
197	return IIO_VAL_INT;
198	}
199	return -EINVAL;
200	}
201
202	static int mma8452_standby(struct mma8452_data *data)
203	{
204	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
205	data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
206	}
207
208	static int mma8452_active(struct mma8452_data *data)
209	{
210	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
211	data->ctrl_reg1);
212	}
213
214	static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
215	{
216	int ret;
217
218	mutex_lock(&data->lock);
219
220	/* config can only be changed when in standby */
221	ret = mma8452_standby(data);
222	if (ret < 0)
223	goto fail;
224
225	ret = i2c_smbus_write_byte_data(data->client, reg, val);
226	if (ret < 0)
227	goto fail;
228
229	ret = mma8452_active(data);
230	if (ret < 0)
231	goto fail;
232
233	ret = 0;
234	fail:
235	mutex_unlock(&data->lock);
236	return ret;
237	}
238
239	static int mma8452_write_raw(struct iio_dev *indio_dev,
240	struct iio_chan_spec const *chan,
241	int val, int val2, long mask)
242	{
243	struct mma8452_data *data = iio_priv(indio_dev);
244	int i;
245
246	if (iio_buffer_enabled(indio_dev))
247	return -EBUSY;
248
249	switch (mask) {
250	case IIO_CHAN_INFO_SAMP_FREQ:
251	i = mma8452_get_samp_freq_index(data, val, val2);
252	if (i < 0)
253	return -EINVAL;
254
255	data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
256	data->ctrl_reg1 \|= i << MMA8452_CTRL_DR_SHIFT;
257	return mma8452_change_config(data, MMA8452_CTRL_REG1,
258	data->ctrl_reg1);
259	case IIO_CHAN_INFO_SCALE:
260	i = mma8452_get_scale_index(data, val, val2);
261	if (i < 0)
262	return -EINVAL;
263	data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
264	data->data_cfg \|= i;
265	return mma8452_change_config(data, MMA8452_DATA_CFG,
266	data->data_cfg);
267	case IIO_CHAN_INFO_CALIBBIAS:
268	if (val < -128 \|\| val > 127)
269	return -EINVAL;
270	return mma8452_change_config(data, MMA8452_OFF_X +
271	chan->scan_index, val);
272	default:
273	return -EINVAL;
274	}
275	}
276
277	static irqreturn_t mma8452_trigger_handler(int irq, void *p)
278	{
279	struct iio_poll_func *pf = p;
280	struct iio_dev *indio_dev = pf->indio_dev;
281	struct mma8452_data *data = iio_priv(indio_dev);
282	u8 buffer[16]; /* 3 16-bit channels + padding + ts */
283	int ret;
284
285	ret = mma8452_read(data, (__be16 *) buffer);
286	if (ret < 0)
287	goto done;
288
289	iio_push_to_buffers_with_timestamp(indio_dev, buffer,
290	iio_get_time_ns());
291
292	done:
293	iio_trigger_notify_done(indio_dev->trig);
294	return IRQ_HANDLED;
295	}
296
2a17698c MF	297	static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
	298	unsigned reg, unsigned writeval,
	299	unsigned *readval)
	300	{
	301	int ret;
	302	struct mma8452_data *data = iio_priv(indio_dev);
	303
	304	if (reg > MMA8452_MAX_REG)
	305	return -EINVAL;
	306
	307	if (!readval)
	308	return mma8452_change_config(data, reg, writeval);
	309
	310	ret = i2c_smbus_read_byte_data(data->client, reg);
	311	if (ret < 0)
	312	return ret;
	313
	314	*readval = ret;
	315
	316	return 0;
	317	}
	318
c7eeea93 PM	319	#define MMA8452_CHANNEL(axis, idx) { \
	320	.type = IIO_ACCEL, \
	321	.modified = 1, \
	322	.channel2 = IIO_MOD_##axis, \
	323	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	324	BIT(IIO_CHAN_INFO_CALIBBIAS), \
	325	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) \| \
	326	BIT(IIO_CHAN_INFO_SCALE), \
	327	.scan_index = idx, \
	328	.scan_type = { \
	329	.sign = 's', \
	330	.realbits = 12, \
	331	.storagebits = 16, \
	332	.shift = 4, \
	333	.endianness = IIO_BE, \
	334	}, \
	335	}
	336
	337	static const struct iio_chan_spec mma8452_channels[] = {
	338	MMA8452_CHANNEL(X, 0),
	339	MMA8452_CHANNEL(Y, 1),
	340	MMA8452_CHANNEL(Z, 2),
	341	IIO_CHAN_SOFT_TIMESTAMP(3),
	342	};
	343
	344	static struct attribute *mma8452_attributes[] = {
	345	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
	346	&iio_dev_attr_in_accel_scale_available.dev_attr.attr,
	347	NULL
	348	};
	349
	350	static const struct attribute_group mma8452_group = {
	351	.attrs = mma8452_attributes,
	352	};
	353
	354	static const struct iio_info mma8452_info = {
	355	.attrs = &mma8452_group,
	356	.read_raw = &mma8452_read_raw,
	357	.write_raw = &mma8452_write_raw,
2a17698c	358	.debugfs_reg_access = &mma8452_reg_access_dbg,
c7eeea93 PM	359	.driver_module = THIS_MODULE,
	360	};
	361
	362	static const unsigned long mma8452_scan_masks[] = {0x7, 0};
	363
ecabae71 MF	364	static int mma8452_reset(struct i2c_client *client)
	365	{
	366	int i;
	367	int ret;
	368
	369	ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
	370	MMA8452_CTRL_REG2_RST);
	371	if (ret < 0)
	372	return ret;
	373
	374	for (i = 0; i < 10; i++) {
	375	usleep_range(100, 200);
	376	ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
	377	if (ret == -EIO)
	378	continue; /* I2C comm reset */
	379	if (ret < 0)
	380	return ret;
	381	if (!(ret & MMA8452_CTRL_REG2_RST))
	382	return 0;
	383	}
	384
	385	return -ETIMEDOUT;
	386	}
	387
c7eeea93 PM	388	static int mma8452_probe(struct i2c_client *client,
	389	const struct i2c_device_id *id)
	390	{
	391	struct mma8452_data *data;
	392	struct iio_dev *indio_dev;
	393	int ret;
	394
	395	ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
	396	if (ret < 0)
	397	return ret;
	398	if (ret != MMA8452_DEVICE_ID)
	399	return -ENODEV;
	400
	401	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
	402	if (!indio_dev)
	403	return -ENOMEM;
	404
	405	data = iio_priv(indio_dev);
	406	data->client = client;
	407	mutex_init(&data->lock);
	408
	409	i2c_set_clientdata(client, indio_dev);
	410	indio_dev->info = &mma8452_info;
	411	indio_dev->name = id->name;
	412	indio_dev->dev.parent = &client->dev;
	413	indio_dev->modes = INDIO_DIRECT_MODE;
	414	indio_dev->channels = mma8452_channels;
	415	indio_dev->num_channels = ARRAY_SIZE(mma8452_channels);
	416	indio_dev->available_scan_masks = mma8452_scan_masks;
	417
ecabae71	418	ret = mma8452_reset(client);
c7eeea93 PM	419	if (ret < 0)
	420	return ret;
	421
	422	data->data_cfg = MMA8452_DATA_CFG_FS_2G;
	423	ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
	424	data->data_cfg);
	425	if (ret < 0)
	426	return ret;
	427
ecabae71 MF	428	data->ctrl_reg1 = MMA8452_CTRL_ACTIVE \|
	429	(MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
	430	ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
	431	data->ctrl_reg1);
	432	if (ret < 0)
	433	return ret;
	434
c7eeea93 PM	435	ret = iio_triggered_buffer_setup(indio_dev, NULL,
	436	mma8452_trigger_handler, NULL);
	437	if (ret < 0)
	438	return ret;
	439
	440	ret = iio_device_register(indio_dev);
	441	if (ret < 0)
	442	goto buffer_cleanup;
	443	return 0;
	444
	445	buffer_cleanup:
	446	iio_triggered_buffer_cleanup(indio_dev);
	447	return ret;
	448	}
	449
	450	static int mma8452_remove(struct i2c_client *client)
	451	{
	452	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	453
	454	iio_device_unregister(indio_dev);
	455	iio_triggered_buffer_cleanup(indio_dev);
	456	mma8452_standby(iio_priv(indio_dev));
	457
	458	return 0;
	459	}
	460
	461	#ifdef CONFIG_PM_SLEEP
	462	static int mma8452_suspend(struct device *dev)
	463	{
	464	return mma8452_standby(iio_priv(i2c_get_clientdata(
	465	to_i2c_client(dev))));
	466	}
	467
	468	static int mma8452_resume(struct device *dev)
	469	{
	470	return mma8452_active(iio_priv(i2c_get_clientdata(
	471	to_i2c_client(dev))));
	472	}
	473
	474	static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
	475	#define MMA8452_PM_OPS (&mma8452_pm_ops)
	476	#else
	477	#define MMA8452_PM_OPS NULL
	478	#endif
	479
	480	static const struct i2c_device_id mma8452_id[] = {
	481	{ "mma8452", 0 },
	482	{ }
	483	};
	484	MODULE_DEVICE_TABLE(i2c, mma8452_id);
	485
a3fb96a8 MF	486	static const struct of_device_id mma8452_dt_ids[] = {
	487	{ .compatible = "fsl,mma8452" },
	488	{ }
	489	};
	490
c7eeea93 PM	491	static struct i2c_driver mma8452_driver = {
	492	.driver = {
	493	.name = "mma8452",
a3fb96a8	494	.of_match_table = of_match_ptr(mma8452_dt_ids),
c7eeea93 PM	495	.pm = MMA8452_PM_OPS,
	496	},
	497	.probe = mma8452_probe,
	498	.remove = mma8452_remove,
	499	.id_table = mma8452_id,
	500	};
	501	module_i2c_driver(mma8452_driver);
	502
	503	MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
	504	MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
	505	MODULE_LICENSE("GPL");