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[mirror_ubuntu-zesty-kernel.git] / drivers / iio / accel / mma8452.c
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c7eeea93 1/*
c5ea1b58
MK		 2 * mma8452.c - Support for following Freescale 3-axis accelerometers:
3 *
4 * MMA8452Q (12 bit)
5 * MMA8453Q (10 bit)
417e008b
MK		 6 * MMA8652FC (12 bit)
7 * MMA8653FC (10 bit)
c7eeea93 8 *
d6223c37 9 * Copyright 2015 Martin Kepplinger <martin.kepplinger@theobroma-systems.com>
c7eeea93
PM		 10 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
11 *
12 * This file is subject to the terms and conditions of version 2 of
13 * the GNU General Public License. See the file COPYING in the main
14 * directory of this archive for more details.
15 *
16 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
17 *
28e34278 18 * TODO: orientation / freefall events, autosleep
c7eeea93
PM		 19 */
20
21#include <linux/module.h>
22#include <linux/i2c.h>
23#include <linux/iio/iio.h>
24#include <linux/iio/sysfs.h>
c7eeea93 25#include <linux/iio/buffer.h>
ae6d9ce0
MF		 26#include <linux/iio/trigger.h>
27#include <linux/iio/trigger_consumer.h>
c7eeea93 28#include <linux/iio/triggered_buffer.h>
28e34278 29#include <linux/iio/events.h>
c7eeea93 30#include <linux/delay.h>
c3cdd6e4 31#include <linux/of_device.h>
c7eeea93 32
69abff81
HK		 33#define MMA8452_STATUS 0x00
34#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
c5ea1b58 35#define MMA8452_OUT_X 0x01 /* MSB first */
69abff81
HK		 36#define MMA8452_OUT_Y 0x03
37#define MMA8452_OUT_Z 0x05
38#define MMA8452_INT_SRC 0x0c
39#define MMA8452_WHO_AM_I 0x0d
40#define MMA8452_DATA_CFG 0x0e
41#define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
42#define MMA8452_DATA_CFG_FS_2G 0
43#define MMA8452_DATA_CFG_FS_4G 1
44#define MMA8452_DATA_CFG_FS_8G 2
45#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
46#define MMA8452_HP_FILTER_CUTOFF 0x0f
47#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
60f562e7
MK		 48#define MMA8452_FF_MT_CFG 0x15
49#define MMA8452_FF_MT_CFG_OAE BIT(6)
50#define MMA8452_FF_MT_CFG_ELE BIT(7)
51#define MMA8452_FF_MT_SRC 0x16
52#define MMA8452_FF_MT_SRC_XHE BIT(1)
53#define MMA8452_FF_MT_SRC_YHE BIT(3)
54#define MMA8452_FF_MT_SRC_ZHE BIT(5)
55#define MMA8452_FF_MT_THS 0x17
56#define MMA8452_FF_MT_THS_MASK 0x7f
57#define MMA8452_FF_MT_COUNT 0x18
69abff81
HK		 58#define MMA8452_TRANSIENT_CFG 0x1d
59#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
60#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
61#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
62#define MMA8452_TRANSIENT_SRC 0x1e
63#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
64#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
65#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
66#define MMA8452_TRANSIENT_THS 0x1f
67#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
68#define MMA8452_TRANSIENT_COUNT 0x20
69#define MMA8452_CTRL_REG1 0x2a
70#define MMA8452_CTRL_ACTIVE BIT(0)
71#define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
72#define MMA8452_CTRL_DR_SHIFT 3
73#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
74#define MMA8452_CTRL_REG2 0x2b
75#define MMA8452_CTRL_REG2_RST BIT(6)
76#define MMA8452_CTRL_REG4 0x2d
77#define MMA8452_CTRL_REG5 0x2e
78#define MMA8452_OFF_X 0x2f
79#define MMA8452_OFF_Y 0x30
80#define MMA8452_OFF_Z 0x31
c7eeea93 81
69abff81 82#define MMA8452_MAX_REG 0x31
2a17698c 83
69abff81 84#define MMA8452_INT_DRDY BIT(0)
60f562e7 85#define MMA8452_INT_FF_MT BIT(2)
69abff81 86#define MMA8452_INT_TRANS BIT(5)
c7eeea93 87
69abff81 88#define MMA8452_DEVICE_ID 0x2a
c5ea1b58 89#define MMA8453_DEVICE_ID 0x3a
417e008b
MK		 90#define MMA8652_DEVICE_ID 0x4a
91#define MMA8653_DEVICE_ID 0x5a
c7eeea93
PM		 92
93struct mma8452_data {
94 struct i2c_client *client;
95 struct mutex lock;
96 u8 ctrl_reg1;
97 u8 data_cfg;
c3cdd6e4
MK		 98 const struct mma_chip_info *chip_info;
99};
100
101/**
102 * struct mma_chip_info - chip specific data for Freescale's accelerometers
103 * @chip_id: WHO_AM_I register's value
104 * @channels: struct iio_chan_spec matching the device's
105 * capabilities
106 * @num_channels: number of channels
107 * @mma_scales: scale factors for converting register values
108 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
109 * per mode: m/s^2 and micro m/s^2
110 * @ev_cfg: event config register address
111 * @ev_cfg_ele: latch bit in event config register
112 * @ev_cfg_chan_shift: number of the bit to enable events in X
113 * direction; in event config register
114 * @ev_src: event source register address
115 * @ev_src_xe: bit in event source register that indicates
116 * an event in X direction
117 * @ev_src_ye: bit in event source register that indicates
118 * an event in Y direction
119 * @ev_src_ze: bit in event source register that indicates
120 * an event in Z direction
121 * @ev_ths: event threshold register address
122 * @ev_ths_mask: mask for the threshold value
123 * @ev_count: event count (period) register address
124 *
125 * Since not all chips supported by the driver support comparing high pass
126 * filtered data for events (interrupts), different interrupt sources are
127 * used for different chips and the relevant registers are included here.
128 */
129struct mma_chip_info {
130 u8 chip_id;
131 const struct iio_chan_spec *channels;
132 int num_channels;
133 const int mma_scales[3][2];
134 u8 ev_cfg;
135 u8 ev_cfg_ele;
136 u8 ev_cfg_chan_shift;
137 u8 ev_src;
138 u8 ev_src_xe;
139 u8 ev_src_ye;
140 u8 ev_src_ze;
141 u8 ev_ths;
142 u8 ev_ths_mask;
143 u8 ev_count;
c7eeea93
PM		 144};
145
146static int mma8452_drdy(struct mma8452_data *data)
147{
148 int tries = 150;
149
150 while (tries-- > 0) {
151 int ret = i2c_smbus_read_byte_data(data->client,
152 MMA8452_STATUS);
153 if (ret < 0)
154 return ret;
155 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
156 return 0;
686027fb 157
c7eeea93
PM		 158 msleep(20);
159 }
160
161 dev_err(&data->client->dev, "data not ready\n");
686027fb 162
c7eeea93
PM		 163 return -EIO;
164}
165
166static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
167{
168 int ret = mma8452_drdy(data);
686027fb 169
c7eeea93
PM		 170 if (ret < 0)
171 return ret;
686027fb
HK		 172
173 return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
174 3 * sizeof(__be16), (u8 *)buf);
c7eeea93
PM		 175}
176
686027fb
HK		 177static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
178 int n)
c7eeea93
PM		 179{
180 size_t len = 0;
181
182 while (n-- > 0)
686027fb
HK		 183 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
184 vals[n][0], vals[n][1]);
c7eeea93
PM		 185
186 /* replace trailing space by newline */
187 buf[len - 1] = '\n';
188
189 return len;
190}
191
192static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
686027fb 193 int val, int val2)
c7eeea93
PM		 194{
195 while (n-- > 0)
196 if (val == vals[n][0] && val2 == vals[n][1])
197 return n;
198
199 return -EINVAL;
200}
201
5dbbd19f
MF		 202static int mma8452_get_odr_index(struct mma8452_data *data)
203{
204 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
205 MMA8452_CTRL_DR_SHIFT;
206}
207
c7eeea93
PM		 208static const int mma8452_samp_freq[8][2] = {
209 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
210 {6, 250000}, {1, 560000}
211};
212
5dbbd19f
MF		 213/* Datasheet table 35 (step time vs sample frequency) */
214static const int mma8452_transient_time_step_us[8] = {
215 1250,
216 2500,
217 5000,
218 10000,
219 20000,
220 20000,
221 20000,
222 20000
223};
224
1e79841a
MF		 225/* Datasheet table 18 (normal mode) */
226static const int mma8452_hp_filter_cutoff[8][4][2] = {
227 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
228 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
229 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
230 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
231 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
232 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
233 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
234 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
235};
236
c7eeea93 237static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
686027fb
HK		 238 struct device_attribute *attr,
239 char *buf)
c7eeea93
PM		 240{
241 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
686027fb 242 ARRAY_SIZE(mma8452_samp_freq));
c7eeea93
PM		 243}
244
245static ssize_t mma8452_show_scale_avail(struct device *dev,
686027fb
HK		 246 struct device_attribute *attr,
247 char *buf)
c7eeea93 248{
c3cdd6e4
MK		 249 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
250 to_i2c_client(dev)));
251
252 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
253 ARRAY_SIZE(data->chip_info->mma_scales));
c7eeea93
PM		 254}
255
1e79841a
MF		 256static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
257 struct device_attribute *attr,
258 char *buf)
259{
260 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
261 struct mma8452_data *data = iio_priv(indio_dev);
262 int i = mma8452_get_odr_index(data);
263
264 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
265 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
266}
267
c7eeea93
PM		 268static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
269static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
686027fb 270 mma8452_show_scale_avail, NULL, 0);
1e79841a 271static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
686027fb 272 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
c7eeea93
PM		 273
274static int mma8452_get_samp_freq_index(struct mma8452_data *data,
686027fb 275 int val, int val2)
c7eeea93
PM		 276{
277 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
686027fb
HK		 278 ARRAY_SIZE(mma8452_samp_freq),
279 val, val2);
c7eeea93
PM		 280}
281
686027fb 282static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
c7eeea93 283{
c3cdd6e4
MK		 284 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
285 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
c7eeea93
PM		 286}
287
1e79841a
MF		 288static int mma8452_get_hp_filter_index(struct mma8452_data *data,
289 int val, int val2)
290{
291 int i = mma8452_get_odr_index(data);
292
293 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
001fceb9 294 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
1e79841a
MF		 295}
296
297static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
298{
299 int i, ret;
300
301 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
302 if (ret < 0)
303 return ret;
304
305 i = mma8452_get_odr_index(data);
306 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
307 *hz = mma8452_hp_filter_cutoff[i][ret][0];
308 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
309
310 return 0;
311}
312
c7eeea93
PM		 313static int mma8452_read_raw(struct iio_dev *indio_dev,
314 struct iio_chan_spec const *chan,
315 int *val, int *val2, long mask)
316{
317 struct mma8452_data *data = iio_priv(indio_dev);
318 __be16 buffer[3];
319 int i, ret;
320
321 switch (mask) {
322 case IIO_CHAN_INFO_RAW:
323 if (iio_buffer_enabled(indio_dev))
324 return -EBUSY;
325
326 mutex_lock(&data->lock);
327 ret = mma8452_read(data, buffer);
328 mutex_unlock(&data->lock);
329 if (ret < 0)
330 return ret;
686027fb 331
c3cdd6e4
MK		 332 *val = sign_extend32(be16_to_cpu(
333 buffer[chan->scan_index]) >> chan->scan_type.shift,
334 chan->scan_type.realbits - 1);
686027fb 335
c7eeea93
PM		 336 return IIO_VAL_INT;
337 case IIO_CHAN_INFO_SCALE:
338 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
c3cdd6e4
MK		 339 *val = data->chip_info->mma_scales[i][0];
340 *val2 = data->chip_info->mma_scales[i][1];
686027fb 341
c7eeea93
PM		 342 return IIO_VAL_INT_PLUS_MICRO;
343 case IIO_CHAN_INFO_SAMP_FREQ:
5dbbd19f 344 i = mma8452_get_odr_index(data);
c7eeea93
PM		 345 *val = mma8452_samp_freq[i][0];
346 *val2 = mma8452_samp_freq[i][1];
686027fb 347
c7eeea93
PM		 348 return IIO_VAL_INT_PLUS_MICRO;
349 case IIO_CHAN_INFO_CALIBBIAS:
686027fb
HK		 350 ret = i2c_smbus_read_byte_data(data->client,
351 MMA8452_OFF_X + chan->scan_index);
c7eeea93
PM		 352 if (ret < 0)
353 return ret;
686027fb 354
c7eeea93 355 *val = sign_extend32(ret, 7);
686027fb 356
c7eeea93 357 return IIO_VAL_INT;
1e79841a
MF		 358 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
359 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
360 ret = mma8452_read_hp_filter(data, val, val2);
361 if (ret < 0)
362 return ret;
363 } else {
364 *val = 0;
365 *val2 = 0;
366 }
686027fb 367
1e79841a 368 return IIO_VAL_INT_PLUS_MICRO;
c7eeea93 369 }
686027fb 370
c7eeea93
PM		 371 return -EINVAL;
372}
373
374static int mma8452_standby(struct mma8452_data *data)
375{
376 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
686027fb 377 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
c7eeea93
PM		 378}
379
380static int mma8452_active(struct mma8452_data *data)
381{
382 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
686027fb 383 data->ctrl_reg1);
c7eeea93
PM		 384}
385
386static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
387{
388 int ret;
389
390 mutex_lock(&data->lock);
391
392 /* config can only be changed when in standby */
393 ret = mma8452_standby(data);
394 if (ret < 0)
395 goto fail;
396
397 ret = i2c_smbus_write_byte_data(data->client, reg, val);
398 if (ret < 0)
399 goto fail;
400
401 ret = mma8452_active(data);
402 if (ret < 0)
403 goto fail;
404
405 ret = 0;
406fail:
407 mutex_unlock(&data->lock);
686027fb 408
c7eeea93
PM		 409 return ret;
410}
411
1e79841a
MF		 412static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
413 int val, int val2)
414{
415 int i, reg;
416
417 i = mma8452_get_hp_filter_index(data, val, val2);
418 if (i < 0)
b9fddcdb 419 return i;
1e79841a
MF		 420
421 reg = i2c_smbus_read_byte_data(data->client,
422 MMA8452_HP_FILTER_CUTOFF);
423 if (reg < 0)
424 return reg;
686027fb 425
1e79841a
MF		 426 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
427 reg |= i;
428
429 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
430}
431
c7eeea93
PM		 432static int mma8452_write_raw(struct iio_dev *indio_dev,
433 struct iio_chan_spec const *chan,
434 int val, int val2, long mask)
435{
436 struct mma8452_data *data = iio_priv(indio_dev);
1e79841a 437 int i, ret;
c7eeea93
PM		 438
439 if (iio_buffer_enabled(indio_dev))
440 return -EBUSY;
441
442 switch (mask) {
443 case IIO_CHAN_INFO_SAMP_FREQ:
444 i = mma8452_get_samp_freq_index(data, val, val2);
445 if (i < 0)
b9fddcdb 446 return i;
c7eeea93
PM		 447
448 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
449 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
686027fb 450
c7eeea93 451 return mma8452_change_config(data, MMA8452_CTRL_REG1,
686027fb 452 data->ctrl_reg1);
c7eeea93
PM		 453 case IIO_CHAN_INFO_SCALE:
454 i = mma8452_get_scale_index(data, val, val2);
455 if (i < 0)
b9fddcdb 456 return i;
686027fb 457
c7eeea93
PM		 458 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
459 data->data_cfg |= i;
686027fb 460
c7eeea93 461 return mma8452_change_config(data, MMA8452_DATA_CFG,
686027fb 462 data->data_cfg);
c7eeea93
PM		 463 case IIO_CHAN_INFO_CALIBBIAS:
464 if (val < -128 || val > 127)
465 return -EINVAL;
686027fb
HK		 466
467 return mma8452_change_config(data,
468 MMA8452_OFF_X + chan->scan_index,
469 val);
1e79841a
MF		 470
471 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
472 if (val == 0 && val2 == 0) {
473 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
474 } else {
475 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
476 ret = mma8452_set_hp_filter_frequency(data, val, val2);
477 if (ret < 0)
478 return ret;
479 }
686027fb 480
1e79841a 481 return mma8452_change_config(data, MMA8452_DATA_CFG,
686027fb 482 data->data_cfg);
1e79841a 483
c7eeea93
PM		 484 default:
485 return -EINVAL;
486 }
487}
488
28e34278
MF		 489static int mma8452_read_thresh(struct iio_dev *indio_dev,
490 const struct iio_chan_spec *chan,
491 enum iio_event_type type,
492 enum iio_event_direction dir,
493 enum iio_event_info info,
494 int *val, int *val2)
495{
496 struct mma8452_data *data = iio_priv(indio_dev);
5dbbd19f 497 int ret, us;
28e34278 498
5dbbd19f
MF		 499 switch (info) {
500 case IIO_EV_INFO_VALUE:
501 ret = i2c_smbus_read_byte_data(data->client,
c3cdd6e4 502 data->chip_info->ev_ths);
5dbbd19f
MF		 503 if (ret < 0)
504 return ret;
505
c3cdd6e4 506 *val = ret & data->chip_info->ev_ths_mask;
686027fb 507
5dbbd19f 508 return IIO_VAL_INT;
28e34278 509
5dbbd19f
MF		 510 case IIO_EV_INFO_PERIOD:
511 ret = i2c_smbus_read_byte_data(data->client,
c3cdd6e4 512 data->chip_info->ev_count);
5dbbd19f
MF		 513 if (ret < 0)
514 return ret;
515
516 us = ret * mma8452_transient_time_step_us[
517 mma8452_get_odr_index(data)];
518 *val = us / USEC_PER_SEC;
519 *val2 = us % USEC_PER_SEC;
686027fb 520
5dbbd19f 521 return IIO_VAL_INT_PLUS_MICRO;
28e34278 522
1e79841a
MF		 523 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
524 ret = i2c_smbus_read_byte_data(data->client,
525 MMA8452_TRANSIENT_CFG);
526 if (ret < 0)
527 return ret;
528
529 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
530 *val = 0;
531 *val2 = 0;
532 } else {
533 ret = mma8452_read_hp_filter(data, val, val2);
534 if (ret < 0)
535 return ret;
536 }
686027fb 537
1e79841a
MF		 538 return IIO_VAL_INT_PLUS_MICRO;
539
5dbbd19f
MF		 540 default:
541 return -EINVAL;
542 }
28e34278
MF		 543}
544
545static int mma8452_write_thresh(struct iio_dev *indio_dev,
546 const struct iio_chan_spec *chan,
547 enum iio_event_type type,
548 enum iio_event_direction dir,
549 enum iio_event_info info,
550 int val, int val2)
551{
552 struct mma8452_data *data = iio_priv(indio_dev);
1e79841a 553 int ret, reg, steps;
28e34278 554
5dbbd19f
MF		 555 switch (info) {
556 case IIO_EV_INFO_VALUE:
11218226
HK		 557 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
558 return -EINVAL;
559
c3cdd6e4
MK		 560 return mma8452_change_config(data, data->chip_info->ev_ths,
561 val);
5dbbd19f
MF		 562
563 case IIO_EV_INFO_PERIOD:
564 steps = (val * USEC_PER_SEC + val2) /
565 mma8452_transient_time_step_us[
566 mma8452_get_odr_index(data)];
567
11218226 568 if (steps < 0 || steps > 0xff)
5dbbd19f
MF		 569 return -EINVAL;
570
c3cdd6e4 571 return mma8452_change_config(data, data->chip_info->ev_count,
5dbbd19f 572 steps);
686027fb 573
1e79841a
MF		 574 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
575 reg = i2c_smbus_read_byte_data(data->client,
576 MMA8452_TRANSIENT_CFG);
577 if (reg < 0)
578 return reg;
579
580 if (val == 0 && val2 == 0) {
581 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
582 } else {
583 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
584 ret = mma8452_set_hp_filter_frequency(data, val, val2);
585 if (ret < 0)
586 return ret;
587 }
686027fb 588
1e79841a
MF		 589 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
590
5dbbd19f
MF		 591 default:
592 return -EINVAL;
593 }
28e34278
MF		 594}
595
596static int mma8452_read_event_config(struct iio_dev *indio_dev,
597 const struct iio_chan_spec *chan,
598 enum iio_event_type type,
599 enum iio_event_direction dir)
600{
601 struct mma8452_data *data = iio_priv(indio_dev);
c3cdd6e4 602 const struct mma_chip_info *chip = data->chip_info;
28e34278
MF		 603 int ret;
604
c3cdd6e4
MK		 605 ret = i2c_smbus_read_byte_data(data->client,
606 data->chip_info->ev_cfg);
28e34278
MF		 607 if (ret < 0)
608 return ret;
609
c3cdd6e4 610 return !!(ret & BIT(chan->scan_index + chip->ev_cfg_chan_shift));
28e34278
MF		 611}
612
613static int mma8452_write_event_config(struct iio_dev *indio_dev,
614 const struct iio_chan_spec *chan,
615 enum iio_event_type type,
616 enum iio_event_direction dir,
617 int state)
618{
619 struct mma8452_data *data = iio_priv(indio_dev);
c3cdd6e4 620 const struct mma_chip_info *chip = data->chip_info;
28e34278
MF		 621 int val;
622
c3cdd6e4 623 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
28e34278
MF		 624 if (val < 0)
625 return val;
626
627 if (state)
c3cdd6e4 628 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
28e34278 629 else
c3cdd6e4 630 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
28e34278 631
60f562e7
MK		 632 val |= chip->ev_cfg_ele;
633 val |= MMA8452_FF_MT_CFG_OAE;
28e34278 634
c3cdd6e4 635 return mma8452_change_config(data, chip->ev_cfg, val);
28e34278
MF		 636}
637
638static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
639{
640 struct mma8452_data *data = iio_priv(indio_dev);
641 s64 ts = iio_get_time_ns();
642 int src;
643
c3cdd6e4 644 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
28e34278
MF		 645 if (src < 0)
646 return;
647
c3cdd6e4 648 if (src & data->chip_info->ev_src_xe)
28e34278
MF		 649 iio_push_event(indio_dev,
650 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
c5d0db06 651 IIO_EV_TYPE_MAG,
28e34278
MF		 652 IIO_EV_DIR_RISING),
653 ts);
654
c3cdd6e4 655 if (src & data->chip_info->ev_src_ye)
28e34278
MF		 656 iio_push_event(indio_dev,
657 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
c5d0db06 658 IIO_EV_TYPE_MAG,
28e34278
MF		 659 IIO_EV_DIR_RISING),
660 ts);
661
c3cdd6e4 662 if (src & data->chip_info->ev_src_ze)
28e34278
MF		 663 iio_push_event(indio_dev,
664 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
c5d0db06 665 IIO_EV_TYPE_MAG,
28e34278
MF		 666 IIO_EV_DIR_RISING),
667 ts);
668}
669
670static irqreturn_t mma8452_interrupt(int irq, void *p)
671{
672 struct iio_dev *indio_dev = p;
673 struct mma8452_data *data = iio_priv(indio_dev);
60f562e7 674 const struct mma_chip_info *chip = data->chip_info;
ae6d9ce0 675 int ret = IRQ_NONE;
28e34278
MF		 676 int src;
677
678 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
679 if (src < 0)
680 return IRQ_NONE;
681
ae6d9ce0
MF		 682 if (src & MMA8452_INT_DRDY) {
683 iio_trigger_poll_chained(indio_dev->trig);
684 ret = IRQ_HANDLED;
685 }
686
60f562e7
MK		 687 if ((src & MMA8452_INT_TRANS &&
688 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
689 (src & MMA8452_INT_FF_MT &&
690 chip->ev_src == MMA8452_FF_MT_SRC)) {
28e34278 691 mma8452_transient_interrupt(indio_dev);
ae6d9ce0 692 ret = IRQ_HANDLED;
28e34278
MF		 693 }
694
ae6d9ce0 695 return ret;
28e34278
MF		 696}
697
c7eeea93
PM		 698static irqreturn_t mma8452_trigger_handler(int irq, void *p)
699{
700 struct iio_poll_func *pf = p;
701 struct iio_dev *indio_dev = pf->indio_dev;
702 struct mma8452_data *data = iio_priv(indio_dev);
703 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
704 int ret;
705
686027fb 706 ret = mma8452_read(data, (__be16 *)buffer);
c7eeea93
PM		 707 if (ret < 0)
708 goto done;
709
710 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
686027fb 711 iio_get_time_ns());
c7eeea93
PM		 712
713done:
714 iio_trigger_notify_done(indio_dev->trig);
686027fb 715
c7eeea93
PM		 716 return IRQ_HANDLED;
717}
718
2a17698c
MF		 719static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
720 unsigned reg, unsigned writeval,
721 unsigned *readval)
722{
723 int ret;
724 struct mma8452_data *data = iio_priv(indio_dev);
725
726 if (reg > MMA8452_MAX_REG)
727 return -EINVAL;
728
729 if (!readval)
730 return mma8452_change_config(data, reg, writeval);
731
732 ret = i2c_smbus_read_byte_data(data->client, reg);
733 if (ret < 0)
734 return ret;
735
736 *readval = ret;
737
738 return 0;
739}
740
28e34278
MF		 741static const struct iio_event_spec mma8452_transient_event[] = {
742 {
c5d0db06 743 .type = IIO_EV_TYPE_MAG,
28e34278
MF		 744 .dir = IIO_EV_DIR_RISING,
745 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
5dbbd19f 746 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1e79841a
MF		 747 BIT(IIO_EV_INFO_PERIOD) |
748 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
28e34278
MF		 749 },
750};
751
60f562e7
MK		 752static const struct iio_event_spec mma8452_motion_event[] = {
753 {
754 .type = IIO_EV_TYPE_MAG,
755 .dir = IIO_EV_DIR_RISING,
756 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
757 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
758 BIT(IIO_EV_INFO_PERIOD)
759 },
760};
761
28e34278
MF		 762/*
763 * Threshold is configured in fixed 8G/127 steps regardless of
764 * currently selected scale for measurement.
765 */
766static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
767
768static struct attribute *mma8452_event_attributes[] = {
769 &iio_const_attr_accel_transient_scale.dev_attr.attr,
770 NULL,
771};
772
773static struct attribute_group mma8452_event_attribute_group = {
774 .attrs = mma8452_event_attributes,
28e34278
MF		 775};
776
c3cdd6e4 777#define MMA8452_CHANNEL(axis, idx, bits) { \
c7eeea93
PM		 778 .type = IIO_ACCEL, \
779 .modified = 1, \
780 .channel2 = IIO_MOD_##axis, \
781 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
686027fb 782 BIT(IIO_CHAN_INFO_CALIBBIAS), \
c7eeea93 783 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
686027fb
HK		 784 BIT(IIO_CHAN_INFO_SCALE) | \
785 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
c7eeea93
PM		 786 .scan_index = idx, \
787 .scan_type = { \
788 .sign = 's', \
c3cdd6e4 789 .realbits = (bits), \
c7eeea93 790 .storagebits = 16, \
c3cdd6e4 791 .shift = 16 - (bits), \
c7eeea93
PM		 792 .endianness = IIO_BE, \
793 }, \
28e34278
MF		 794 .event_spec = mma8452_transient_event, \
795 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
c7eeea93
PM		 796}
797
417e008b
MK		 798#define MMA8652_CHANNEL(axis, idx, bits) { \
799 .type = IIO_ACCEL, \
800 .modified = 1, \
801 .channel2 = IIO_MOD_##axis, \
802 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
803 BIT(IIO_CHAN_INFO_CALIBBIAS), \
804 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
805 BIT(IIO_CHAN_INFO_SCALE), \
806 .scan_index = idx, \
807 .scan_type = { \
808 .sign = 's', \
809 .realbits = (bits), \
810 .storagebits = 16, \
811 .shift = 16 - (bits), \
812 .endianness = IIO_BE, \
813 }, \
814 .event_spec = mma8452_motion_event, \
815 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
816}
817
c7eeea93 818static const struct iio_chan_spec mma8452_channels[] = {
c3cdd6e4
MK		 819 MMA8452_CHANNEL(X, 0, 12),
820 MMA8452_CHANNEL(Y, 1, 12),
821 MMA8452_CHANNEL(Z, 2, 12),
c7eeea93
PM		 822 IIO_CHAN_SOFT_TIMESTAMP(3),
823};
824
c5ea1b58
MK		 825static const struct iio_chan_spec mma8453_channels[] = {
826 MMA8452_CHANNEL(X, 0, 10),
827 MMA8452_CHANNEL(Y, 1, 10),
828 MMA8452_CHANNEL(Z, 2, 10),
829 IIO_CHAN_SOFT_TIMESTAMP(3),
830};
831
417e008b
MK		 832static const struct iio_chan_spec mma8652_channels[] = {
833 MMA8652_CHANNEL(X, 0, 12),
834 MMA8652_CHANNEL(Y, 1, 12),
835 MMA8652_CHANNEL(Z, 2, 12),
836 IIO_CHAN_SOFT_TIMESTAMP(3),
837};
838
839static const struct iio_chan_spec mma8653_channels[] = {
840 MMA8652_CHANNEL(X, 0, 10),
841 MMA8652_CHANNEL(Y, 1, 10),
842 MMA8652_CHANNEL(Z, 2, 10),
843 IIO_CHAN_SOFT_TIMESTAMP(3),
844};
845
c3cdd6e4
MK		 846enum {
847 mma8452,
c5ea1b58 848 mma8453,
417e008b
MK		 849 mma8652,
850 mma8653,
c3cdd6e4
MK		 851};
852
853static const struct mma_chip_info mma_chip_info_table[] = {
854 [mma8452] = {
855 .chip_id = MMA8452_DEVICE_ID,
856 .channels = mma8452_channels,
857 .num_channels = ARRAY_SIZE(mma8452_channels),
858 /*
859 * Hardware has fullscale of -2G, -4G, -8G corresponding to
860 * raw value -2048 for 12 bit or -512 for 10 bit.
861 * The userspace interface uses m/s^2 and we declare micro units
862 * So scale factor for 12 bit here is given by:
863 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
864 */
865 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
866 .ev_cfg = MMA8452_TRANSIENT_CFG,
867 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
868 .ev_cfg_chan_shift = 1,
869 .ev_src = MMA8452_TRANSIENT_SRC,
870 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
871 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
872 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
873 .ev_ths = MMA8452_TRANSIENT_THS,
874 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
875 .ev_count = MMA8452_TRANSIENT_COUNT,
876 },
c5ea1b58
MK		 877 [mma8453] = {
878 .chip_id = MMA8453_DEVICE_ID,
879 .channels = mma8453_channels,
880 .num_channels = ARRAY_SIZE(mma8453_channels),
881 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
882 .ev_cfg = MMA8452_TRANSIENT_CFG,
883 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
884 .ev_cfg_chan_shift = 1,
885 .ev_src = MMA8452_TRANSIENT_SRC,
886 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
887 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
888 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
889 .ev_ths = MMA8452_TRANSIENT_THS,
890 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
891 .ev_count = MMA8452_TRANSIENT_COUNT,
892 },
417e008b
MK		 893 [mma8652] = {
894 .chip_id = MMA8652_DEVICE_ID,
895 .channels = mma8652_channels,
896 .num_channels = ARRAY_SIZE(mma8652_channels),
897 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
898 .ev_cfg = MMA8452_FF_MT_CFG,
899 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
900 .ev_cfg_chan_shift = 3,
901 .ev_src = MMA8452_FF_MT_SRC,
902 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
903 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
904 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
905 .ev_ths = MMA8452_FF_MT_THS,
906 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
907 .ev_count = MMA8452_FF_MT_COUNT,
908 },
909 [mma8653] = {
910 .chip_id = MMA8653_DEVICE_ID,
911 .channels = mma8653_channels,
912 .num_channels = ARRAY_SIZE(mma8653_channels),
913 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
914 .ev_cfg = MMA8452_FF_MT_CFG,
915 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
916 .ev_cfg_chan_shift = 3,
917 .ev_src = MMA8452_FF_MT_SRC,
918 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
919 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
920 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
921 .ev_ths = MMA8452_FF_MT_THS,
922 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
923 .ev_count = MMA8452_FF_MT_COUNT,
924 },
c3cdd6e4
MK		 925};
926
c7eeea93
PM		 927static struct attribute *mma8452_attributes[] = {
928 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
929 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1e79841a 930 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
c7eeea93
PM		 931 NULL
932};
933
934static const struct attribute_group mma8452_group = {
935 .attrs = mma8452_attributes,
936};
937
938static const struct iio_info mma8452_info = {
939 .attrs = &mma8452_group,
940 .read_raw = &mma8452_read_raw,
941 .write_raw = &mma8452_write_raw,
28e34278
MF		 942 .event_attrs = &mma8452_event_attribute_group,
943 .read_event_value = &mma8452_read_thresh,
944 .write_event_value = &mma8452_write_thresh,
945 .read_event_config = &mma8452_read_event_config,
946 .write_event_config = &mma8452_write_event_config,
2a17698c 947 .debugfs_reg_access = &mma8452_reg_access_dbg,
c7eeea93
PM		 948 .driver_module = THIS_MODULE,
949};
950
951static const unsigned long mma8452_scan_masks[] = {0x7, 0};
952
ae6d9ce0
MF		 953static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
954 bool state)
955{
956 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
957 struct mma8452_data *data = iio_priv(indio_dev);
958 int reg;
959
960 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
961 if (reg < 0)
962 return reg;
963
964 if (state)
965 reg |= MMA8452_INT_DRDY;
966 else
967 reg &= ~MMA8452_INT_DRDY;
968
969 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
970}
971
972static int mma8452_validate_device(struct iio_trigger *trig,
973 struct iio_dev *indio_dev)
974{
975 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
976
977 if (indio != indio_dev)
978 return -EINVAL;
979
980 return 0;
981}
982
983static const struct iio_trigger_ops mma8452_trigger_ops = {
984 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
985 .validate_device = mma8452_validate_device,
986 .owner = THIS_MODULE,
987};
988
989static int mma8452_trigger_setup(struct iio_dev *indio_dev)
990{
991 struct mma8452_data *data = iio_priv(indio_dev);
992 struct iio_trigger *trig;
993 int ret;
994
995 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
996 indio_dev->name,
997 indio_dev->id);
998 if (!trig)
999 return -ENOMEM;
1000
1001 trig->dev.parent = &data->client->dev;
1002 trig->ops = &mma8452_trigger_ops;
1003 iio_trigger_set_drvdata(trig, indio_dev);
1004
1005 ret = iio_trigger_register(trig);
1006 if (ret)
1007 return ret;
1008
1009 indio_dev->trig = trig;
686027fb 1010
ae6d9ce0
MF		 1011 return 0;
1012}
1013
1014static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1015{
1016 if (indio_dev->trig)
1017 iio_trigger_unregister(indio_dev->trig);
1018}
1019
ecabae71
MF		 1020static int mma8452_reset(struct i2c_client *client)
1021{
1022 int i;
1023 int ret;
1024
1025 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1026 MMA8452_CTRL_REG2_RST);
1027 if (ret < 0)
1028 return ret;
1029
1030 for (i = 0; i < 10; i++) {
1031 usleep_range(100, 200);
1032 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1033 if (ret == -EIO)
1034 continue; /* I2C comm reset */
1035 if (ret < 0)
1036 return ret;
1037 if (!(ret & MMA8452_CTRL_REG2_RST))
1038 return 0;
1039 }
1040
1041 return -ETIMEDOUT;
1042}
1043
c3cdd6e4
MK		 1044static const struct of_device_id mma8452_dt_ids[] = {
1045 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
c5ea1b58 1046 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
417e008b
MK		 1047 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1048 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
c3cdd6e4
MK		 1049 { }
1050};
1051MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1052
c7eeea93
PM		 1053static int mma8452_probe(struct i2c_client *client,
1054 const struct i2c_device_id *id)
1055{
1056 struct mma8452_data *data;
1057 struct iio_dev *indio_dev;
1058 int ret;
c3cdd6e4 1059 const struct of_device_id *match;
c7eeea93 1060
c3cdd6e4
MK		 1061 match = of_match_device(mma8452_dt_ids, &client->dev);
1062 if (!match) {
1063 dev_err(&client->dev, "unknown device model\n");
1064 return -ENODEV;
1065 }
1066
c7eeea93
PM		 1067 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1068 if (!indio_dev)
1069 return -ENOMEM;
1070
1071 data = iio_priv(indio_dev);
1072 data->client = client;
1073 mutex_init(&data->lock);
c3cdd6e4
MK		 1074 data->chip_info = match->data;
1075
417e008b
MK		 1076 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1077 if (ret < 0)
1078 return ret;
1079
1080 switch (ret) {
1081 case MMA8452_DEVICE_ID:
1082 case MMA8453_DEVICE_ID:
1083 case MMA8652_DEVICE_ID:
1084 case MMA8653_DEVICE_ID:
1085 if (ret == data->chip_info->chip_id)
1086 break;
1087 default:
1088 return -ENODEV;
1089 }
1090
c3cdd6e4
MK		 1091 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1092 match->compatible, data->chip_info->chip_id);
c7eeea93
PM		 1093
1094 i2c_set_clientdata(client, indio_dev);
1095 indio_dev->info = &mma8452_info;
1096 indio_dev->name = id->name;
1097 indio_dev->dev.parent = &client->dev;
1098 indio_dev->modes = INDIO_DIRECT_MODE;
c3cdd6e4
MK		 1099 indio_dev->channels = data->chip_info->channels;
1100 indio_dev->num_channels = data->chip_info->num_channels;
c7eeea93
PM		 1101 indio_dev->available_scan_masks = mma8452_scan_masks;
1102
ecabae71 1103 ret = mma8452_reset(client);
c7eeea93
PM		 1104 if (ret < 0)
1105 return ret;
1106
1107 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1108 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
686027fb 1109 data->data_cfg);
c7eeea93
PM		 1110 if (ret < 0)
1111 return ret;
1112
28e34278
MF		 1113 /*
1114 * By default set transient threshold to max to avoid events if
1115 * enabling without configuring threshold.
1116 */
1117 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1118 MMA8452_TRANSIENT_THS_MASK);
1119 if (ret < 0)
1120 return ret;
1121
1122 if (client->irq) {
1123 /*
60f562e7
MK		 1124 * Although we enable the interrupt sources once and for
1125 * all here the event detection itself is not enabled until
1126 * userspace asks for it by mma8452_write_event_config()
28e34278 1127 */
60f562e7
MK		 1128 int supported_interrupts = MMA8452_INT_DRDY |
1129 MMA8452_INT_TRANS |
1130 MMA8452_INT_FF_MT;
1131 int enabled_interrupts = MMA8452_INT_TRANS |
1132 MMA8452_INT_FF_MT;
28e34278
MF		 1133
1134 /* Assume wired to INT1 pin */
1135 ret = i2c_smbus_write_byte_data(client,
1136 MMA8452_CTRL_REG5,
1137 supported_interrupts);
1138 if (ret < 0)
1139 return ret;
1140
1141 ret = i2c_smbus_write_byte_data(client,
1142 MMA8452_CTRL_REG4,
ae6d9ce0
MF		 1143 enabled_interrupts);
1144 if (ret < 0)
1145 return ret;
1146
1147 ret = mma8452_trigger_setup(indio_dev);
28e34278
MF		 1148 if (ret < 0)
1149 return ret;
1150 }
1151
ecabae71 1152 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
686027fb 1153 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
ecabae71
MF		 1154 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1155 data->ctrl_reg1);
1156 if (ret < 0)
ae6d9ce0 1157 goto trigger_cleanup;
ecabae71 1158
c7eeea93 1159 ret = iio_triggered_buffer_setup(indio_dev, NULL,
686027fb 1160 mma8452_trigger_handler, NULL);
c7eeea93 1161 if (ret < 0)
ae6d9ce0 1162 goto trigger_cleanup;
c7eeea93 1163
28e34278
MF		 1164 if (client->irq) {
1165 ret = devm_request_threaded_irq(&client->dev,
1166 client->irq,
1167 NULL, mma8452_interrupt,
1168 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1169 client->name, indio_dev);
1170 if (ret)
1171 goto buffer_cleanup;
1172 }
1173
c7eeea93
PM		 1174 ret = iio_device_register(indio_dev);
1175 if (ret < 0)
1176 goto buffer_cleanup;
28e34278 1177
c7eeea93
PM		 1178 return 0;
1179
1180buffer_cleanup:
1181 iio_triggered_buffer_cleanup(indio_dev);
ae6d9ce0
MF		 1182
1183trigger_cleanup:
1184 mma8452_trigger_cleanup(indio_dev);
1185
c7eeea93
PM		 1186 return ret;
1187}
1188
1189static int mma8452_remove(struct i2c_client *client)
1190{
1191 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1192
1193 iio_device_unregister(indio_dev);
1194 iio_triggered_buffer_cleanup(indio_dev);
ae6d9ce0 1195 mma8452_trigger_cleanup(indio_dev);
c7eeea93
PM		 1196 mma8452_standby(iio_priv(indio_dev));
1197
1198 return 0;
1199}
1200
1201#ifdef CONFIG_PM_SLEEP
1202static int mma8452_suspend(struct device *dev)
1203{
1204 return mma8452_standby(iio_priv(i2c_get_clientdata(
1205 to_i2c_client(dev))));
1206}
1207
1208static int mma8452_resume(struct device *dev)
1209{
1210 return mma8452_active(iio_priv(i2c_get_clientdata(
1211 to_i2c_client(dev))));
1212}
1213
1214static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
1215#define MMA8452_PM_OPS (&mma8452_pm_ops)
1216#else
1217#define MMA8452_PM_OPS NULL
1218#endif
1219
1220static const struct i2c_device_id mma8452_id[] = {
c3cdd6e4 1221 { "mma8452", mma8452 },
c5ea1b58 1222 { "mma8453", mma8453 },
417e008b
MK		 1223 { "mma8652", mma8652 },
1224 { "mma8653", mma8653 },
c7eeea93
PM		 1225 { }
1226};
1227MODULE_DEVICE_TABLE(i2c, mma8452_id);
1228
1229static struct i2c_driver mma8452_driver = {
1230 .driver = {
1231 .name = "mma8452",
a3fb96a8 1232 .of_match_table = of_match_ptr(mma8452_dt_ids),
c7eeea93
PM		 1233 .pm = MMA8452_PM_OPS,
1234 },
1235 .probe = mma8452_probe,
1236 .remove = mma8452_remove,
1237 .id_table = mma8452_id,
1238};
1239module_i2c_driver(mma8452_driver);
1240
1241MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1242MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1243MODULE_LICENSE("GPL");
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