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Commit | Line | Data |
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7c31b984 MH |
1 | /* |
2 | * AD7298 SPI ADC driver | |
3 | * | |
4 | * Copyright 2011 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2. | |
7 | */ | |
8 | ||
7c31b984 MH |
9 | #include <linux/device.h> |
10 | #include <linux/kernel.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/sysfs.h> | |
13 | #include <linux/spi/spi.h> | |
14 | #include <linux/regulator/consumer.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/delay.h> | |
99c97852 | 17 | #include <linux/module.h> |
dc4871ad | 18 | #include <linux/interrupt.h> |
48898053 | 19 | #include <linux/bitops.h> |
7c31b984 | 20 | |
06458e27 JC |
21 | #include <linux/iio/iio.h> |
22 | #include <linux/iio/sysfs.h> | |
23 | #include <linux/iio/buffer.h> | |
dc4871ad LPC |
24 | #include <linux/iio/trigger_consumer.h> |
25 | #include <linux/iio/triggered_buffer.h> | |
7c31b984 | 26 | |
709ab36e | 27 | #include <linux/platform_data/ad7298.h> |
7c31b984 | 28 | |
48898053 PM |
29 | #define AD7298_WRITE BIT(15) /* write to the control register */ |
30 | #define AD7298_REPEAT BIT(14) /* repeated conversion enable */ | |
31 | #define AD7298_CH(x) BIT(13 - (x)) /* channel select */ | |
32 | #define AD7298_TSENSE BIT(5) /* temperature conversion enable */ | |
33 | #define AD7298_EXTREF BIT(2) /* external reference enable */ | |
34 | #define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */ | |
35 | #define AD7298_PDD BIT(0) /* partial power down enable */ | |
dc4871ad LPC |
36 | |
37 | #define AD7298_MAX_CHAN 8 | |
dc4871ad LPC |
38 | #define AD7298_INTREF_mV 2500 |
39 | ||
40 | #define AD7298_CH_TEMP 9 | |
41 | ||
dc4871ad LPC |
42 | struct ad7298_state { |
43 | struct spi_device *spi; | |
44 | struct regulator *reg; | |
45 | unsigned ext_ref; | |
46 | struct spi_transfer ring_xfer[10]; | |
47 | struct spi_transfer scan_single_xfer[3]; | |
48 | struct spi_message ring_msg; | |
49 | struct spi_message scan_single_msg; | |
50 | /* | |
51 | * DMA (thus cache coherency maintenance) requires the | |
52 | * transfer buffers to live in their own cache lines. | |
53 | */ | |
be7fd3b8 JC |
54 | __be16 rx_buf[12] ____cacheline_aligned; |
55 | __be16 tx_buf[2]; | |
dc4871ad LPC |
56 | }; |
57 | ||
95e48f77 JC |
58 | #define AD7298_V_CHAN(index) \ |
59 | { \ | |
60 | .type = IIO_VOLTAGE, \ | |
61 | .indexed = 1, \ | |
62 | .channel = index, \ | |
40dd676d JC |
63 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
64 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ | |
95e48f77 JC |
65 | .address = index, \ |
66 | .scan_index = index, \ | |
67 | .scan_type = { \ | |
68 | .sign = 'u', \ | |
69 | .realbits = 12, \ | |
70 | .storagebits = 16, \ | |
ca654638 | 71 | .endianness = IIO_BE, \ |
95e48f77 JC |
72 | }, \ |
73 | } | |
74 | ||
f4e4b955 | 75 | static const struct iio_chan_spec ad7298_channels[] = { |
95e48f77 JC |
76 | { |
77 | .type = IIO_TEMP, | |
78 | .indexed = 1, | |
79 | .channel = 0, | |
40dd676d JC |
80 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | |
81 | BIT(IIO_CHAN_INFO_SCALE) | | |
82 | BIT(IIO_CHAN_INFO_OFFSET), | |
d045b9d2 LPC |
83 | .address = AD7298_CH_TEMP, |
84 | .scan_index = -1, | |
95e48f77 JC |
85 | .scan_type = { |
86 | .sign = 's', | |
87 | .realbits = 32, | |
88 | .storagebits = 32, | |
89 | }, | |
90 | }, | |
91 | AD7298_V_CHAN(0), | |
92 | AD7298_V_CHAN(1), | |
93 | AD7298_V_CHAN(2), | |
94 | AD7298_V_CHAN(3), | |
95 | AD7298_V_CHAN(4), | |
96 | AD7298_V_CHAN(5), | |
97 | AD7298_V_CHAN(6), | |
98 | AD7298_V_CHAN(7), | |
01a99e18 MH |
99 | IIO_CHAN_SOFT_TIMESTAMP(8), |
100 | }; | |
101 | ||
dc4871ad LPC |
102 | /** |
103 | * ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask | |
104 | **/ | |
105 | static int ad7298_update_scan_mode(struct iio_dev *indio_dev, | |
106 | const unsigned long *active_scan_mask) | |
107 | { | |
108 | struct ad7298_state *st = iio_priv(indio_dev); | |
109 | int i, m; | |
110 | unsigned short command; | |
111 | int scan_count; | |
112 | ||
113 | /* Now compute overall size */ | |
114 | scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength); | |
115 | ||
116 | command = AD7298_WRITE | st->ext_ref; | |
117 | ||
118 | for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1) | |
119 | if (test_bit(i, active_scan_mask)) | |
120 | command |= m; | |
121 | ||
122 | st->tx_buf[0] = cpu_to_be16(command); | |
123 | ||
124 | /* build spi ring message */ | |
125 | st->ring_xfer[0].tx_buf = &st->tx_buf[0]; | |
126 | st->ring_xfer[0].len = 2; | |
127 | st->ring_xfer[0].cs_change = 1; | |
128 | st->ring_xfer[1].tx_buf = &st->tx_buf[1]; | |
129 | st->ring_xfer[1].len = 2; | |
130 | st->ring_xfer[1].cs_change = 1; | |
131 | ||
132 | spi_message_init(&st->ring_msg); | |
133 | spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg); | |
134 | spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg); | |
135 | ||
136 | for (i = 0; i < scan_count; i++) { | |
137 | st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i]; | |
138 | st->ring_xfer[i + 2].len = 2; | |
139 | st->ring_xfer[i + 2].cs_change = 1; | |
140 | spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg); | |
141 | } | |
142 | /* make sure last transfer cs_change is not set */ | |
143 | st->ring_xfer[i + 1].cs_change = 0; | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | /** | |
149 | * ad7298_trigger_handler() bh of trigger launched polling to ring buffer | |
150 | * | |
151 | * Currently there is no option in this driver to disable the saving of | |
152 | * timestamps within the ring. | |
153 | **/ | |
154 | static irqreturn_t ad7298_trigger_handler(int irq, void *p) | |
155 | { | |
156 | struct iio_poll_func *pf = p; | |
157 | struct iio_dev *indio_dev = pf->indio_dev; | |
158 | struct ad7298_state *st = iio_priv(indio_dev); | |
dc4871ad LPC |
159 | int b_sent; |
160 | ||
161 | b_sent = spi_sync(st->spi, &st->ring_msg); | |
162 | if (b_sent) | |
163 | goto done; | |
164 | ||
85ec2372 | 165 | iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf, |
bc2b7dab | 166 | iio_get_time_ns(indio_dev)); |
dc4871ad LPC |
167 | |
168 | done: | |
169 | iio_trigger_notify_done(indio_dev->trig); | |
170 | ||
171 | return IRQ_HANDLED; | |
172 | } | |
173 | ||
7c31b984 MH |
174 | static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch) |
175 | { | |
176 | int ret; | |
177 | st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref | | |
178 | (AD7298_CH(0) >> ch)); | |
179 | ||
180 | ret = spi_sync(st->spi, &st->scan_single_msg); | |
181 | if (ret) | |
182 | return ret; | |
183 | ||
184 | return be16_to_cpu(st->rx_buf[0]); | |
185 | } | |
186 | ||
01a99e18 | 187 | static int ad7298_scan_temp(struct ad7298_state *st, int *val) |
7c31b984 | 188 | { |
01a10e04 | 189 | int ret; |
c1a75288 | 190 | __be16 buf; |
7c31b984 | 191 | |
c1a75288 | 192 | buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE | |
01a99e18 | 193 | AD7298_TAVG | st->ext_ref); |
7c31b984 | 194 | |
c1a75288 | 195 | ret = spi_write(st->spi, (u8 *)&buf, 2); |
01a99e18 | 196 | if (ret) |
7c31b984 MH |
197 | return ret; |
198 | ||
c1a75288 | 199 | buf = cpu_to_be16(0); |
7c31b984 | 200 | |
c1a75288 | 201 | ret = spi_write(st->spi, (u8 *)&buf, 2); |
01a99e18 MH |
202 | if (ret) |
203 | return ret; | |
7c31b984 | 204 | |
7c31b984 | 205 | usleep_range(101, 1000); /* sleep > 100us */ |
01a99e18 | 206 | |
c1a75288 | 207 | ret = spi_read(st->spi, (u8 *)&buf, 2); |
01a99e18 MH |
208 | if (ret) |
209 | return ret; | |
7c31b984 | 210 | |
01a10e04 | 211 | *val = sign_extend32(be16_to_cpu(buf), 11); |
7c31b984 | 212 | |
01a10e04 LPC |
213 | return 0; |
214 | } | |
215 | ||
216 | static int ad7298_get_ref_voltage(struct ad7298_state *st) | |
217 | { | |
218 | int vref; | |
7c31b984 | 219 | |
01a10e04 LPC |
220 | if (st->ext_ref) { |
221 | vref = regulator_get_voltage(st->reg); | |
222 | if (vref < 0) | |
223 | return vref; | |
7c31b984 | 224 | |
01a10e04 | 225 | return vref / 1000; |
7c31b984 | 226 | } else { |
01a10e04 | 227 | return AD7298_INTREF_mV; |
7c31b984 | 228 | } |
01a99e18 | 229 | } |
7c31b984 | 230 | |
84f79ecb | 231 | static int ad7298_read_raw(struct iio_dev *indio_dev, |
01a99e18 MH |
232 | struct iio_chan_spec const *chan, |
233 | int *val, | |
234 | int *val2, | |
235 | long m) | |
7c31b984 | 236 | { |
01a99e18 | 237 | int ret; |
84f79ecb | 238 | struct ad7298_state *st = iio_priv(indio_dev); |
01a99e18 MH |
239 | |
240 | switch (m) { | |
b11f98ff | 241 | case IIO_CHAN_INFO_RAW: |
d02ec00d AS |
242 | ret = iio_device_claim_direct_mode(indio_dev); |
243 | if (ret) | |
244 | return ret; | |
245 | ||
246 | if (chan->address == AD7298_CH_TEMP) | |
247 | ret = ad7298_scan_temp(st, val); | |
248 | else | |
249 | ret = ad7298_scan_direct(st, chan->address); | |
250 | ||
251 | iio_device_release_direct_mode(indio_dev); | |
01a99e18 MH |
252 | |
253 | if (ret < 0) | |
254 | return ret; | |
255 | ||
256 | if (chan->address != AD7298_CH_TEMP) | |
48898053 | 257 | *val = ret & GENMASK(chan->scan_type.realbits - 1, 0); |
01a99e18 MH |
258 | |
259 | return IIO_VAL_INT; | |
c8a9f805 JC |
260 | case IIO_CHAN_INFO_SCALE: |
261 | switch (chan->type) { | |
262 | case IIO_VOLTAGE: | |
01a10e04 | 263 | *val = ad7298_get_ref_voltage(st); |
2e334600 LPC |
264 | *val2 = chan->scan_type.realbits; |
265 | return IIO_VAL_FRACTIONAL_LOG2; | |
c8a9f805 | 266 | case IIO_TEMP: |
01a10e04 LPC |
267 | *val = ad7298_get_ref_voltage(st); |
268 | *val2 = 10; | |
269 | return IIO_VAL_FRACTIONAL; | |
c8a9f805 JC |
270 | default: |
271 | return -EINVAL; | |
272 | } | |
01a10e04 LPC |
273 | case IIO_CHAN_INFO_OFFSET: |
274 | *val = 1093 - 2732500 / ad7298_get_ref_voltage(st); | |
275 | return IIO_VAL_INT; | |
01a99e18 MH |
276 | } |
277 | return -EINVAL; | |
7c31b984 | 278 | } |
7c31b984 | 279 | |
6fe8135f JC |
280 | static const struct iio_info ad7298_info = { |
281 | .read_raw = &ad7298_read_raw, | |
d045b9d2 | 282 | .update_scan_mode = ad7298_update_scan_mode, |
6fe8135f JC |
283 | }; |
284 | ||
fc52692c | 285 | static int ad7298_probe(struct spi_device *spi) |
7c31b984 MH |
286 | { |
287 | struct ad7298_platform_data *pdata = spi->dev.platform_data; | |
288 | struct ad7298_state *st; | |
7abe9007 | 289 | struct iio_dev *indio_dev; |
2e334600 | 290 | int ret; |
7c31b984 | 291 | |
7abe9007 | 292 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); |
cc4a48e4 MH |
293 | if (indio_dev == NULL) |
294 | return -ENOMEM; | |
295 | ||
296 | st = iio_priv(indio_dev); | |
7c31b984 | 297 | |
2e334600 LPC |
298 | if (pdata && pdata->ext_ref) |
299 | st->ext_ref = AD7298_EXTREF; | |
300 | ||
301 | if (st->ext_ref) { | |
7abe9007 SK |
302 | st->reg = devm_regulator_get(&spi->dev, "vref"); |
303 | if (IS_ERR(st->reg)) | |
304 | return PTR_ERR(st->reg); | |
305 | ||
7c31b984 MH |
306 | ret = regulator_enable(st->reg); |
307 | if (ret) | |
7abe9007 | 308 | return ret; |
7c31b984 MH |
309 | } |
310 | ||
cc4a48e4 | 311 | spi_set_drvdata(spi, indio_dev); |
7c31b984 | 312 | |
7c31b984 MH |
313 | st->spi = spi; |
314 | ||
cc4a48e4 MH |
315 | indio_dev->name = spi_get_device_id(spi)->name; |
316 | indio_dev->dev.parent = &spi->dev; | |
b541eaff | 317 | indio_dev->dev.of_node = spi->dev.of_node; |
cc4a48e4 MH |
318 | indio_dev->modes = INDIO_DIRECT_MODE; |
319 | indio_dev->channels = ad7298_channels; | |
320 | indio_dev->num_channels = ARRAY_SIZE(ad7298_channels); | |
6fe8135f | 321 | indio_dev->info = &ad7298_info; |
7c31b984 MH |
322 | |
323 | /* Setup default message */ | |
324 | ||
325 | st->scan_single_xfer[0].tx_buf = &st->tx_buf[0]; | |
326 | st->scan_single_xfer[0].len = 2; | |
327 | st->scan_single_xfer[0].cs_change = 1; | |
328 | st->scan_single_xfer[1].tx_buf = &st->tx_buf[1]; | |
329 | st->scan_single_xfer[1].len = 2; | |
330 | st->scan_single_xfer[1].cs_change = 1; | |
331 | st->scan_single_xfer[2].rx_buf = &st->rx_buf[0]; | |
332 | st->scan_single_xfer[2].len = 2; | |
333 | ||
334 | spi_message_init(&st->scan_single_msg); | |
335 | spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg); | |
336 | spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg); | |
337 | spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg); | |
338 | ||
dc4871ad LPC |
339 | ret = iio_triggered_buffer_setup(indio_dev, NULL, |
340 | &ad7298_trigger_handler, NULL); | |
7c31b984 | 341 | if (ret) |
cc4a48e4 | 342 | goto error_disable_reg; |
7c31b984 | 343 | |
26d25ae3 JC |
344 | ret = iio_device_register(indio_dev); |
345 | if (ret) | |
d045b9d2 | 346 | goto error_cleanup_ring; |
cc4a48e4 | 347 | |
7c31b984 MH |
348 | return 0; |
349 | ||
350 | error_cleanup_ring: | |
dc4871ad | 351 | iio_triggered_buffer_cleanup(indio_dev); |
7c31b984 | 352 | error_disable_reg: |
2e334600 | 353 | if (st->ext_ref) |
7c31b984 | 354 | regulator_disable(st->reg); |
cc4a48e4 | 355 | |
7c31b984 MH |
356 | return ret; |
357 | } | |
358 | ||
fc52692c | 359 | static int ad7298_remove(struct spi_device *spi) |
7c31b984 | 360 | { |
cc4a48e4 MH |
361 | struct iio_dev *indio_dev = spi_get_drvdata(spi); |
362 | struct ad7298_state *st = iio_priv(indio_dev); | |
7c31b984 | 363 | |
d2fffd6c | 364 | iio_device_unregister(indio_dev); |
dc4871ad | 365 | iio_triggered_buffer_cleanup(indio_dev); |
7abe9007 | 366 | if (st->ext_ref) |
7c31b984 | 367 | regulator_disable(st->reg); |
cc4a48e4 | 368 | |
7c31b984 MH |
369 | return 0; |
370 | } | |
371 | ||
372 | static const struct spi_device_id ad7298_id[] = { | |
373 | {"ad7298", 0}, | |
374 | {} | |
375 | }; | |
55e4390c | 376 | MODULE_DEVICE_TABLE(spi, ad7298_id); |
7c31b984 MH |
377 | |
378 | static struct spi_driver ad7298_driver = { | |
379 | .driver = { | |
380 | .name = "ad7298", | |
7c31b984 MH |
381 | }, |
382 | .probe = ad7298_probe, | |
fc52692c | 383 | .remove = ad7298_remove, |
7c31b984 MH |
384 | .id_table = ad7298_id, |
385 | }; | |
ae6ae6fe | 386 | module_spi_driver(ad7298_driver); |
7c31b984 MH |
387 | |
388 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
389 | MODULE_DESCRIPTION("Analog Devices AD7298 ADC"); | |
390 | MODULE_LICENSE("GPL v2"); |