[mirror_ubuntu-hirsute-kernel.git] / drivers / iio / adc / ad7298.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * AD7298 SPI ADC driver
 *
 * Copyright 2011 Analog Devices Inc.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#define AD7298_WRITE	BIT(15) /* write to the control register */
#define AD7298_REPEAT	BIT(14) /* repeated conversion enable */
#define AD7298_CH(x)	BIT(13 - (x)) /* channel select */
#define AD7298_TSENSE	BIT(5) /* temperature conversion enable */
#define AD7298_EXTREF	BIT(2) /* external reference enable */
#define AD7298_TAVG	BIT(1) /* temperature sensor averaging enable */
#define AD7298_PDD	BIT(0) /* partial power down enable */

#define AD7298_MAX_CHAN		8
#define AD7298_INTREF_mV	2500

#define AD7298_CH_TEMP		9

struct ad7298_state {
	struct spi_device		*spi;
	struct regulator		*reg;
	unsigned			ext_ref;
	struct spi_transfer		ring_xfer[10];
	struct spi_transfer		scan_single_xfer[3];
	struct spi_message		ring_msg;
	struct spi_message		scan_single_msg;
	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 */
	__be16				rx_buf[12] ____cacheline_aligned;
	__be16				tx_buf[2];
};

#define AD7298_V_CHAN(index)						\
	{								\
		.type = IIO_VOLTAGE,					\
		.indexed = 1,						\
		.channel = index,					\
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
		.address = index,					\
		.scan_index = index,					\
		.scan_type = {						\
			.sign = 'u',					\
			.realbits = 12,					\
			.storagebits = 16,				\
			.endianness = IIO_BE,				\
		},							\
	}

static const struct iio_chan_spec ad7298_channels[] = {
	{
		.type = IIO_TEMP,
		.indexed = 1,
		.channel = 0,
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
			BIT(IIO_CHAN_INFO_SCALE) |
			BIT(IIO_CHAN_INFO_OFFSET),
		.address = AD7298_CH_TEMP,
		.scan_index = -1,
		.scan_type = {
			.sign = 's',
			.realbits = 32,
			.storagebits = 32,
		},
	},
	AD7298_V_CHAN(0),
	AD7298_V_CHAN(1),
	AD7298_V_CHAN(2),
	AD7298_V_CHAN(3),
	AD7298_V_CHAN(4),
	AD7298_V_CHAN(5),
	AD7298_V_CHAN(6),
	AD7298_V_CHAN(7),
	IIO_CHAN_SOFT_TIMESTAMP(8),
};

/*
 * ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
 */
static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
	const unsigned long *active_scan_mask)
{
	struct ad7298_state *st = iio_priv(indio_dev);
	int i, m;
	unsigned short command;
	int scan_count;

	/* Now compute overall size */
	scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);

	command = AD7298_WRITE | st->ext_ref;

	for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
		if (test_bit(i, active_scan_mask))
			command |= m;

	st->tx_buf[0] = cpu_to_be16(command);

	/* build spi ring message */
	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
	st->ring_xfer[0].len = 2;
	st->ring_xfer[0].cs_change = 1;
	st->ring_xfer[1].tx_buf = &st->tx_buf[1];
	st->ring_xfer[1].len = 2;
	st->ring_xfer[1].cs_change = 1;

	spi_message_init(&st->ring_msg);
	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
	spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);

	for (i = 0; i < scan_count; i++) {
		st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
		st->ring_xfer[i + 2].len = 2;
		st->ring_xfer[i + 2].cs_change = 1;
		spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
	}
	/* make sure last transfer cs_change is not set */
	st->ring_xfer[i + 1].cs_change = 0;

	return 0;
}

/*
 * ad7298_trigger_handler() bh of trigger launched polling to ring buffer
 *
 * Currently there is no option in this driver to disable the saving of
 * timestamps within the ring.
 */
static irqreturn_t ad7298_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ad7298_state *st = iio_priv(indio_dev);
	int b_sent;

	b_sent = spi_sync(st->spi, &st->ring_msg);
	if (b_sent)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
		iio_get_time_ns(indio_dev));

done:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
{
	int ret;
	st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref |
				   (AD7298_CH(0) >> ch));

	ret = spi_sync(st->spi, &st->scan_single_msg);
	if (ret)
		return ret;

	return be16_to_cpu(st->rx_buf[0]);
}

static int ad7298_scan_temp(struct ad7298_state *st, int *val)
{
	int ret;
	__be16 buf;

	buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
			  AD7298_TAVG | st->ext_ref);

	ret = spi_write(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	buf = cpu_to_be16(0);

	ret = spi_write(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	usleep_range(101, 1000); /* sleep > 100us */

	ret = spi_read(st->spi, (u8 *)&buf, 2);
	if (ret)
		return ret;

	*val = sign_extend32(be16_to_cpu(buf), 11);

	return 0;
}

static int ad7298_get_ref_voltage(struct ad7298_state *st)
{
	int vref;

	if (st->reg) {
		vref = regulator_get_voltage(st->reg);
		if (vref < 0)
			return vref;

		return vref / 1000;
	} else {
		return AD7298_INTREF_mV;
	}
}

static int ad7298_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	int ret;
	struct ad7298_state *st = iio_priv(indio_dev);

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		ret = iio_device_claim_direct_mode(indio_dev);
		if (ret)
			return ret;

		if (chan->address == AD7298_CH_TEMP)
			ret = ad7298_scan_temp(st, val);
		else
			ret = ad7298_scan_direct(st, chan->address);

		iio_device_release_direct_mode(indio_dev);

		if (ret < 0)
			return ret;

		if (chan->address != AD7298_CH_TEMP)
			*val = ret & GENMASK(chan->scan_type.realbits - 1, 0);

		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		switch (chan->type) {
		case IIO_VOLTAGE:
			*val = ad7298_get_ref_voltage(st);
			*val2 = chan->scan_type.realbits;
			return IIO_VAL_FRACTIONAL_LOG2;
		case IIO_TEMP:
			*val = ad7298_get_ref_voltage(st);
			*val2 = 10;
			return IIO_VAL_FRACTIONAL;
		default:
			return -EINVAL;
		}
	case IIO_CHAN_INFO_OFFSET:
		*val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
		return IIO_VAL_INT;
	}
	return -EINVAL;
}

static const struct iio_info ad7298_info = {
	.read_raw = &ad7298_read_raw,
	.update_scan_mode = ad7298_update_scan_mode,
};

static void ad7298_reg_disable(void *data)
{
	struct regulator *reg = data;

	regulator_disable(reg);
}

static int ad7298_probe(struct spi_device *spi)
{
	struct ad7298_state *st;
	struct iio_dev *indio_dev;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (indio_dev == NULL)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	st->reg = devm_regulator_get_optional(&spi->dev, "vref");
	if (!IS_ERR(st->reg)) {
		st->ext_ref = AD7298_EXTREF;
	} else {
		ret = PTR_ERR(st->reg);
		if (ret != -ENODEV)
			return ret;

		st->reg = NULL;
	}

	if (st->reg) {
		ret = regulator_enable(st->reg);
		if (ret)
			return ret;

		ret = devm_add_action_or_reset(&spi->dev, ad7298_reg_disable,
					       st->reg);
		if (ret)
			return ret;
	}

	st->spi = spi;

	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = ad7298_channels;
	indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
	indio_dev->info = &ad7298_info;

	/* Setup default message */

	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
	st->scan_single_xfer[0].len = 2;
	st->scan_single_xfer[0].cs_change = 1;
	st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
	st->scan_single_xfer[1].len = 2;
	st->scan_single_xfer[1].cs_change = 1;
	st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
	st->scan_single_xfer[2].len = 2;

	spi_message_init(&st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);

	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
			&ad7298_trigger_handler, NULL);
	if (ret)
		return ret;

	return devm_iio_device_register(&spi->dev, indio_dev);
}

static const struct spi_device_id ad7298_id[] = {
	{"ad7298", 0},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7298_id);

static struct spi_driver ad7298_driver = {
	.driver = {
		.name	= "ad7298",
	},
	.probe		= ad7298_probe,
	.id_table	= ad7298_id,
};
module_spi_driver(ad7298_driver);

MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fda8d26e	1	// SPDX-License-Identifier: GPL-2.0-only
7c31b984 MH	2	/*
	3	* AD7298 SPI ADC driver
	4	*
	5	* Copyright 2011 Analog Devices Inc.
7c31b984 MH	6	*/
7c31b984 MH	7
7c31b984 MH	8	#include <linux/device.h>
	9	#include <linux/kernel.h>
	10	#include <linux/slab.h>
	11	#include <linux/sysfs.h>
	12	#include <linux/spi/spi.h>
	13	#include <linux/regulator/consumer.h>
	14	#include <linux/err.h>
	15	#include <linux/delay.h>
99c97852	16	#include <linux/module.h>
dc4871ad	17	#include <linux/interrupt.h>
48898053	18	#include <linux/bitops.h>
7c31b984	19
06458e27 JC	20	#include <linux/iio/iio.h>
	21	#include <linux/iio/sysfs.h>
	22	#include <linux/iio/buffer.h>
dc4871ad LPC	23	#include <linux/iio/trigger_consumer.h>
dc4871ad LPC	24	#include <linux/iio/triggered_buffer.h>
7c31b984	25
48898053 PM	26	#define AD7298_WRITE BIT(15) /* write to the control register */
	27	#define AD7298_REPEAT BIT(14) /* repeated conversion enable */
	28	#define AD7298_CH(x) BIT(13 - (x)) /* channel select */
	29	#define AD7298_TSENSE BIT(5) /* temperature conversion enable */
	30	#define AD7298_EXTREF BIT(2) /* external reference enable */
	31	#define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
	32	#define AD7298_PDD BIT(0) /* partial power down enable */
dc4871ad LPC	33
dc4871ad LPC	34	#define AD7298_MAX_CHAN 8
dc4871ad LPC	35	#define AD7298_INTREF_mV 2500
	36
	37	#define AD7298_CH_TEMP 9
	38
dc4871ad LPC	39	struct ad7298_state {
	40	struct spi_device *spi;
	41	struct regulator *reg;
	42	unsigned ext_ref;
	43	struct spi_transfer ring_xfer[10];
	44	struct spi_transfer scan_single_xfer[3];
	45	struct spi_message ring_msg;
	46	struct spi_message scan_single_msg;
	47	/*
	48	* DMA (thus cache coherency maintenance) requires the
	49	* transfer buffers to live in their own cache lines.
	50	*/
be7fd3b8 JC	51	__be16 rx_buf[12] ____cacheline_aligned;
be7fd3b8 JC	52	__be16 tx_buf[2];
dc4871ad LPC	53	};
dc4871ad LPC	54
95e48f77 JC	55	#define AD7298_V_CHAN(index) \
	56	{ \
	57	.type = IIO_VOLTAGE, \
	58	.indexed = 1, \
	59	.channel = index, \
40dd676d JC	60	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
40dd676d JC	61	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
95e48f77 JC	62	.address = index, \
	63	.scan_index = index, \
	64	.scan_type = { \
	65	.sign = 'u', \
	66	.realbits = 12, \
	67	.storagebits = 16, \
ca654638	68	.endianness = IIO_BE, \
95e48f77 JC	69	}, \
	70	}
	71
f4e4b955	72	static const struct iio_chan_spec ad7298_channels[] = {
95e48f77 JC	73	{
	74	.type = IIO_TEMP,
	75	.indexed = 1,
	76	.channel = 0,
40dd676d JC	77	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \|
	78	BIT(IIO_CHAN_INFO_SCALE) \|
	79	BIT(IIO_CHAN_INFO_OFFSET),
d045b9d2 LPC	80	.address = AD7298_CH_TEMP,
d045b9d2 LPC	81	.scan_index = -1,
95e48f77 JC	82	.scan_type = {
	83	.sign = 's',
	84	.realbits = 32,
	85	.storagebits = 32,
	86	},
	87	},
	88	AD7298_V_CHAN(0),
	89	AD7298_V_CHAN(1),
	90	AD7298_V_CHAN(2),
	91	AD7298_V_CHAN(3),
	92	AD7298_V_CHAN(4),
	93	AD7298_V_CHAN(5),
	94	AD7298_V_CHAN(6),
	95	AD7298_V_CHAN(7),
01a99e18 MH	96	IIO_CHAN_SOFT_TIMESTAMP(8),
	97	};
	98
b5d214de	99	/*
dc4871ad	100	* ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
b5d214de	101	*/
dc4871ad LPC	102	static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
	103	const unsigned long *active_scan_mask)
	104	{
	105	struct ad7298_state *st = iio_priv(indio_dev);
	106	int i, m;
	107	unsigned short command;
	108	int scan_count;
	109
	110	/* Now compute overall size */
	111	scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);
	112
	113	command = AD7298_WRITE \| st->ext_ref;
	114
	115	for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
	116	if (test_bit(i, active_scan_mask))
	117	command \|= m;
	118
	119	st->tx_buf[0] = cpu_to_be16(command);
	120
	121	/* build spi ring message */
	122	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
	123	st->ring_xfer[0].len = 2;
	124	st->ring_xfer[0].cs_change = 1;
	125	st->ring_xfer[1].tx_buf = &st->tx_buf[1];
	126	st->ring_xfer[1].len = 2;
	127	st->ring_xfer[1].cs_change = 1;
	128
	129	spi_message_init(&st->ring_msg);
	130	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
	131	spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
	132
	133	for (i = 0; i < scan_count; i++) {
	134	st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
	135	st->ring_xfer[i + 2].len = 2;
	136	st->ring_xfer[i + 2].cs_change = 1;
	137	spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
	138	}
	139	/* make sure last transfer cs_change is not set */
	140	st->ring_xfer[i + 1].cs_change = 0;
	141
	142	return 0;
	143	}
	144
b5d214de	145	/*
dc4871ad LPC	146	* ad7298_trigger_handler() bh of trigger launched polling to ring buffer
	147	*
	148	* Currently there is no option in this driver to disable the saving of
	149	* timestamps within the ring.
b5d214de	150	*/
dc4871ad LPC	151	static irqreturn_t ad7298_trigger_handler(int irq, void *p)
	152	{
	153	struct iio_poll_func *pf = p;
	154	struct iio_dev *indio_dev = pf->indio_dev;
	155	struct ad7298_state *st = iio_priv(indio_dev);
dc4871ad LPC	156	int b_sent;
	157
	158	b_sent = spi_sync(st->spi, &st->ring_msg);
	159	if (b_sent)
	160	goto done;
	161
85ec2372	162	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
bc2b7dab	163	iio_get_time_ns(indio_dev));
dc4871ad LPC	164
	165	done:
	166	iio_trigger_notify_done(indio_dev->trig);
	167
	168	return IRQ_HANDLED;
	169	}
	170
7c31b984 MH	171	static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
	172	{
	173	int ret;
	174	st->tx_buf[0] = cpu_to_be16(AD7298_WRITE \| st->ext_ref \|
	175	(AD7298_CH(0) >> ch));
	176
	177	ret = spi_sync(st->spi, &st->scan_single_msg);
	178	if (ret)
	179	return ret;
	180
	181	return be16_to_cpu(st->rx_buf[0]);
	182	}
	183
01a99e18	184	static int ad7298_scan_temp(struct ad7298_state st, int val)
7c31b984	185	{
01a10e04	186	int ret;
c1a75288	187	__be16 buf;
7c31b984	188
c1a75288	189	buf = cpu_to_be16(AD7298_WRITE \| AD7298_TSENSE \|
01a99e18	190	AD7298_TAVG \| st->ext_ref);
7c31b984	191
c1a75288	192	ret = spi_write(st->spi, (u8 *)&buf, 2);
01a99e18	193	if (ret)
7c31b984 MH	194	return ret;
7c31b984 MH	195
c1a75288	196	buf = cpu_to_be16(0);
7c31b984	197
c1a75288	198	ret = spi_write(st->spi, (u8 *)&buf, 2);
01a99e18 MH	199	if (ret)
01a99e18 MH	200	return ret;
7c31b984	201
7c31b984	202	usleep_range(101, 1000); /* sleep > 100us */
01a99e18	203
c1a75288	204	ret = spi_read(st->spi, (u8 *)&buf, 2);
01a99e18 MH	205	if (ret)
01a99e18 MH	206	return ret;
7c31b984	207
01a10e04	208	*val = sign_extend32(be16_to_cpu(buf), 11);
7c31b984	209
01a10e04 LPC	210	return 0;
	211	}
	212
	213	static int ad7298_get_ref_voltage(struct ad7298_state *st)
	214	{
	215	int vref;
7c31b984	216
53c6b0d5	217	if (st->reg) {
01a10e04 LPC	218	vref = regulator_get_voltage(st->reg);
	219	if (vref < 0)
	220	return vref;
7c31b984	221
01a10e04	222	return vref / 1000;
7c31b984	223	} else {
01a10e04	224	return AD7298_INTREF_mV;
7c31b984	225	}
01a99e18	226	}
7c31b984	227
84f79ecb	228	static int ad7298_read_raw(struct iio_dev *indio_dev,
01a99e18 MH	229	struct iio_chan_spec const *chan,
	230	int *val,
	231	int *val2,
	232	long m)
7c31b984	233	{
01a99e18	234	int ret;
84f79ecb	235	struct ad7298_state *st = iio_priv(indio_dev);
01a99e18 MH	236
01a99e18 MH	237	switch (m) {
b11f98ff	238	case IIO_CHAN_INFO_RAW:
d02ec00d AS	239	ret = iio_device_claim_direct_mode(indio_dev);
	240	if (ret)
	241	return ret;
	242
	243	if (chan->address == AD7298_CH_TEMP)
	244	ret = ad7298_scan_temp(st, val);
	245	else
	246	ret = ad7298_scan_direct(st, chan->address);
	247
	248	iio_device_release_direct_mode(indio_dev);
01a99e18 MH	249
	250	if (ret < 0)
	251	return ret;
	252
	253	if (chan->address != AD7298_CH_TEMP)
48898053	254	*val = ret & GENMASK(chan->scan_type.realbits - 1, 0);
01a99e18 MH	255
01a99e18 MH	256	return IIO_VAL_INT;
c8a9f805 JC	257	case IIO_CHAN_INFO_SCALE:
	258	switch (chan->type) {
	259	case IIO_VOLTAGE:
01a10e04	260	*val = ad7298_get_ref_voltage(st);
2e334600 LPC	261	*val2 = chan->scan_type.realbits;
2e334600 LPC	262	return IIO_VAL_FRACTIONAL_LOG2;
c8a9f805	263	case IIO_TEMP:
01a10e04 LPC	264	*val = ad7298_get_ref_voltage(st);
	265	*val2 = 10;
	266	return IIO_VAL_FRACTIONAL;
c8a9f805 JC	267	default:
	268	return -EINVAL;
	269	}
01a10e04 LPC	270	case IIO_CHAN_INFO_OFFSET:
	271	*val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
	272	return IIO_VAL_INT;
01a99e18 MH	273	}
01a99e18 MH	274	return -EINVAL;
7c31b984	275	}
7c31b984	276
6fe8135f JC	277	static const struct iio_info ad7298_info = {
6fe8135f JC	278	.read_raw = &ad7298_read_raw,
d045b9d2	279	.update_scan_mode = ad7298_update_scan_mode,
6fe8135f JC	280	};
6fe8135f JC	281
b6a3f832 AA	282	static void ad7298_reg_disable(void *data)
	283	{
	284	struct regulator *reg = data;
	285
	286	regulator_disable(reg);
	287	}
	288
fc52692c	289	static int ad7298_probe(struct spi_device *spi)
7c31b984	290	{
7c31b984	291	struct ad7298_state *st;
7abe9007	292	struct iio_dev *indio_dev;
2e334600	293	int ret;
7c31b984	294
7abe9007	295	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
cc4a48e4 MH	296	if (indio_dev == NULL)
	297	return -ENOMEM;
	298
	299	st = iio_priv(indio_dev);
7c31b984	300
28963f2f AA	301	st->reg = devm_regulator_get_optional(&spi->dev, "vref");
28963f2f AA	302	if (!IS_ERR(st->reg)) {
2e334600	303	st->ext_ref = AD7298_EXTREF;
28963f2f AA	304	} else {
	305	ret = PTR_ERR(st->reg);
	306	if (ret != -ENODEV)
	307	return ret;
2e334600	308
28963f2f AA	309	st->reg = NULL;
28963f2f AA	310	}
7abe9007	311
28963f2f	312	if (st->reg) {
7c31b984 MH	313	ret = regulator_enable(st->reg);
7c31b984 MH	314	if (ret)
7abe9007	315	return ret;
7c31b984	316
b6a3f832 AA	317	ret = devm_add_action_or_reset(&spi->dev, ad7298_reg_disable,
	318	st->reg);
	319	if (ret)
	320	return ret;
	321	}
7c31b984	322
7c31b984 MH	323	st->spi = spi;
7c31b984 MH	324
cc4a48e4	325	indio_dev->name = spi_get_device_id(spi)->name;
cc4a48e4 MH	326	indio_dev->modes = INDIO_DIRECT_MODE;
	327	indio_dev->channels = ad7298_channels;
	328	indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
6fe8135f	329	indio_dev->info = &ad7298_info;
7c31b984 MH	330
	331	/* Setup default message */
	332
	333	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
	334	st->scan_single_xfer[0].len = 2;
	335	st->scan_single_xfer[0].cs_change = 1;
	336	st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
	337	st->scan_single_xfer[1].len = 2;
	338	st->scan_single_xfer[1].cs_change = 1;
	339	st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
	340	st->scan_single_xfer[2].len = 2;
	341
	342	spi_message_init(&st->scan_single_msg);
	343	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
	344	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
	345	spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);
	346
b6a3f832	347	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
dc4871ad	348	&ad7298_trigger_handler, NULL);
7c31b984	349	if (ret)
b6a3f832	350	return ret;
cc4a48e4	351
b6a3f832	352	return devm_iio_device_register(&spi->dev, indio_dev);
7c31b984 MH	353	}
	354
	355	static const struct spi_device_id ad7298_id[] = {
	356	{"ad7298", 0},
	357	{}
	358	};
55e4390c	359	MODULE_DEVICE_TABLE(spi, ad7298_id);
7c31b984 MH	360
	361	static struct spi_driver ad7298_driver = {
	362	.driver = {
	363	.name = "ad7298",
7c31b984 MH	364	},
7c31b984 MH	365	.probe = ad7298_probe,
7c31b984 MH	366	.id_table = ad7298_id,
7c31b984 MH	367	};
ae6ae6fe	368	module_spi_driver(ad7298_driver);
7c31b984	369
9920ed25	370	MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
7c31b984 MH	371	MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
7c31b984 MH	372	MODULE_LICENSE("GPL v2");