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CommitLineData
985dbe77
MH
1/*
2 * iio/adc/ad799x.c
630097f7 3 * Copyright (C) 2010-2011 Michael Hennerich, Analog Devices Inc.
985dbe77
MH
4 *
5 * based on iio/adc/max1363
6 * Copyright (C) 2008-2010 Jonathan Cameron
7 *
8 * based on linux/drivers/i2c/chips/max123x
9 * Copyright (C) 2002-2004 Stefan Eletzhofer
10 *
11 * based on linux/drivers/acron/char/pcf8583.c
12 * Copyright (C) 2000 Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 * ad799x.c
19 *
20 * Support for ad7991, ad7995, ad7999, ad7992, ad7993, ad7994, ad7997,
21 * ad7998 and similar chips.
22 *
23 */
24
25#include <linux/interrupt.h>
985dbe77
MH
26#include <linux/device.h>
27#include <linux/kernel.h>
28#include <linux/sysfs.h>
985dbe77
MH
29#include <linux/i2c.h>
30#include <linux/regulator/consumer.h>
31#include <linux/slab.h>
32#include <linux/types.h>
33#include <linux/err.h>
99c97852 34#include <linux/module.h>
e1c6e2a2 35#include <linux/bitops.h>
985dbe77 36
06458e27
JC
37#include <linux/iio/iio.h>
38#include <linux/iio/sysfs.h>
39#include <linux/iio/events.h>
40#include <linux/iio/buffer.h>
396590b3
LPC
41#include <linux/iio/trigger_consumer.h>
42#include <linux/iio/triggered_buffer.h>
cdf38709 43
396590b3 44#define AD799X_CHANNEL_SHIFT 4
e1c6e2a2 45
396590b3
LPC
46/*
47 * AD7991, AD7995 and AD7999 defines
48 */
49
50#define AD7991_REF_SEL 0x08
51#define AD7991_FLTR 0x04
52#define AD7991_BIT_TRIAL_DELAY 0x02
53#define AD7991_SAMPLE_DELAY 0x01
54
55/*
56 * AD7992, AD7993, AD7994, AD7997 and AD7998 defines
57 */
58
e1c6e2a2
PM
59#define AD7998_FLTR BIT(3)
60#define AD7998_ALERT_EN BIT(2)
61#define AD7998_BUSY_ALERT BIT(1)
62#define AD7998_BUSY_ALERT_POL BIT(0)
396590b3
LPC
63
64#define AD7998_CONV_RES_REG 0x0
65#define AD7998_ALERT_STAT_REG 0x1
66#define AD7998_CONF_REG 0x2
67#define AD7998_CYCLE_TMR_REG 0x3
68
69#define AD7998_DATALOW_REG(x) ((x) * 3 + 0x4)
70#define AD7998_DATAHIGH_REG(x) ((x) * 3 + 0x5)
71#define AD7998_HYST_REG(x) ((x) * 3 + 0x6)
72
e1c6e2a2 73#define AD7998_CYC_MASK GENMASK(2, 0)
396590b3
LPC
74#define AD7998_CYC_DIS 0x0
75#define AD7998_CYC_TCONF_32 0x1
76#define AD7998_CYC_TCONF_64 0x2
77#define AD7998_CYC_TCONF_128 0x3
78#define AD7998_CYC_TCONF_256 0x4
79#define AD7998_CYC_TCONF_512 0x5
80#define AD7998_CYC_TCONF_1024 0x6
81#define AD7998_CYC_TCONF_2048 0x7
82
83#define AD7998_ALERT_STAT_CLEAR 0xFF
84
85/*
86 * AD7997 and AD7997 defines
87 */
88
e1c6e2a2
PM
89#define AD7997_8_READ_SINGLE BIT(7)
90#define AD7997_8_READ_SEQUENCE (BIT(6) | BIT(5) | BIT(4))
396590b3
LPC
91
92enum {
93 ad7991,
94 ad7995,
95 ad7999,
96 ad7992,
97 ad7993,
98 ad7994,
99 ad7997,
100 ad7998
101};
102
103/**
91556c69 104 * struct ad799x_chip_config - chip specific information
396590b3 105 * @channel: channel specification
396590b3 106 * @default_config: device default configuration
a3eeb159 107 * @info: pointer to iio_info struct
396590b3 108 */
91556c69 109struct ad799x_chip_config {
ef0bf6f8 110 const struct iio_chan_spec channel[9];
396590b3
LPC
111 u16 default_config;
112 const struct iio_info *info;
113};
114
91556c69
PM
115/**
116 * struct ad799x_chip_info - chip specific information
117 * @num_channels: number of channels
118 * @noirq_config: device configuration w/o IRQ
119 * @irq_config: device configuration w/IRQ
120 */
121struct ad799x_chip_info {
122 int num_channels;
123 const struct ad799x_chip_config noirq_config;
124 const struct ad799x_chip_config irq_config;
125};
126
396590b3
LPC
127struct ad799x_state {
128 struct i2c_client *client;
91556c69 129 const struct ad799x_chip_config *chip_config;
396590b3
LPC
130 struct regulator *reg;
131 struct regulator *vref;
132 unsigned id;
133 u16 config;
134
135 u8 *rx_buf;
136 unsigned int transfer_size;
137};
138
89ca79af
PM
139static int ad799x_write_config(struct ad799x_state *st, u16 val)
140{
141 switch (st->id) {
142 case ad7997:
143 case ad7998:
144 return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG,
145 val);
2eacc608
LPC
146 case ad7992:
147 case ad7993:
148 case ad7994:
89ca79af
PM
149 return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG,
150 val);
2eacc608
LPC
151 default:
152 /* Will be written when doing a conversion */
153 st->config = val;
154 return 0;
89ca79af
PM
155 }
156}
157
158static int ad799x_read_config(struct ad799x_state *st)
159{
160 switch (st->id) {
161 case ad7997:
162 case ad7998:
163 return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG);
2eacc608
LPC
164 case ad7992:
165 case ad7993:
166 case ad7994:
89ca79af 167 return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG);
2eacc608
LPC
168 default:
169 /* No readback support */
170 return st->config;
89ca79af
PM
171 }
172}
173
396590b3
LPC
174/**
175 * ad799x_trigger_handler() bh of trigger launched polling to ring buffer
176 *
177 * Currently there is no option in this driver to disable the saving of
178 * timestamps within the ring.
179 **/
180static irqreturn_t ad799x_trigger_handler(int irq, void *p)
181{
182 struct iio_poll_func *pf = p;
183 struct iio_dev *indio_dev = pf->indio_dev;
184 struct ad799x_state *st = iio_priv(indio_dev);
185 int b_sent;
186 u8 cmd;
187
188 switch (st->id) {
189 case ad7991:
190 case ad7995:
191 case ad7999:
192 cmd = st->config |
193 (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT);
194 break;
195 case ad7992:
196 case ad7993:
197 case ad7994:
198 cmd = (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT) |
199 AD7998_CONV_RES_REG;
200 break;
201 case ad7997:
202 case ad7998:
203 cmd = AD7997_8_READ_SEQUENCE | AD7998_CONV_RES_REG;
204 break;
205 default:
206 cmd = 0;
207 }
208
209 b_sent = i2c_smbus_read_i2c_block_data(st->client,
210 cmd, st->transfer_size, st->rx_buf);
211 if (b_sent < 0)
212 goto out;
213
214 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
bc2b7dab 215 iio_get_time_ns(indio_dev));
396590b3
LPC
216out:
217 iio_trigger_notify_done(indio_dev->trig);
218
219 return IRQ_HANDLED;
220}
985dbe77 221
8235841b 222static int ad799x_update_scan_mode(struct iio_dev *indio_dev,
ae3805c3 223 const unsigned long *scan_mask)
985dbe77 224{
ae3805c3
LPC
225 struct ad799x_state *st = iio_priv(indio_dev);
226
d8dca330
LPC
227 kfree(st->rx_buf);
228 st->rx_buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
229 if (!st->rx_buf)
230 return -ENOMEM;
231
232 st->transfer_size = bitmap_weight(scan_mask, indio_dev->masklength) * 2;
233
ae3805c3 234 switch (st->id) {
8235841b
PM
235 case ad7992:
236 case ad7993:
237 case ad7994:
ae3805c3
LPC
238 case ad7997:
239 case ad7998:
8235841b
PM
240 st->config &= ~(GENMASK(7, 0) << AD799X_CHANNEL_SHIFT);
241 st->config |= (*scan_mask << AD799X_CHANNEL_SHIFT);
242 return ad799x_write_config(st, st->config);
ae3805c3 243 default:
bd3bd432 244 return 0;
ae3805c3 245 }
985dbe77
MH
246}
247
d22fd9c5 248static int ad799x_scan_direct(struct ad799x_state *st, unsigned ch)
985dbe77 249{
d22fd9c5 250 u8 cmd;
985dbe77 251
d22fd9c5
MH
252 switch (st->id) {
253 case ad7991:
254 case ad7995:
255 case ad7999:
e1c6e2a2 256 cmd = st->config | (BIT(ch) << AD799X_CHANNEL_SHIFT);
d22fd9c5
MH
257 break;
258 case ad7992:
259 case ad7993:
260 case ad7994:
e1c6e2a2 261 cmd = BIT(ch) << AD799X_CHANNEL_SHIFT;
d22fd9c5
MH
262 break;
263 case ad7997:
264 case ad7998:
265 cmd = (ch << AD799X_CHANNEL_SHIFT) | AD7997_8_READ_SINGLE;
266 break;
267 default:
268 return -EINVAL;
985dbe77
MH
269 }
270
54154471 271 return i2c_smbus_read_word_swapped(st->client, cmd);
985dbe77
MH
272}
273
84f79ecb 274static int ad799x_read_raw(struct iio_dev *indio_dev,
d22fd9c5
MH
275 struct iio_chan_spec const *chan,
276 int *val,
277 int *val2,
278 long m)
985dbe77 279{
d22fd9c5 280 int ret;
84f79ecb 281 struct ad799x_state *st = iio_priv(indio_dev);
d22fd9c5
MH
282
283 switch (m) {
b11f98ff 284 case IIO_CHAN_INFO_RAW:
1bb86ecb
AS
285 ret = iio_device_claim_direct_mode(indio_dev);
286 if (ret)
287 return ret;
288 ret = ad799x_scan_direct(st, chan->scan_index);
289 iio_device_release_direct_mode(indio_dev);
985dbe77 290
985dbe77 291 if (ret < 0)
d22fd9c5 292 return ret;
5357ba3d 293 *val = (ret >> chan->scan_type.shift) &
e1c6e2a2 294 GENMASK(chan->scan_type.realbits - 1, 0);
d22fd9c5 295 return IIO_VAL_INT;
c8a9f805 296 case IIO_CHAN_INFO_SCALE:
2deaf23b
HK
297 ret = regulator_get_voltage(st->vref);
298 if (ret < 0)
299 return ret;
300 *val = ret / 1000;
b740f48a
LPC
301 *val2 = chan->scan_type.realbits;
302 return IIO_VAL_FRACTIONAL_LOG2;
985dbe77 303 }
d22fd9c5 304 return -EINVAL;
985dbe77 305}
24cba406
JC
306static const unsigned int ad7998_frequencies[] = {
307 [AD7998_CYC_DIS] = 0,
308 [AD7998_CYC_TCONF_32] = 15625,
309 [AD7998_CYC_TCONF_64] = 7812,
310 [AD7998_CYC_TCONF_128] = 3906,
311 [AD7998_CYC_TCONF_512] = 976,
312 [AD7998_CYC_TCONF_1024] = 488,
313 [AD7998_CYC_TCONF_2048] = 244,
314};
54154471 315
985dbe77
MH
316static ssize_t ad799x_read_frequency(struct device *dev,
317 struct device_attribute *attr,
318 char *buf)
319{
62c51839 320 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
84f79ecb 321 struct ad799x_state *st = iio_priv(indio_dev);
985dbe77 322
54154471
PM
323 int ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG);
324 if (ret < 0)
985dbe77
MH
325 return ret;
326
54154471 327 return sprintf(buf, "%u\n", ad7998_frequencies[ret & AD7998_CYC_MASK]);
985dbe77
MH
328}
329
330static ssize_t ad799x_write_frequency(struct device *dev,
331 struct device_attribute *attr,
332 const char *buf,
333 size_t len)
334{
62c51839 335 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
84f79ecb 336 struct ad799x_state *st = iio_priv(indio_dev);
985dbe77
MH
337
338 long val;
24cba406 339 int ret, i;
985dbe77 340
f86f8362 341 ret = kstrtol(buf, 10, &val);
985dbe77
MH
342 if (ret)
343 return ret;
344
84f79ecb 345 mutex_lock(&indio_dev->mlock);
54154471
PM
346 ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG);
347 if (ret < 0)
985dbe77
MH
348 goto error_ret_mutex;
349 /* Wipe the bits clean */
54154471 350 ret &= ~AD7998_CYC_MASK;
985dbe77 351
24cba406
JC
352 for (i = 0; i < ARRAY_SIZE(ad7998_frequencies); i++)
353 if (val == ad7998_frequencies[i])
354 break;
355 if (i == ARRAY_SIZE(ad7998_frequencies)) {
985dbe77
MH
356 ret = -EINVAL;
357 goto error_ret_mutex;
358 }
54154471
PM
359
360 ret = i2c_smbus_write_byte_data(st->client, AD7998_CYCLE_TMR_REG,
361 ret | i);
362 if (ret < 0)
363 goto error_ret_mutex;
364 ret = len;
985dbe77
MH
365
366error_ret_mutex:
84f79ecb 367 mutex_unlock(&indio_dev->mlock);
985dbe77 368
54154471 369 return ret;
985dbe77
MH
370}
371
84f79ecb 372static int ad799x_read_event_config(struct iio_dev *indio_dev,
5b9e048a
LPC
373 const struct iio_chan_spec *chan,
374 enum iio_event_type type,
375 enum iio_event_direction dir)
231c5c3b 376{
1d15330a
PM
377 struct ad799x_state *st = iio_priv(indio_dev);
378
379 if (!(st->config & AD7998_ALERT_EN))
380 return 0;
381
382 if ((st->config >> AD799X_CHANNEL_SHIFT) & BIT(chan->scan_index))
383 return 1;
384
385 return 0;
231c5c3b
JC
386}
387
3008d082
PM
388static int ad799x_write_event_config(struct iio_dev *indio_dev,
389 const struct iio_chan_spec *chan,
390 enum iio_event_type type,
391 enum iio_event_direction dir,
392 int state)
393{
394 struct ad799x_state *st = iio_priv(indio_dev);
395 int ret;
396
1bb86ecb
AS
397 ret = iio_device_claim_direct_mode(indio_dev);
398 if (ret)
399 return ret;
3008d082
PM
400
401 if (state)
402 st->config |= BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT;
403 else
404 st->config &= ~(BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT);
405
406 if (st->config >> AD799X_CHANNEL_SHIFT)
407 st->config |= AD7998_ALERT_EN;
408 else
409 st->config &= ~AD7998_ALERT_EN;
410
411 ret = ad799x_write_config(st, st->config);
1bb86ecb 412 iio_device_release_direct_mode(indio_dev);
3008d082
PM
413 return ret;
414}
415
ba1d7961
LPC
416static unsigned int ad799x_threshold_reg(const struct iio_chan_spec *chan,
417 enum iio_event_direction dir,
418 enum iio_event_info info)
69582b88 419{
ba1d7961
LPC
420 switch (info) {
421 case IIO_EV_INFO_VALUE:
422 if (dir == IIO_EV_DIR_FALLING)
423 return AD7998_DATALOW_REG(chan->channel);
424 else
425 return AD7998_DATAHIGH_REG(chan->channel);
426 case IIO_EV_INFO_HYSTERESIS:
427 return AD7998_HYST_REG(chan->channel);
428 default:
429 return -EINVAL;
430 }
431
432 return 0;
69582b88 433}
231c5c3b
JC
434
435static int ad799x_write_event_value(struct iio_dev *indio_dev,
5b9e048a
LPC
436 const struct iio_chan_spec *chan,
437 enum iio_event_type type,
438 enum iio_event_direction dir,
439 enum iio_event_info info,
440 int val, int val2)
231c5c3b
JC
441{
442 int ret;
443 struct ad799x_state *st = iio_priv(indio_dev);
231c5c3b 444
e1c6e2a2 445 if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
361d7950
PM
446 return -EINVAL;
447
231c5c3b 448 mutex_lock(&indio_dev->mlock);
54154471
PM
449 ret = i2c_smbus_write_word_swapped(st->client,
450 ad799x_threshold_reg(chan, dir, info),
361d7950 451 val << chan->scan_type.shift);
231c5c3b
JC
452 mutex_unlock(&indio_dev->mlock);
453
454 return ret;
455}
456
457static int ad799x_read_event_value(struct iio_dev *indio_dev,
5b9e048a
LPC
458 const struct iio_chan_spec *chan,
459 enum iio_event_type type,
460 enum iio_event_direction dir,
461 enum iio_event_info info,
462 int *val, int *val2)
231c5c3b
JC
463{
464 int ret;
465 struct ad799x_state *st = iio_priv(indio_dev);
231c5c3b
JC
466
467 mutex_lock(&indio_dev->mlock);
54154471
PM
468 ret = i2c_smbus_read_word_swapped(st->client,
469 ad799x_threshold_reg(chan, dir, info));
231c5c3b
JC
470 mutex_unlock(&indio_dev->mlock);
471 if (ret < 0)
472 return ret;
54154471 473 *val = (ret >> chan->scan_type.shift) &
102447ad 474 GENMASK(chan->scan_type.realbits - 1, 0);
231c5c3b 475
5b9e048a 476 return IIO_VAL_INT;
231c5c3b
JC
477}
478
72148f6e 479static irqreturn_t ad799x_event_handler(int irq, void *private)
985dbe77 480{
72148f6e 481 struct iio_dev *indio_dev = private;
d8aea29b 482 struct ad799x_state *st = iio_priv(private);
72148f6e 483 int i, ret;
985dbe77 484
54154471
PM
485 ret = i2c_smbus_read_byte_data(st->client, AD7998_ALERT_STAT_REG);
486 if (ret <= 0)
f654a7e2 487 goto done;
985dbe77 488
54154471
PM
489 if (i2c_smbus_write_byte_data(st->client, AD7998_ALERT_STAT_REG,
490 AD7998_ALERT_STAT_CLEAR) < 0)
f654a7e2 491 goto done;
985dbe77 492
985dbe77 493 for (i = 0; i < 8; i++) {
e1c6e2a2 494 if (ret & BIT(i))
5aa96188 495 iio_push_event(indio_dev,
72148f6e 496 i & 0x1 ?
6835cb6b 497 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
cdf38709
JC
498 (i >> 1),
499 IIO_EV_TYPE_THRESH,
500 IIO_EV_DIR_RISING) :
6835cb6b 501 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
cdf38709
JC
502 (i >> 1),
503 IIO_EV_TYPE_THRESH,
504 IIO_EV_DIR_FALLING),
bc2b7dab 505 iio_get_time_ns(indio_dev));
985dbe77
MH
506 }
507
f654a7e2 508done:
72148f6e 509 return IRQ_HANDLED;
985dbe77
MH
510}
511
985dbe77
MH
512static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
513 ad799x_read_frequency,
514 ad799x_write_frequency);
515static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("15625 7812 3906 1953 976 488 244 0");
516
ba1d7961 517static struct attribute *ad799x_event_attributes[] = {
985dbe77
MH
518 &iio_dev_attr_sampling_frequency.dev_attr.attr,
519 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
520 NULL,
521};
522
ba1d7961
LPC
523static struct attribute_group ad799x_event_attrs_group = {
524 .attrs = ad799x_event_attributes,
985dbe77
MH
525};
526
6fe8135f
JC
527static const struct iio_info ad7991_info = {
528 .read_raw = &ad799x_read_raw,
529 .driver_module = THIS_MODULE,
7d3cc21d 530 .update_scan_mode = ad799x_update_scan_mode,
6fe8135f
JC
531};
532
91556c69
PM
533static const struct iio_info ad7993_4_7_8_noirq_info = {
534 .read_raw = &ad799x_read_raw,
535 .driver_module = THIS_MODULE,
8235841b 536 .update_scan_mode = ad799x_update_scan_mode,
91556c69
PM
537};
538
539static const struct iio_info ad7993_4_7_8_irq_info = {
6fe8135f 540 .read_raw = &ad799x_read_raw,
ba1d7961 541 .event_attrs = &ad799x_event_attrs_group,
cb955852 542 .read_event_config = &ad799x_read_event_config,
3008d082 543 .write_event_config = &ad799x_write_event_config,
cb955852
LPC
544 .read_event_value = &ad799x_read_event_value,
545 .write_event_value = &ad799x_write_event_value,
6fe8135f 546 .driver_module = THIS_MODULE,
8235841b 547 .update_scan_mode = ad799x_update_scan_mode,
6fe8135f
JC
548};
549
5b9e048a
LPC
550static const struct iio_event_spec ad799x_events[] = {
551 {
552 .type = IIO_EV_TYPE_THRESH,
553 .dir = IIO_EV_DIR_RISING,
554 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
555 BIT(IIO_EV_INFO_ENABLE),
556 }, {
557 .type = IIO_EV_TYPE_THRESH,
558 .dir = IIO_EV_DIR_FALLING,
d180371d 559 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
5b9e048a 560 BIT(IIO_EV_INFO_ENABLE),
ba1d7961
LPC
561 }, {
562 .type = IIO_EV_TYPE_THRESH,
563 .dir = IIO_EV_DIR_EITHER,
564 .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),
5b9e048a
LPC
565 },
566};
231c5c3b 567
5b9e048a 568#define _AD799X_CHANNEL(_index, _realbits, _ev_spec, _num_ev_spec) { \
ae6d6489
LPC
569 .type = IIO_VOLTAGE, \
570 .indexed = 1, \
571 .channel = (_index), \
572 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
d00698df 573 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
ae6d6489 574 .scan_index = (_index), \
83d5f324
JC
575 .scan_type = { \
576 .sign = 'u', \
577 .realbits = (_realbits), \
578 .storagebits = 16, \
579 .shift = 12 - (_realbits), \
580 .endianness = IIO_BE, \
581 }, \
5b9e048a
LPC
582 .event_spec = _ev_spec, \
583 .num_event_specs = _num_ev_spec, \
ae6d6489
LPC
584}
585
5b9e048a
LPC
586#define AD799X_CHANNEL(_index, _realbits) \
587 _AD799X_CHANNEL(_index, _realbits, NULL, 0)
588
589#define AD799X_CHANNEL_WITH_EVENTS(_index, _realbits) \
590 _AD799X_CHANNEL(_index, _realbits, ad799x_events, \
591 ARRAY_SIZE(ad799x_events))
592
985dbe77
MH
593static const struct ad799x_chip_info ad799x_chip_info_tbl[] = {
594 [ad7991] = {
d22fd9c5 595 .num_channels = 5,
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PM
596 .noirq_config = {
597 .channel = {
598 AD799X_CHANNEL(0, 12),
599 AD799X_CHANNEL(1, 12),
600 AD799X_CHANNEL(2, 12),
601 AD799X_CHANNEL(3, 12),
602 IIO_CHAN_SOFT_TIMESTAMP(4),
603 },
604 .info = &ad7991_info,
605 },
985dbe77
MH
606 },
607 [ad7995] = {
d22fd9c5 608 .num_channels = 5,
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PM
609 .noirq_config = {
610 .channel = {
611 AD799X_CHANNEL(0, 10),
612 AD799X_CHANNEL(1, 10),
613 AD799X_CHANNEL(2, 10),
614 AD799X_CHANNEL(3, 10),
615 IIO_CHAN_SOFT_TIMESTAMP(4),
616 },
617 .info = &ad7991_info,
618 },
985dbe77
MH
619 },
620 [ad7999] = {
d22fd9c5 621 .num_channels = 5,
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PM
622 .noirq_config = {
623 .channel = {
624 AD799X_CHANNEL(0, 8),
625 AD799X_CHANNEL(1, 8),
626 AD799X_CHANNEL(2, 8),
627 AD799X_CHANNEL(3, 8),
628 IIO_CHAN_SOFT_TIMESTAMP(4),
629 },
630 .info = &ad7991_info,
631 },
985dbe77
MH
632 },
633 [ad7992] = {
d22fd9c5 634 .num_channels = 3,
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PM
635 .noirq_config = {
636 .channel = {
637 AD799X_CHANNEL(0, 12),
638 AD799X_CHANNEL(1, 12),
639 IIO_CHAN_SOFT_TIMESTAMP(3),
640 },
641 .info = &ad7993_4_7_8_noirq_info,
642 },
643 .irq_config = {
644 .channel = {
645 AD799X_CHANNEL_WITH_EVENTS(0, 12),
646 AD799X_CHANNEL_WITH_EVENTS(1, 12),
647 IIO_CHAN_SOFT_TIMESTAMP(3),
648 },
0f7ddcc1 649 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
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PM
650 .info = &ad7993_4_7_8_irq_info,
651 },
985dbe77
MH
652 },
653 [ad7993] = {
d22fd9c5 654 .num_channels = 5,
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PM
655 .noirq_config = {
656 .channel = {
657 AD799X_CHANNEL(0, 10),
658 AD799X_CHANNEL(1, 10),
659 AD799X_CHANNEL(2, 10),
660 AD799X_CHANNEL(3, 10),
661 IIO_CHAN_SOFT_TIMESTAMP(4),
662 },
663 .info = &ad7993_4_7_8_noirq_info,
664 },
665 .irq_config = {
666 .channel = {
667 AD799X_CHANNEL_WITH_EVENTS(0, 10),
668 AD799X_CHANNEL_WITH_EVENTS(1, 10),
669 AD799X_CHANNEL_WITH_EVENTS(2, 10),
670 AD799X_CHANNEL_WITH_EVENTS(3, 10),
671 IIO_CHAN_SOFT_TIMESTAMP(4),
672 },
0f7ddcc1 673 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
91556c69
PM
674 .info = &ad7993_4_7_8_irq_info,
675 },
985dbe77
MH
676 },
677 [ad7994] = {
d22fd9c5 678 .num_channels = 5,
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PM
679 .noirq_config = {
680 .channel = {
681 AD799X_CHANNEL(0, 12),
682 AD799X_CHANNEL(1, 12),
683 AD799X_CHANNEL(2, 12),
684 AD799X_CHANNEL(3, 12),
685 IIO_CHAN_SOFT_TIMESTAMP(4),
686 },
687 .info = &ad7993_4_7_8_noirq_info,
688 },
689 .irq_config = {
690 .channel = {
691 AD799X_CHANNEL_WITH_EVENTS(0, 12),
692 AD799X_CHANNEL_WITH_EVENTS(1, 12),
693 AD799X_CHANNEL_WITH_EVENTS(2, 12),
694 AD799X_CHANNEL_WITH_EVENTS(3, 12),
695 IIO_CHAN_SOFT_TIMESTAMP(4),
696 },
0f7ddcc1 697 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
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PM
698 .info = &ad7993_4_7_8_irq_info,
699 },
985dbe77
MH
700 },
701 [ad7997] = {
d22fd9c5 702 .num_channels = 9,
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PM
703 .noirq_config = {
704 .channel = {
705 AD799X_CHANNEL(0, 10),
706 AD799X_CHANNEL(1, 10),
707 AD799X_CHANNEL(2, 10),
708 AD799X_CHANNEL(3, 10),
709 AD799X_CHANNEL(4, 10),
710 AD799X_CHANNEL(5, 10),
711 AD799X_CHANNEL(6, 10),
712 AD799X_CHANNEL(7, 10),
713 IIO_CHAN_SOFT_TIMESTAMP(8),
714 },
715 .info = &ad7993_4_7_8_noirq_info,
716 },
717 .irq_config = {
718 .channel = {
719 AD799X_CHANNEL_WITH_EVENTS(0, 10),
720 AD799X_CHANNEL_WITH_EVENTS(1, 10),
721 AD799X_CHANNEL_WITH_EVENTS(2, 10),
722 AD799X_CHANNEL_WITH_EVENTS(3, 10),
723 AD799X_CHANNEL(4, 10),
724 AD799X_CHANNEL(5, 10),
725 AD799X_CHANNEL(6, 10),
726 AD799X_CHANNEL(7, 10),
727 IIO_CHAN_SOFT_TIMESTAMP(8),
728 },
0f7ddcc1 729 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
91556c69
PM
730 .info = &ad7993_4_7_8_irq_info,
731 },
985dbe77
MH
732 },
733 [ad7998] = {
d22fd9c5 734 .num_channels = 9,
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PM
735 .noirq_config = {
736 .channel = {
737 AD799X_CHANNEL(0, 12),
738 AD799X_CHANNEL(1, 12),
739 AD799X_CHANNEL(2, 12),
740 AD799X_CHANNEL(3, 12),
741 AD799X_CHANNEL(4, 12),
742 AD799X_CHANNEL(5, 12),
743 AD799X_CHANNEL(6, 12),
744 AD799X_CHANNEL(7, 12),
745 IIO_CHAN_SOFT_TIMESTAMP(8),
746 },
747 .info = &ad7993_4_7_8_noirq_info,
748 },
749 .irq_config = {
750 .channel = {
751 AD799X_CHANNEL_WITH_EVENTS(0, 12),
752 AD799X_CHANNEL_WITH_EVENTS(1, 12),
753 AD799X_CHANNEL_WITH_EVENTS(2, 12),
754 AD799X_CHANNEL_WITH_EVENTS(3, 12),
755 AD799X_CHANNEL(4, 12),
756 AD799X_CHANNEL(5, 12),
757 AD799X_CHANNEL(6, 12),
758 AD799X_CHANNEL(7, 12),
759 IIO_CHAN_SOFT_TIMESTAMP(8),
760 },
0f7ddcc1 761 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
91556c69
PM
762 .info = &ad7993_4_7_8_irq_info,
763 },
985dbe77
MH
764 },
765};
766
4ae1c61f 767static int ad799x_probe(struct i2c_client *client,
985dbe77
MH
768 const struct i2c_device_id *id)
769{
26d25ae3 770 int ret;
1bf7ac76 771 struct ad799x_state *st;
6a88fa48 772 struct iio_dev *indio_dev;
91556c69
PM
773 const struct ad799x_chip_info *chip_info =
774 &ad799x_chip_info_tbl[id->driver_data];
1bf7ac76 775
6a88fa48 776 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
1bf7ac76
MH
777 if (indio_dev == NULL)
778 return -ENOMEM;
985dbe77 779
1bf7ac76 780 st = iio_priv(indio_dev);
985dbe77 781 /* this is only used for device removal purposes */
1bf7ac76 782 i2c_set_clientdata(client, indio_dev);
985dbe77 783
985dbe77 784 st->id = id->driver_data;
91556c69
PM
785 if (client->irq > 0 && chip_info->irq_config.info)
786 st->chip_config = &chip_info->irq_config;
787 else
788 st->chip_config = &chip_info->noirq_config;
985dbe77
MH
789
790 /* TODO: Add pdata options for filtering and bit delay */
791
6a88fa48 792 st->reg = devm_regulator_get(&client->dev, "vcc");
2deaf23b
HK
793 if (IS_ERR(st->reg))
794 return PTR_ERR(st->reg);
795 ret = regulator_enable(st->reg);
796 if (ret)
797 return ret;
798 st->vref = devm_regulator_get(&client->dev, "vref");
799 if (IS_ERR(st->vref)) {
800 ret = PTR_ERR(st->vref);
801 goto error_disable_reg;
985dbe77 802 }
2deaf23b
HK
803 ret = regulator_enable(st->vref);
804 if (ret)
805 goto error_disable_reg;
806
985dbe77
MH
807 st->client = client;
808
1bf7ac76 809 indio_dev->dev.parent = &client->dev;
b541eaff 810 indio_dev->dev.of_node = client->dev.of_node;
1bf7ac76 811 indio_dev->name = id->name;
91556c69 812 indio_dev->info = st->chip_config->info;
6fe8135f 813
1bf7ac76 814 indio_dev->modes = INDIO_DIRECT_MODE;
91556c69
PM
815 indio_dev->channels = st->chip_config->channel;
816 indio_dev->num_channels = chip_info->num_channels;
1bf7ac76 817
0f7ddcc1
PM
818 ret = ad799x_write_config(st, st->chip_config->default_config);
819 if (ret < 0)
820 goto error_disable_reg;
821 ret = ad799x_read_config(st);
822 if (ret < 0)
823 goto error_disable_reg;
824 st->config = ret;
825
396590b3
LPC
826 ret = iio_triggered_buffer_setup(indio_dev, NULL,
827 &ad799x_trigger_handler, NULL);
985dbe77 828 if (ret)
82a5803c 829 goto error_disable_vref;
985dbe77 830
6fe8135f 831 if (client->irq > 0) {
cc7c0f7e
HK
832 ret = devm_request_threaded_irq(&client->dev,
833 client->irq,
834 NULL,
835 ad799x_event_handler,
836 IRQF_TRIGGER_FALLING |
837 IRQF_ONESHOT,
838 client->name,
839 indio_dev);
985dbe77
MH
840 if (ret)
841 goto error_cleanup_ring;
985dbe77 842 }
26d25ae3
JC
843 ret = iio_device_register(indio_dev);
844 if (ret)
cc7c0f7e 845 goto error_cleanup_ring;
985dbe77
MH
846
847 return 0;
1bf7ac76 848
985dbe77 849error_cleanup_ring:
396590b3 850 iio_triggered_buffer_cleanup(indio_dev);
82a5803c
DC
851error_disable_vref:
852 regulator_disable(st->vref);
985dbe77 853error_disable_reg:
82a5803c 854 regulator_disable(st->reg);
1bf7ac76 855
985dbe77
MH
856 return ret;
857}
858
447d4f29 859static int ad799x_remove(struct i2c_client *client)
985dbe77 860{
1bf7ac76
MH
861 struct iio_dev *indio_dev = i2c_get_clientdata(client);
862 struct ad799x_state *st = iio_priv(indio_dev);
985dbe77 863
d2fffd6c 864 iio_device_unregister(indio_dev);
985dbe77 865
396590b3 866 iio_triggered_buffer_cleanup(indio_dev);
82a5803c
DC
867 regulator_disable(st->vref);
868 regulator_disable(st->reg);
d8dca330 869 kfree(st->rx_buf);
985dbe77
MH
870
871 return 0;
872}
873
874static const struct i2c_device_id ad799x_id[] = {
875 { "ad7991", ad7991 },
876 { "ad7995", ad7995 },
877 { "ad7999", ad7999 },
878 { "ad7992", ad7992 },
879 { "ad7993", ad7993 },
880 { "ad7994", ad7994 },
881 { "ad7997", ad7997 },
882 { "ad7998", ad7998 },
883 {}
884};
885
886MODULE_DEVICE_TABLE(i2c, ad799x_id);
887
888static struct i2c_driver ad799x_driver = {
889 .driver = {
890 .name = "ad799x",
891 },
892 .probe = ad799x_probe,
e543acf0 893 .remove = ad799x_remove,
985dbe77
MH
894 .id_table = ad799x_id,
895};
6e5af184 896module_i2c_driver(ad799x_driver);
985dbe77
MH
897
898MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
899MODULE_DESCRIPTION("Analog Devices AD799x ADC");
900MODULE_LICENSE("GPL v2");