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57380323 RA |
1 | /* |
2 | * Aspeed AST2400/2500 ADC | |
3 | * | |
4 | * Copyright (C) 2017 Google, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of_platform.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/types.h> | |
22 | ||
23 | #include <linux/iio/iio.h> | |
24 | #include <linux/iio/driver.h> | |
25 | ||
26 | #define ASPEED_RESOLUTION_BITS 10 | |
27 | #define ASPEED_CLOCKS_PER_SAMPLE 12 | |
28 | ||
29 | #define ASPEED_REG_ENGINE_CONTROL 0x00 | |
30 | #define ASPEED_REG_INTERRUPT_CONTROL 0x04 | |
31 | #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 | |
32 | #define ASPEED_REG_CLOCK_CONTROL 0x0C | |
33 | #define ASPEED_REG_MAX 0xC0 | |
34 | ||
35 | #define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1) | |
36 | #define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1) | |
37 | #define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1) | |
38 | ||
39 | #define ASPEED_ENGINE_ENABLE BIT(0) | |
40 | ||
41 | struct aspeed_adc_model_data { | |
42 | const char *model_name; | |
43 | unsigned int min_sampling_rate; // Hz | |
44 | unsigned int max_sampling_rate; // Hz | |
45 | unsigned int vref_voltage; // mV | |
46 | }; | |
47 | ||
48 | struct aspeed_adc_data { | |
49 | struct device *dev; | |
50 | void __iomem *base; | |
51 | spinlock_t clk_lock; | |
52 | struct clk_hw *clk_prescaler; | |
53 | struct clk_hw *clk_scaler; | |
54 | }; | |
55 | ||
56 | #define ASPEED_CHAN(_idx, _data_reg_addr) { \ | |
57 | .type = IIO_VOLTAGE, \ | |
58 | .indexed = 1, \ | |
59 | .channel = (_idx), \ | |
60 | .address = (_data_reg_addr), \ | |
61 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
62 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ | |
63 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ | |
64 | } | |
65 | ||
66 | static const struct iio_chan_spec aspeed_adc_iio_channels[] = { | |
67 | ASPEED_CHAN(0, 0x10), | |
68 | ASPEED_CHAN(1, 0x12), | |
69 | ASPEED_CHAN(2, 0x14), | |
70 | ASPEED_CHAN(3, 0x16), | |
71 | ASPEED_CHAN(4, 0x18), | |
72 | ASPEED_CHAN(5, 0x1A), | |
73 | ASPEED_CHAN(6, 0x1C), | |
74 | ASPEED_CHAN(7, 0x1E), | |
75 | ASPEED_CHAN(8, 0x20), | |
76 | ASPEED_CHAN(9, 0x22), | |
77 | ASPEED_CHAN(10, 0x24), | |
78 | ASPEED_CHAN(11, 0x26), | |
79 | ASPEED_CHAN(12, 0x28), | |
80 | ASPEED_CHAN(13, 0x2A), | |
81 | ASPEED_CHAN(14, 0x2C), | |
82 | ASPEED_CHAN(15, 0x2E), | |
83 | }; | |
84 | ||
85 | static int aspeed_adc_read_raw(struct iio_dev *indio_dev, | |
86 | struct iio_chan_spec const *chan, | |
87 | int *val, int *val2, long mask) | |
88 | { | |
89 | struct aspeed_adc_data *data = iio_priv(indio_dev); | |
90 | const struct aspeed_adc_model_data *model_data = | |
91 | of_device_get_match_data(data->dev); | |
92 | ||
93 | switch (mask) { | |
94 | case IIO_CHAN_INFO_RAW: | |
95 | *val = readw(data->base + chan->address); | |
96 | return IIO_VAL_INT; | |
97 | ||
98 | case IIO_CHAN_INFO_SCALE: | |
99 | *val = model_data->vref_voltage; | |
100 | *val2 = ASPEED_RESOLUTION_BITS; | |
101 | return IIO_VAL_FRACTIONAL_LOG2; | |
102 | ||
103 | case IIO_CHAN_INFO_SAMP_FREQ: | |
104 | *val = clk_get_rate(data->clk_scaler->clk) / | |
105 | ASPEED_CLOCKS_PER_SAMPLE; | |
106 | return IIO_VAL_INT; | |
107 | ||
108 | default: | |
109 | return -EINVAL; | |
110 | } | |
111 | } | |
112 | ||
113 | static int aspeed_adc_write_raw(struct iio_dev *indio_dev, | |
114 | struct iio_chan_spec const *chan, | |
115 | int val, int val2, long mask) | |
116 | { | |
117 | struct aspeed_adc_data *data = iio_priv(indio_dev); | |
118 | const struct aspeed_adc_model_data *model_data = | |
119 | of_device_get_match_data(data->dev); | |
120 | ||
121 | switch (mask) { | |
122 | case IIO_CHAN_INFO_SAMP_FREQ: | |
123 | if (val < model_data->min_sampling_rate || | |
124 | val > model_data->max_sampling_rate) | |
125 | return -EINVAL; | |
126 | ||
127 | clk_set_rate(data->clk_scaler->clk, | |
128 | val * ASPEED_CLOCKS_PER_SAMPLE); | |
129 | return 0; | |
130 | ||
131 | case IIO_CHAN_INFO_SCALE: | |
132 | case IIO_CHAN_INFO_RAW: | |
133 | /* | |
134 | * Technically, these could be written but the only reasons | |
135 | * for doing so seem better handled in userspace. EPERM is | |
136 | * returned to signal this is a policy choice rather than a | |
137 | * hardware limitation. | |
138 | */ | |
139 | return -EPERM; | |
140 | ||
141 | default: | |
142 | return -EINVAL; | |
143 | } | |
144 | } | |
145 | ||
146 | static int aspeed_adc_reg_access(struct iio_dev *indio_dev, | |
147 | unsigned int reg, unsigned int writeval, | |
148 | unsigned int *readval) | |
149 | { | |
150 | struct aspeed_adc_data *data = iio_priv(indio_dev); | |
151 | ||
152 | if (!readval || reg % 4 || reg > ASPEED_REG_MAX) | |
153 | return -EINVAL; | |
154 | ||
155 | *readval = readl(data->base + reg); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static const struct iio_info aspeed_adc_iio_info = { | |
161 | .driver_module = THIS_MODULE, | |
162 | .read_raw = aspeed_adc_read_raw, | |
163 | .write_raw = aspeed_adc_write_raw, | |
164 | .debugfs_reg_access = aspeed_adc_reg_access, | |
165 | }; | |
166 | ||
167 | static int aspeed_adc_probe(struct platform_device *pdev) | |
168 | { | |
169 | struct iio_dev *indio_dev; | |
170 | struct aspeed_adc_data *data; | |
171 | const struct aspeed_adc_model_data *model_data; | |
172 | struct resource *res; | |
173 | const char *clk_parent_name; | |
174 | int ret; | |
175 | u32 adc_engine_control_reg_val; | |
176 | ||
177 | indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data)); | |
178 | if (!indio_dev) | |
179 | return -ENOMEM; | |
180 | ||
181 | data = iio_priv(indio_dev); | |
182 | data->dev = &pdev->dev; | |
183 | ||
184 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
185 | data->base = devm_ioremap_resource(&pdev->dev, res); | |
186 | if (IS_ERR(data->base)) | |
187 | return PTR_ERR(data->base); | |
188 | ||
189 | /* Register ADC clock prescaler with source specified by device tree. */ | |
190 | spin_lock_init(&data->clk_lock); | |
191 | clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); | |
192 | ||
193 | data->clk_prescaler = clk_hw_register_divider( | |
194 | &pdev->dev, "prescaler", clk_parent_name, 0, | |
195 | data->base + ASPEED_REG_CLOCK_CONTROL, | |
196 | 17, 15, 0, &data->clk_lock); | |
197 | if (IS_ERR(data->clk_prescaler)) | |
198 | return PTR_ERR(data->clk_prescaler); | |
199 | ||
200 | /* | |
201 | * Register ADC clock scaler downstream from the prescaler. Allow rate | |
202 | * setting to adjust the prescaler as well. | |
203 | */ | |
204 | data->clk_scaler = clk_hw_register_divider( | |
205 | &pdev->dev, "scaler", "prescaler", | |
206 | CLK_SET_RATE_PARENT, | |
207 | data->base + ASPEED_REG_CLOCK_CONTROL, | |
208 | 0, 10, 0, &data->clk_lock); | |
209 | if (IS_ERR(data->clk_scaler)) { | |
210 | ret = PTR_ERR(data->clk_scaler); | |
211 | goto scaler_error; | |
212 | } | |
213 | ||
214 | /* Start all channels in normal mode. */ | |
4e36a8ad AY |
215 | ret = clk_prepare_enable(data->clk_scaler->clk); |
216 | if (ret) | |
217 | goto clk_enable_error; | |
218 | ||
57380323 RA |
219 | adc_engine_control_reg_val = GENMASK(31, 16) | |
220 | ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE; | |
221 | writel(adc_engine_control_reg_val, | |
222 | data->base + ASPEED_REG_ENGINE_CONTROL); | |
223 | ||
224 | model_data = of_device_get_match_data(&pdev->dev); | |
225 | indio_dev->name = model_data->model_name; | |
226 | indio_dev->dev.parent = &pdev->dev; | |
227 | indio_dev->info = &aspeed_adc_iio_info; | |
228 | indio_dev->modes = INDIO_DIRECT_MODE; | |
229 | indio_dev->channels = aspeed_adc_iio_channels; | |
230 | indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels); | |
231 | ||
232 | ret = iio_device_register(indio_dev); | |
233 | if (ret) | |
234 | goto iio_register_error; | |
235 | ||
236 | return 0; | |
237 | ||
238 | iio_register_error: | |
239 | writel(ASPEED_OPERATION_MODE_POWER_DOWN, | |
240 | data->base + ASPEED_REG_ENGINE_CONTROL); | |
241 | clk_disable_unprepare(data->clk_scaler->clk); | |
4e36a8ad | 242 | clk_enable_error: |
57380323 RA |
243 | clk_hw_unregister_divider(data->clk_scaler); |
244 | ||
245 | scaler_error: | |
246 | clk_hw_unregister_divider(data->clk_prescaler); | |
247 | return ret; | |
248 | } | |
249 | ||
250 | static int aspeed_adc_remove(struct platform_device *pdev) | |
251 | { | |
252 | struct iio_dev *indio_dev = platform_get_drvdata(pdev); | |
253 | struct aspeed_adc_data *data = iio_priv(indio_dev); | |
254 | ||
255 | iio_device_unregister(indio_dev); | |
256 | writel(ASPEED_OPERATION_MODE_POWER_DOWN, | |
257 | data->base + ASPEED_REG_ENGINE_CONTROL); | |
258 | clk_disable_unprepare(data->clk_scaler->clk); | |
259 | clk_hw_unregister_divider(data->clk_scaler); | |
260 | clk_hw_unregister_divider(data->clk_prescaler); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static const struct aspeed_adc_model_data ast2400_model_data = { | |
266 | .model_name = "ast2400-adc", | |
267 | .vref_voltage = 2500, // mV | |
268 | .min_sampling_rate = 10000, | |
269 | .max_sampling_rate = 500000, | |
270 | }; | |
271 | ||
272 | static const struct aspeed_adc_model_data ast2500_model_data = { | |
273 | .model_name = "ast2500-adc", | |
274 | .vref_voltage = 1800, // mV | |
275 | .min_sampling_rate = 1, | |
276 | .max_sampling_rate = 1000000, | |
277 | }; | |
278 | ||
279 | static const struct of_device_id aspeed_adc_matches[] = { | |
280 | { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data }, | |
281 | { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data }, | |
282 | {}, | |
283 | }; | |
284 | MODULE_DEVICE_TABLE(of, aspeed_adc_matches); | |
285 | ||
286 | static struct platform_driver aspeed_adc_driver = { | |
287 | .probe = aspeed_adc_probe, | |
288 | .remove = aspeed_adc_remove, | |
289 | .driver = { | |
290 | .name = KBUILD_MODNAME, | |
291 | .of_match_table = aspeed_adc_matches, | |
292 | } | |
293 | }; | |
294 | ||
295 | module_platform_driver(aspeed_adc_driver); | |
296 | ||
297 | MODULE_AUTHOR("Rick Altherr <raltherr@google.com>"); | |
298 | MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver"); | |
299 | MODULE_LICENSE("GPL"); |