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57380323 RA |
1 | /* |
2 | * Aspeed AST2400/2500 ADC | |
3 | * | |
4 | * Copyright (C) 2017 Google, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of_platform.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/types.h> | |
22 | ||
23 | #include <linux/iio/iio.h> | |
24 | #include <linux/iio/driver.h> | |
737cc2a5 | 25 | #include <linux/iopoll.h> |
57380323 RA |
26 | |
27 | #define ASPEED_RESOLUTION_BITS 10 | |
28 | #define ASPEED_CLOCKS_PER_SAMPLE 12 | |
29 | ||
30 | #define ASPEED_REG_ENGINE_CONTROL 0x00 | |
31 | #define ASPEED_REG_INTERRUPT_CONTROL 0x04 | |
32 | #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 | |
33 | #define ASPEED_REG_CLOCK_CONTROL 0x0C | |
34 | #define ASPEED_REG_MAX 0xC0 | |
35 | ||
36 | #define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1) | |
37 | #define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1) | |
38 | #define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1) | |
39 | ||
40 | #define ASPEED_ENGINE_ENABLE BIT(0) | |
41 | ||
737cc2a5 MK |
42 | #define ASPEED_ADC_CTRL_INIT_RDY BIT(8) |
43 | ||
44 | #define ASPEED_ADC_INIT_POLLING_TIME 500 | |
45 | #define ASPEED_ADC_INIT_TIMEOUT 500000 | |
46 | ||
57380323 RA |
47 | struct aspeed_adc_model_data { |
48 | const char *model_name; | |
49 | unsigned int min_sampling_rate; // Hz | |
50 | unsigned int max_sampling_rate; // Hz | |
51 | unsigned int vref_voltage; // mV | |
737cc2a5 | 52 | bool wait_init_sequence; |
57380323 RA |
53 | }; |
54 | ||
55 | struct aspeed_adc_data { | |
56 | struct device *dev; | |
57 | void __iomem *base; | |
58 | spinlock_t clk_lock; | |
59 | struct clk_hw *clk_prescaler; | |
60 | struct clk_hw *clk_scaler; | |
61 | }; | |
62 | ||
63 | #define ASPEED_CHAN(_idx, _data_reg_addr) { \ | |
64 | .type = IIO_VOLTAGE, \ | |
65 | .indexed = 1, \ | |
66 | .channel = (_idx), \ | |
67 | .address = (_data_reg_addr), \ | |
68 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
69 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ | |
70 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ | |
71 | } | |
72 | ||
73 | static const struct iio_chan_spec aspeed_adc_iio_channels[] = { | |
74 | ASPEED_CHAN(0, 0x10), | |
75 | ASPEED_CHAN(1, 0x12), | |
76 | ASPEED_CHAN(2, 0x14), | |
77 | ASPEED_CHAN(3, 0x16), | |
78 | ASPEED_CHAN(4, 0x18), | |
79 | ASPEED_CHAN(5, 0x1A), | |
80 | ASPEED_CHAN(6, 0x1C), | |
81 | ASPEED_CHAN(7, 0x1E), | |
82 | ASPEED_CHAN(8, 0x20), | |
83 | ASPEED_CHAN(9, 0x22), | |
84 | ASPEED_CHAN(10, 0x24), | |
85 | ASPEED_CHAN(11, 0x26), | |
86 | ASPEED_CHAN(12, 0x28), | |
87 | ASPEED_CHAN(13, 0x2A), | |
88 | ASPEED_CHAN(14, 0x2C), | |
89 | ASPEED_CHAN(15, 0x2E), | |
90 | }; | |
91 | ||
92 | static int aspeed_adc_read_raw(struct iio_dev *indio_dev, | |
93 | struct iio_chan_spec const *chan, | |
94 | int *val, int *val2, long mask) | |
95 | { | |
96 | struct aspeed_adc_data *data = iio_priv(indio_dev); | |
97 | const struct aspeed_adc_model_data *model_data = | |
98 | of_device_get_match_data(data->dev); | |
99 | ||
100 | switch (mask) { | |
101 | case IIO_CHAN_INFO_RAW: | |
102 | *val = readw(data->base + chan->address); | |
103 | return IIO_VAL_INT; | |
104 | ||
105 | case IIO_CHAN_INFO_SCALE: | |
106 | *val = model_data->vref_voltage; | |
107 | *val2 = ASPEED_RESOLUTION_BITS; | |
108 | return IIO_VAL_FRACTIONAL_LOG2; | |
109 | ||
110 | case IIO_CHAN_INFO_SAMP_FREQ: | |
111 | *val = clk_get_rate(data->clk_scaler->clk) / | |
112 | ASPEED_CLOCKS_PER_SAMPLE; | |
113 | return IIO_VAL_INT; | |
114 | ||
115 | default: | |
116 | return -EINVAL; | |
117 | } | |
118 | } | |
119 | ||
120 | static int aspeed_adc_write_raw(struct iio_dev *indio_dev, | |
121 | struct iio_chan_spec const *chan, | |
122 | int val, int val2, long mask) | |
123 | { | |
124 | struct aspeed_adc_data *data = iio_priv(indio_dev); | |
125 | const struct aspeed_adc_model_data *model_data = | |
126 | of_device_get_match_data(data->dev); | |
127 | ||
128 | switch (mask) { | |
129 | case IIO_CHAN_INFO_SAMP_FREQ: | |
130 | if (val < model_data->min_sampling_rate || | |
131 | val > model_data->max_sampling_rate) | |
132 | return -EINVAL; | |
133 | ||
134 | clk_set_rate(data->clk_scaler->clk, | |
135 | val * ASPEED_CLOCKS_PER_SAMPLE); | |
136 | return 0; | |
137 | ||
138 | case IIO_CHAN_INFO_SCALE: | |
139 | case IIO_CHAN_INFO_RAW: | |
140 | /* | |
141 | * Technically, these could be written but the only reasons | |
142 | * for doing so seem better handled in userspace. EPERM is | |
143 | * returned to signal this is a policy choice rather than a | |
144 | * hardware limitation. | |
145 | */ | |
146 | return -EPERM; | |
147 | ||
148 | default: | |
149 | return -EINVAL; | |
150 | } | |
151 | } | |
152 | ||
153 | static int aspeed_adc_reg_access(struct iio_dev *indio_dev, | |
154 | unsigned int reg, unsigned int writeval, | |
155 | unsigned int *readval) | |
156 | { | |
157 | struct aspeed_adc_data *data = iio_priv(indio_dev); | |
158 | ||
159 | if (!readval || reg % 4 || reg > ASPEED_REG_MAX) | |
160 | return -EINVAL; | |
161 | ||
162 | *readval = readl(data->base + reg); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | static const struct iio_info aspeed_adc_iio_info = { | |
168 | .driver_module = THIS_MODULE, | |
169 | .read_raw = aspeed_adc_read_raw, | |
170 | .write_raw = aspeed_adc_write_raw, | |
171 | .debugfs_reg_access = aspeed_adc_reg_access, | |
172 | }; | |
173 | ||
174 | static int aspeed_adc_probe(struct platform_device *pdev) | |
175 | { | |
176 | struct iio_dev *indio_dev; | |
177 | struct aspeed_adc_data *data; | |
178 | const struct aspeed_adc_model_data *model_data; | |
179 | struct resource *res; | |
180 | const char *clk_parent_name; | |
181 | int ret; | |
182 | u32 adc_engine_control_reg_val; | |
183 | ||
184 | indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data)); | |
185 | if (!indio_dev) | |
186 | return -ENOMEM; | |
187 | ||
188 | data = iio_priv(indio_dev); | |
189 | data->dev = &pdev->dev; | |
190 | ||
191 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
192 | data->base = devm_ioremap_resource(&pdev->dev, res); | |
193 | if (IS_ERR(data->base)) | |
194 | return PTR_ERR(data->base); | |
195 | ||
196 | /* Register ADC clock prescaler with source specified by device tree. */ | |
197 | spin_lock_init(&data->clk_lock); | |
198 | clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); | |
199 | ||
200 | data->clk_prescaler = clk_hw_register_divider( | |
201 | &pdev->dev, "prescaler", clk_parent_name, 0, | |
202 | data->base + ASPEED_REG_CLOCK_CONTROL, | |
203 | 17, 15, 0, &data->clk_lock); | |
204 | if (IS_ERR(data->clk_prescaler)) | |
205 | return PTR_ERR(data->clk_prescaler); | |
206 | ||
207 | /* | |
208 | * Register ADC clock scaler downstream from the prescaler. Allow rate | |
209 | * setting to adjust the prescaler as well. | |
210 | */ | |
211 | data->clk_scaler = clk_hw_register_divider( | |
212 | &pdev->dev, "scaler", "prescaler", | |
213 | CLK_SET_RATE_PARENT, | |
214 | data->base + ASPEED_REG_CLOCK_CONTROL, | |
215 | 0, 10, 0, &data->clk_lock); | |
216 | if (IS_ERR(data->clk_scaler)) { | |
217 | ret = PTR_ERR(data->clk_scaler); | |
218 | goto scaler_error; | |
219 | } | |
220 | ||
737cc2a5 MK |
221 | model_data = of_device_get_match_data(&pdev->dev); |
222 | ||
223 | if (model_data->wait_init_sequence) { | |
224 | /* Enable engine in normal mode. */ | |
225 | writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE, | |
226 | data->base + ASPEED_REG_ENGINE_CONTROL); | |
227 | ||
228 | /* Wait for initial sequence complete. */ | |
229 | ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL, | |
230 | adc_engine_control_reg_val, | |
231 | adc_engine_control_reg_val & | |
232 | ASPEED_ADC_CTRL_INIT_RDY, | |
233 | ASPEED_ADC_INIT_POLLING_TIME, | |
234 | ASPEED_ADC_INIT_TIMEOUT); | |
235 | if (ret) | |
236 | goto scaler_error; | |
237 | } | |
238 | ||
57380323 | 239 | /* Start all channels in normal mode. */ |
4e36a8ad AY |
240 | ret = clk_prepare_enable(data->clk_scaler->clk); |
241 | if (ret) | |
242 | goto clk_enable_error; | |
243 | ||
57380323 RA |
244 | adc_engine_control_reg_val = GENMASK(31, 16) | |
245 | ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE; | |
246 | writel(adc_engine_control_reg_val, | |
247 | data->base + ASPEED_REG_ENGINE_CONTROL); | |
248 | ||
249 | model_data = of_device_get_match_data(&pdev->dev); | |
250 | indio_dev->name = model_data->model_name; | |
251 | indio_dev->dev.parent = &pdev->dev; | |
252 | indio_dev->info = &aspeed_adc_iio_info; | |
253 | indio_dev->modes = INDIO_DIRECT_MODE; | |
254 | indio_dev->channels = aspeed_adc_iio_channels; | |
255 | indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels); | |
256 | ||
257 | ret = iio_device_register(indio_dev); | |
258 | if (ret) | |
259 | goto iio_register_error; | |
260 | ||
261 | return 0; | |
262 | ||
263 | iio_register_error: | |
264 | writel(ASPEED_OPERATION_MODE_POWER_DOWN, | |
265 | data->base + ASPEED_REG_ENGINE_CONTROL); | |
266 | clk_disable_unprepare(data->clk_scaler->clk); | |
4e36a8ad | 267 | clk_enable_error: |
57380323 RA |
268 | clk_hw_unregister_divider(data->clk_scaler); |
269 | ||
270 | scaler_error: | |
271 | clk_hw_unregister_divider(data->clk_prescaler); | |
272 | return ret; | |
273 | } | |
274 | ||
275 | static int aspeed_adc_remove(struct platform_device *pdev) | |
276 | { | |
277 | struct iio_dev *indio_dev = platform_get_drvdata(pdev); | |
278 | struct aspeed_adc_data *data = iio_priv(indio_dev); | |
279 | ||
280 | iio_device_unregister(indio_dev); | |
281 | writel(ASPEED_OPERATION_MODE_POWER_DOWN, | |
282 | data->base + ASPEED_REG_ENGINE_CONTROL); | |
283 | clk_disable_unprepare(data->clk_scaler->clk); | |
284 | clk_hw_unregister_divider(data->clk_scaler); | |
285 | clk_hw_unregister_divider(data->clk_prescaler); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
290 | static const struct aspeed_adc_model_data ast2400_model_data = { | |
291 | .model_name = "ast2400-adc", | |
292 | .vref_voltage = 2500, // mV | |
293 | .min_sampling_rate = 10000, | |
294 | .max_sampling_rate = 500000, | |
295 | }; | |
296 | ||
297 | static const struct aspeed_adc_model_data ast2500_model_data = { | |
298 | .model_name = "ast2500-adc", | |
299 | .vref_voltage = 1800, // mV | |
300 | .min_sampling_rate = 1, | |
301 | .max_sampling_rate = 1000000, | |
737cc2a5 | 302 | .wait_init_sequence = true, |
57380323 RA |
303 | }; |
304 | ||
305 | static const struct of_device_id aspeed_adc_matches[] = { | |
306 | { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data }, | |
307 | { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data }, | |
308 | {}, | |
309 | }; | |
310 | MODULE_DEVICE_TABLE(of, aspeed_adc_matches); | |
311 | ||
312 | static struct platform_driver aspeed_adc_driver = { | |
313 | .probe = aspeed_adc_probe, | |
314 | .remove = aspeed_adc_remove, | |
315 | .driver = { | |
316 | .name = KBUILD_MODNAME, | |
317 | .of_match_table = aspeed_adc_matches, | |
318 | } | |
319 | }; | |
320 | ||
321 | module_platform_driver(aspeed_adc_driver); | |
322 | ||
323 | MODULE_AUTHOR("Rick Altherr <raltherr@google.com>"); | |
324 | MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver"); | |
325 | MODULE_LICENSE("GPL"); |