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0e589d5f MR |
1 | /* |
2 | * Driver for the ADC present in the Atmel AT91 evaluation boards. | |
3 | * | |
4 | * Copyright 2011 Free Electrons | |
5 | * | |
6 | * Licensed under the GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/bitmap.h> | |
10 | #include <linux/bitops.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
c8b11de0 | 14 | #include <linux/input.h> |
0e589d5f MR |
15 | #include <linux/interrupt.h> |
16 | #include <linux/jiffies.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
e364185f MR |
19 | #include <linux/of.h> |
20 | #include <linux/of_device.h> | |
0e589d5f MR |
21 | #include <linux/platform_device.h> |
22 | #include <linux/sched.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/wait.h> | |
25 | ||
26 | #include <linux/platform_data/at91_adc.h> | |
27 | ||
28 | #include <linux/iio/iio.h> | |
29 | #include <linux/iio/buffer.h> | |
0e589d5f MR |
30 | #include <linux/iio/trigger.h> |
31 | #include <linux/iio/trigger_consumer.h> | |
90032e4e | 32 | #include <linux/iio/triggered_buffer.h> |
0e589d5f | 33 | |
bee20c4b AB |
34 | /* Registers */ |
35 | #define AT91_ADC_CR 0x00 /* Control Register */ | |
36 | #define AT91_ADC_SWRST (1 << 0) /* Software Reset */ | |
37 | #define AT91_ADC_START (1 << 1) /* Start Conversion */ | |
38 | ||
39 | #define AT91_ADC_MR 0x04 /* Mode Register */ | |
40 | #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */ | |
41 | #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */ | |
42 | #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */ | |
43 | #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ | |
44 | #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ | |
45 | #define AT91_ADC_TRGSEL_TC0 (0 << 1) | |
46 | #define AT91_ADC_TRGSEL_TC1 (1 << 1) | |
47 | #define AT91_ADC_TRGSEL_TC2 (2 << 1) | |
48 | #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) | |
49 | #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ | |
50 | #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ | |
51 | #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */ | |
52 | #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ | |
53 | #define AT91_ADC_PRESCAL_9G45 (0xff << 8) | |
54 | #define AT91_ADC_PRESCAL_(x) ((x) << 8) | |
55 | #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ | |
56 | #define AT91_ADC_STARTUP_9G45 (0x7f << 16) | |
57 | #define AT91_ADC_STARTUP_9X5 (0xf << 16) | |
58 | #define AT91_ADC_STARTUP_(x) ((x) << 16) | |
59 | #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ | |
60 | #define AT91_ADC_SHTIM_(x) ((x) << 24) | |
61 | #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */ | |
62 | #define AT91_ADC_PENDBC_(x) ((x) << 28) | |
63 | ||
64 | #define AT91_ADC_TSR 0x0C | |
65 | #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */ | |
66 | #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24) | |
67 | ||
68 | #define AT91_ADC_CHER 0x10 /* Channel Enable Register */ | |
69 | #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ | |
70 | #define AT91_ADC_CHSR 0x18 /* Channel Status Register */ | |
71 | #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ | |
72 | ||
73 | #define AT91_ADC_SR 0x1C /* Status Register */ | |
74 | #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ | |
75 | #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ | |
76 | #define AT91_ADC_DRDY (1 << 16) /* Data Ready */ | |
77 | #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ | |
78 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ | |
79 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ | |
80 | ||
81 | #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ | |
82 | #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ | |
83 | ||
84 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ | |
85 | #define AT91_ADC_LDATA (0x3ff) | |
86 | ||
87 | #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ | |
88 | #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ | |
89 | #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ | |
90 | #define AT91RL_ADC_IER_PEN (1 << 20) | |
91 | #define AT91RL_ADC_IER_NOPEN (1 << 21) | |
92 | #define AT91_ADC_IER_PEN (1 << 29) | |
93 | #define AT91_ADC_IER_NOPEN (1 << 30) | |
94 | #define AT91_ADC_IER_XRDY (1 << 20) | |
95 | #define AT91_ADC_IER_YRDY (1 << 21) | |
96 | #define AT91_ADC_IER_PRDY (1 << 22) | |
97 | #define AT91_ADC_ISR_PENS (1 << 31) | |
98 | ||
99 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ | |
100 | #define AT91_ADC_DATA (0x3ff) | |
101 | ||
102 | #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ | |
103 | ||
104 | #define AT91_ADC_ACR 0x94 /* Analog Control Register */ | |
105 | #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ | |
106 | ||
107 | #define AT91_ADC_TSMR 0xB0 | |
108 | #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ | |
109 | #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) | |
110 | #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) | |
111 | #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) | |
112 | #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) | |
113 | #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ | |
114 | #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) | |
115 | #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ | |
116 | #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ | |
117 | #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) | |
118 | #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ | |
119 | #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ | |
120 | #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ | |
121 | ||
122 | #define AT91_ADC_TSXPOSR 0xB4 | |
123 | #define AT91_ADC_TSYPOSR 0xB8 | |
124 | #define AT91_ADC_TSPRESSR 0xBC | |
125 | ||
126 | #define AT91_ADC_TRGR_9260 AT91_ADC_MR | |
127 | #define AT91_ADC_TRGR_9G45 0x08 | |
128 | #define AT91_ADC_TRGR_9X5 0xC0 | |
129 | ||
130 | /* Trigger Register bit field */ | |
131 | #define AT91_ADC_TRGR_TRGPER (0xffff << 16) | |
132 | #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) | |
133 | #define AT91_ADC_TRGR_TRGMOD (0x7 << 0) | |
134 | #define AT91_ADC_TRGR_NONE (0 << 0) | |
135 | #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) | |
0e589d5f MR |
136 | |
137 | #define AT91_ADC_CHAN(st, ch) \ | |
138 | (st->registers->channel_base + (ch * 4)) | |
139 | #define at91_adc_readl(st, reg) \ | |
140 | (readl_relaxed(st->reg_base + reg)) | |
141 | #define at91_adc_writel(st, reg, val) \ | |
142 | (writel_relaxed(val, st->reg_base + reg)) | |
143 | ||
c8b11de0 JW |
144 | #define DRIVER_NAME "at91_adc" |
145 | #define MAX_POS_BITS 12 | |
146 | ||
147 | #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ | |
148 | #define TOUCH_PEN_DETECT_DEBOUNCE_US 200 | |
149 | ||
84882b06 AB |
150 | #define MAX_RLPOS_BITS 10 |
151 | #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */ | |
152 | #define TOUCH_SHTIM 0xa | |
153 | ||
2de0c019 AB |
154 | /** |
155 | * struct at91_adc_reg_desc - Various informations relative to registers | |
156 | * @channel_base: Base offset for the channel data registers | |
157 | * @drdy_mask: Mask of the DRDY field in the relevant registers | |
158 | (Interruptions registers mostly) | |
159 | * @status_register: Offset of the Interrupt Status Register | |
160 | * @trigger_register: Offset of the Trigger setup register | |
161 | * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register | |
162 | * @mr_startup_mask: Mask of the STARTUP field in the adc MR register | |
163 | */ | |
164 | struct at91_adc_reg_desc { | |
165 | u8 channel_base; | |
166 | u32 drdy_mask; | |
167 | u8 status_register; | |
168 | u8 trigger_register; | |
169 | u32 mr_prescal_mask; | |
170 | u32 mr_startup_mask; | |
171 | }; | |
172 | ||
e1811f97 | 173 | struct at91_adc_caps { |
c8b11de0 JW |
174 | bool has_ts; /* Support touch screen */ |
175 | bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */ | |
176 | /* | |
177 | * Numbers of sampling data will be averaged. Can be 0~3. | |
178 | * Hardware can average (2 ^ ts_filter_average) sample data. | |
179 | */ | |
180 | u8 ts_filter_average; | |
181 | /* Pen Detection input pull-up resistor, can be 0~3 */ | |
182 | u8 ts_pen_detect_sensitivity; | |
183 | ||
c4601666 | 184 | /* startup time calculate function */ |
2ab5f39b | 185 | u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz); |
c4601666 | 186 | |
2b6d598b | 187 | u8 num_channels; |
e1811f97 JW |
188 | struct at91_adc_reg_desc registers; |
189 | }; | |
190 | ||
0e589d5f MR |
191 | struct at91_adc_state { |
192 | struct clk *adc_clk; | |
193 | u16 *buffer; | |
194 | unsigned long channels_mask; | |
195 | struct clk *clk; | |
196 | bool done; | |
197 | int irq; | |
0e589d5f | 198 | u16 last_value; |
d4f51956 | 199 | int chnb; |
0e589d5f MR |
200 | struct mutex lock; |
201 | u8 num_channels; | |
202 | void __iomem *reg_base; | |
203 | struct at91_adc_reg_desc *registers; | |
2ab5f39b | 204 | u32 startup_time; |
beca9e76 | 205 | u8 sample_hold_time; |
e748783c | 206 | bool sleep_mode; |
0e589d5f MR |
207 | struct iio_trigger **trig; |
208 | struct at91_adc_trigger *trigger_list; | |
209 | u32 trigger_number; | |
210 | bool use_external; | |
211 | u32 vref_mv; | |
47be16b6 LD |
212 | u32 res; /* resolution used for convertions */ |
213 | bool low_res; /* the resolution corresponds to the lowest one */ | |
0e589d5f | 214 | wait_queue_head_t wq_data_avail; |
e1811f97 | 215 | struct at91_adc_caps *caps; |
c8b11de0 JW |
216 | |
217 | /* | |
218 | * Following ADC channels are shared by touchscreen: | |
219 | * | |
220 | * CH0 -- Touch screen XP/UL | |
221 | * CH1 -- Touch screen XM/UR | |
222 | * CH2 -- Touch screen YP/LL | |
223 | * CH3 -- Touch screen YM/Sense | |
224 | * CH4 -- Touch screen LR(5-wire only) | |
225 | * | |
226 | * The bitfields below represents the reserved channel in the | |
227 | * touchscreen mode. | |
228 | */ | |
229 | #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0) | |
230 | #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0) | |
231 | enum atmel_adc_ts_type touchscreen_type; | |
232 | struct input_dev *ts_input; | |
233 | ||
234 | u16 ts_sample_period_val; | |
235 | u32 ts_pressure_threshold; | |
84882b06 AB |
236 | u16 ts_pendbc; |
237 | ||
238 | bool ts_bufferedmeasure; | |
239 | u32 ts_prev_absx; | |
240 | u32 ts_prev_absy; | |
0e589d5f MR |
241 | }; |
242 | ||
243 | static irqreturn_t at91_adc_trigger_handler(int irq, void *p) | |
244 | { | |
245 | struct iio_poll_func *pf = p; | |
246 | struct iio_dev *idev = pf->indio_dev; | |
247 | struct at91_adc_state *st = iio_priv(idev); | |
0e589d5f MR |
248 | int i, j = 0; |
249 | ||
250 | for (i = 0; i < idev->masklength; i++) { | |
251 | if (!test_bit(i, idev->active_scan_mask)) | |
252 | continue; | |
253 | st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i)); | |
254 | j++; | |
255 | } | |
256 | ||
e79cece0 | 257 | iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp); |
0e589d5f MR |
258 | |
259 | iio_trigger_notify_done(idev->trig); | |
0e589d5f MR |
260 | |
261 | /* Needed to ACK the DRDY interruption */ | |
262 | at91_adc_readl(st, AT91_ADC_LCDR); | |
263 | ||
264 | enable_irq(st->irq); | |
265 | ||
266 | return IRQ_HANDLED; | |
267 | } | |
268 | ||
c8b11de0 | 269 | /* Handler for classic adc channel eoc trigger */ |
3068ab20 | 270 | static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev) |
0e589d5f | 271 | { |
0e589d5f | 272 | struct at91_adc_state *st = iio_priv(idev); |
0e589d5f MR |
273 | |
274 | if (iio_buffer_enabled(idev)) { | |
275 | disable_irq_nosync(irq); | |
398fd22b | 276 | iio_trigger_poll(idev->trig); |
0e589d5f | 277 | } else { |
d4f51956 | 278 | st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb)); |
0e589d5f MR |
279 | st->done = true; |
280 | wake_up_interruptible(&st->wq_data_avail); | |
281 | } | |
c8b11de0 JW |
282 | } |
283 | ||
284 | static int at91_ts_sample(struct at91_adc_state *st) | |
285 | { | |
286 | unsigned int xscale, yscale, reg, z1, z2; | |
287 | unsigned int x, y, pres, xpos, ypos; | |
288 | unsigned int rxp = 1; | |
289 | unsigned int factor = 1000; | |
290 | struct iio_dev *idev = iio_priv_to_dev(st); | |
291 | ||
292 | unsigned int xyz_mask_bits = st->res; | |
293 | unsigned int xyz_mask = (1 << xyz_mask_bits) - 1; | |
294 | ||
295 | /* calculate position */ | |
296 | /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */ | |
297 | reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); | |
298 | xpos = reg & xyz_mask; | |
299 | x = (xpos << MAX_POS_BITS) - xpos; | |
300 | xscale = (reg >> 16) & xyz_mask; | |
301 | if (xscale == 0) { | |
302 | dev_err(&idev->dev, "Error: xscale == 0!\n"); | |
303 | return -1; | |
304 | } | |
305 | x /= xscale; | |
306 | ||
307 | /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */ | |
308 | reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); | |
309 | ypos = reg & xyz_mask; | |
310 | y = (ypos << MAX_POS_BITS) - ypos; | |
311 | yscale = (reg >> 16) & xyz_mask; | |
312 | if (yscale == 0) { | |
313 | dev_err(&idev->dev, "Error: yscale == 0!\n"); | |
314 | return -1; | |
315 | } | |
316 | y /= yscale; | |
317 | ||
318 | /* calculate the pressure */ | |
319 | reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); | |
320 | z1 = reg & xyz_mask; | |
321 | z2 = (reg >> 16) & xyz_mask; | |
322 | ||
323 | if (z1 != 0) | |
324 | pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor) | |
325 | / factor; | |
326 | else | |
327 | pres = st->ts_pressure_threshold; /* no pen contacted */ | |
328 | ||
329 | dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n", | |
330 | xpos, xscale, ypos, yscale, z1, z2, pres); | |
331 | ||
332 | if (pres < st->ts_pressure_threshold) { | |
333 | dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n", | |
334 | x, y, pres / factor); | |
335 | input_report_abs(st->ts_input, ABS_X, x); | |
336 | input_report_abs(st->ts_input, ABS_Y, y); | |
337 | input_report_abs(st->ts_input, ABS_PRESSURE, pres); | |
338 | input_report_key(st->ts_input, BTN_TOUCH, 1); | |
339 | input_sync(st->ts_input); | |
340 | } else { | |
341 | dev_dbg(&idev->dev, "pressure too low: not reporting\n"); | |
342 | } | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
84882b06 AB |
347 | static irqreturn_t at91_adc_rl_interrupt(int irq, void *private) |
348 | { | |
349 | struct iio_dev *idev = private; | |
350 | struct at91_adc_state *st = iio_priv(idev); | |
351 | u32 status = at91_adc_readl(st, st->registers->status_register); | |
352 | unsigned int reg; | |
353 | ||
354 | status &= at91_adc_readl(st, AT91_ADC_IMR); | |
d4f51956 | 355 | if (status & GENMASK(st->num_channels - 1, 0)) |
84882b06 AB |
356 | handle_adc_eoc_trigger(irq, idev); |
357 | ||
358 | if (status & AT91RL_ADC_IER_PEN) { | |
359 | /* Disabling pen debounce is required to get a NOPEN irq */ | |
360 | reg = at91_adc_readl(st, AT91_ADC_MR); | |
361 | reg &= ~AT91_ADC_PENDBC; | |
362 | at91_adc_writel(st, AT91_ADC_MR, reg); | |
363 | ||
364 | at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); | |
365 | at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN | |
366 | | AT91_ADC_EOC(3)); | |
367 | /* Set up period trigger for sampling */ | |
368 | at91_adc_writel(st, st->registers->trigger_register, | |
369 | AT91_ADC_TRGR_MOD_PERIOD_TRIG | | |
370 | AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); | |
371 | } else if (status & AT91RL_ADC_IER_NOPEN) { | |
372 | reg = at91_adc_readl(st, AT91_ADC_MR); | |
373 | reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; | |
374 | at91_adc_writel(st, AT91_ADC_MR, reg); | |
375 | at91_adc_writel(st, st->registers->trigger_register, | |
376 | AT91_ADC_TRGR_NONE); | |
377 | ||
378 | at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN | |
379 | | AT91_ADC_EOC(3)); | |
380 | at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); | |
381 | st->ts_bufferedmeasure = false; | |
382 | input_report_key(st->ts_input, BTN_TOUCH, 0); | |
383 | input_sync(st->ts_input); | |
384 | } else if (status & AT91_ADC_EOC(3)) { | |
385 | /* Conversion finished */ | |
386 | if (st->ts_bufferedmeasure) { | |
387 | /* | |
388 | * Last measurement is always discarded, since it can | |
389 | * be erroneous. | |
390 | * Always report previous measurement | |
391 | */ | |
392 | input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx); | |
393 | input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy); | |
394 | input_report_key(st->ts_input, BTN_TOUCH, 1); | |
395 | input_sync(st->ts_input); | |
396 | } else | |
397 | st->ts_bufferedmeasure = true; | |
398 | ||
399 | /* Now make new measurement */ | |
400 | st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3)) | |
401 | << MAX_RLPOS_BITS; | |
402 | st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2)); | |
403 | ||
404 | st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1)) | |
405 | << MAX_RLPOS_BITS; | |
406 | st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0)); | |
407 | } | |
408 | ||
409 | return IRQ_HANDLED; | |
410 | } | |
411 | ||
412 | static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private) | |
c8b11de0 JW |
413 | { |
414 | struct iio_dev *idev = private; | |
415 | struct at91_adc_state *st = iio_priv(idev); | |
416 | u32 status = at91_adc_readl(st, st->registers->status_register); | |
417 | const uint32_t ts_data_irq_mask = | |
418 | AT91_ADC_IER_XRDY | | |
419 | AT91_ADC_IER_YRDY | | |
420 | AT91_ADC_IER_PRDY; | |
421 | ||
d4f51956 | 422 | if (status & GENMASK(st->num_channels - 1, 0)) |
c8b11de0 JW |
423 | handle_adc_eoc_trigger(irq, idev); |
424 | ||
425 | if (status & AT91_ADC_IER_PEN) { | |
426 | at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); | |
427 | at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN | | |
428 | ts_data_irq_mask); | |
429 | /* Set up period trigger for sampling */ | |
430 | at91_adc_writel(st, st->registers->trigger_register, | |
431 | AT91_ADC_TRGR_MOD_PERIOD_TRIG | | |
432 | AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); | |
433 | } else if (status & AT91_ADC_IER_NOPEN) { | |
434 | at91_adc_writel(st, st->registers->trigger_register, 0); | |
435 | at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN | | |
436 | ts_data_irq_mask); | |
437 | at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); | |
438 | ||
439 | input_report_key(st->ts_input, BTN_TOUCH, 0); | |
440 | input_sync(st->ts_input); | |
441 | } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) { | |
442 | /* Now all touchscreen data is ready */ | |
443 | ||
444 | if (status & AT91_ADC_ISR_PENS) { | |
445 | /* validate data by pen contact */ | |
446 | at91_ts_sample(st); | |
447 | } else { | |
448 | /* triggered by event that is no pen contact, just read | |
449 | * them to clean the interrupt and discard all. | |
450 | */ | |
451 | at91_adc_readl(st, AT91_ADC_TSXPOSR); | |
452 | at91_adc_readl(st, AT91_ADC_TSYPOSR); | |
453 | at91_adc_readl(st, AT91_ADC_TSPRESSR); | |
454 | } | |
455 | } | |
0e589d5f MR |
456 | |
457 | return IRQ_HANDLED; | |
458 | } | |
459 | ||
460 | static int at91_adc_channel_init(struct iio_dev *idev) | |
461 | { | |
462 | struct at91_adc_state *st = iio_priv(idev); | |
463 | struct iio_chan_spec *chan_array, *timestamp; | |
464 | int bit, idx = 0; | |
c8b11de0 JW |
465 | unsigned long rsvd_mask = 0; |
466 | ||
467 | /* If touchscreen is enable, then reserve the adc channels */ | |
468 | if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) | |
469 | rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE; | |
470 | else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE) | |
471 | rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE; | |
472 | ||
473 | /* set up the channel mask to reserve touchscreen channels */ | |
474 | st->channels_mask &= ~rsvd_mask; | |
0e589d5f MR |
475 | |
476 | idev->num_channels = bitmap_weight(&st->channels_mask, | |
477 | st->num_channels) + 1; | |
478 | ||
6b3aa313 AL |
479 | chan_array = devm_kzalloc(&idev->dev, |
480 | ((idev->num_channels + 1) * | |
481 | sizeof(struct iio_chan_spec)), | |
482 | GFP_KERNEL); | |
0e589d5f MR |
483 | |
484 | if (!chan_array) | |
485 | return -ENOMEM; | |
486 | ||
487 | for_each_set_bit(bit, &st->channels_mask, st->num_channels) { | |
488 | struct iio_chan_spec *chan = chan_array + idx; | |
489 | ||
490 | chan->type = IIO_VOLTAGE; | |
491 | chan->indexed = 1; | |
492 | chan->channel = bit; | |
493 | chan->scan_index = idx; | |
494 | chan->scan_type.sign = 'u'; | |
47be16b6 | 495 | chan->scan_type.realbits = st->res; |
0e589d5f | 496 | chan->scan_type.storagebits = 16; |
01bdab66 JC |
497 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); |
498 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); | |
0e589d5f MR |
499 | idx++; |
500 | } | |
501 | timestamp = chan_array + idx; | |
502 | ||
503 | timestamp->type = IIO_TIMESTAMP; | |
504 | timestamp->channel = -1; | |
505 | timestamp->scan_index = idx; | |
506 | timestamp->scan_type.sign = 's'; | |
507 | timestamp->scan_type.realbits = 64; | |
508 | timestamp->scan_type.storagebits = 64; | |
509 | ||
510 | idev->channels = chan_array; | |
511 | return idev->num_channels; | |
512 | } | |
513 | ||
4f3bcd87 | 514 | static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, |
0e589d5f MR |
515 | struct at91_adc_trigger *triggers, |
516 | const char *trigger_name) | |
517 | { | |
518 | struct at91_adc_state *st = iio_priv(idev); | |
0e589d5f MR |
519 | int i; |
520 | ||
521 | for (i = 0; i < st->trigger_number; i++) { | |
522 | char *name = kasprintf(GFP_KERNEL, | |
523 | "%s-dev%d-%s", | |
524 | idev->name, | |
525 | idev->id, | |
526 | triggers[i].name); | |
527 | if (!name) | |
528 | return -ENOMEM; | |
529 | ||
530 | if (strcmp(trigger_name, name) == 0) { | |
0e589d5f | 531 | kfree(name); |
4f3bcd87 DC |
532 | if (triggers[i].value == 0) |
533 | return -EINVAL; | |
534 | return triggers[i].value; | |
0e589d5f MR |
535 | } |
536 | ||
537 | kfree(name); | |
538 | } | |
539 | ||
4f3bcd87 | 540 | return -EINVAL; |
0e589d5f MR |
541 | } |
542 | ||
543 | static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) | |
544 | { | |
1e9663c6 | 545 | struct iio_dev *idev = iio_trigger_get_drvdata(trig); |
0e589d5f | 546 | struct at91_adc_state *st = iio_priv(idev); |
0e589d5f MR |
547 | struct at91_adc_reg_desc *reg = st->registers; |
548 | u32 status = at91_adc_readl(st, reg->trigger_register); | |
4f3bcd87 | 549 | int value; |
0e589d5f MR |
550 | u8 bit; |
551 | ||
552 | value = at91_adc_get_trigger_value_by_name(idev, | |
553 | st->trigger_list, | |
554 | idev->trig->name); | |
4f3bcd87 DC |
555 | if (value < 0) |
556 | return value; | |
0e589d5f MR |
557 | |
558 | if (state) { | |
559 | st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); | |
560 | if (st->buffer == NULL) | |
561 | return -ENOMEM; | |
562 | ||
563 | at91_adc_writel(st, reg->trigger_register, | |
564 | status | value); | |
565 | ||
70dddeee | 566 | for_each_set_bit(bit, idev->active_scan_mask, |
0e589d5f MR |
567 | st->num_channels) { |
568 | struct iio_chan_spec const *chan = idev->channels + bit; | |
569 | at91_adc_writel(st, AT91_ADC_CHER, | |
570 | AT91_ADC_CH(chan->channel)); | |
571 | } | |
572 | ||
573 | at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); | |
574 | ||
575 | } else { | |
576 | at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); | |
577 | ||
578 | at91_adc_writel(st, reg->trigger_register, | |
579 | status & ~value); | |
580 | ||
70dddeee | 581 | for_each_set_bit(bit, idev->active_scan_mask, |
0e589d5f MR |
582 | st->num_channels) { |
583 | struct iio_chan_spec const *chan = idev->channels + bit; | |
584 | at91_adc_writel(st, AT91_ADC_CHDR, | |
585 | AT91_ADC_CH(chan->channel)); | |
586 | } | |
587 | kfree(st->buffer); | |
588 | } | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
593 | static const struct iio_trigger_ops at91_adc_trigger_ops = { | |
594 | .owner = THIS_MODULE, | |
595 | .set_trigger_state = &at91_adc_configure_trigger, | |
596 | }; | |
597 | ||
598 | static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, | |
599 | struct at91_adc_trigger *trigger) | |
600 | { | |
601 | struct iio_trigger *trig; | |
602 | int ret; | |
603 | ||
604 | trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, | |
605 | idev->id, trigger->name); | |
606 | if (trig == NULL) | |
607 | return NULL; | |
608 | ||
609 | trig->dev.parent = idev->dev.parent; | |
1e9663c6 | 610 | iio_trigger_set_drvdata(trig, idev); |
0e589d5f MR |
611 | trig->ops = &at91_adc_trigger_ops; |
612 | ||
613 | ret = iio_trigger_register(trig); | |
614 | if (ret) | |
615 | return NULL; | |
616 | ||
617 | return trig; | |
618 | } | |
619 | ||
620 | static int at91_adc_trigger_init(struct iio_dev *idev) | |
621 | { | |
622 | struct at91_adc_state *st = iio_priv(idev); | |
623 | int i, ret; | |
624 | ||
6b3aa313 | 625 | st->trig = devm_kzalloc(&idev->dev, |
42877236 | 626 | st->trigger_number * sizeof(*st->trig), |
6b3aa313 | 627 | GFP_KERNEL); |
0e589d5f MR |
628 | |
629 | if (st->trig == NULL) { | |
630 | ret = -ENOMEM; | |
631 | goto error_ret; | |
632 | } | |
633 | ||
634 | for (i = 0; i < st->trigger_number; i++) { | |
635 | if (st->trigger_list[i].is_external && !(st->use_external)) | |
636 | continue; | |
637 | ||
638 | st->trig[i] = at91_adc_allocate_trigger(idev, | |
639 | st->trigger_list + i); | |
640 | if (st->trig[i] == NULL) { | |
641 | dev_err(&idev->dev, | |
642 | "Could not allocate trigger %d\n", i); | |
643 | ret = -ENOMEM; | |
644 | goto error_trigger; | |
645 | } | |
646 | } | |
647 | ||
648 | return 0; | |
649 | ||
650 | error_trigger: | |
651 | for (i--; i >= 0; i--) { | |
652 | iio_trigger_unregister(st->trig[i]); | |
653 | iio_trigger_free(st->trig[i]); | |
654 | } | |
655 | error_ret: | |
656 | return ret; | |
657 | } | |
658 | ||
659 | static void at91_adc_trigger_remove(struct iio_dev *idev) | |
660 | { | |
661 | struct at91_adc_state *st = iio_priv(idev); | |
662 | int i; | |
663 | ||
664 | for (i = 0; i < st->trigger_number; i++) { | |
665 | iio_trigger_unregister(st->trig[i]); | |
666 | iio_trigger_free(st->trig[i]); | |
667 | } | |
668 | } | |
669 | ||
0e589d5f MR |
670 | static int at91_adc_buffer_init(struct iio_dev *idev) |
671 | { | |
90032e4e LPC |
672 | return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, |
673 | &at91_adc_trigger_handler, NULL); | |
0e589d5f MR |
674 | } |
675 | ||
676 | static void at91_adc_buffer_remove(struct iio_dev *idev) | |
677 | { | |
90032e4e | 678 | iio_triggered_buffer_cleanup(idev); |
0e589d5f MR |
679 | } |
680 | ||
681 | static int at91_adc_read_raw(struct iio_dev *idev, | |
682 | struct iio_chan_spec const *chan, | |
683 | int *val, int *val2, long mask) | |
684 | { | |
685 | struct at91_adc_state *st = iio_priv(idev); | |
686 | int ret; | |
687 | ||
688 | switch (mask) { | |
689 | case IIO_CHAN_INFO_RAW: | |
690 | mutex_lock(&st->lock); | |
691 | ||
d4f51956 | 692 | st->chnb = chan->channel; |
0e589d5f MR |
693 | at91_adc_writel(st, AT91_ADC_CHER, |
694 | AT91_ADC_CH(chan->channel)); | |
d4f51956 | 695 | at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); |
0e589d5f MR |
696 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); |
697 | ||
698 | ret = wait_event_interruptible_timeout(st->wq_data_avail, | |
699 | st->done, | |
700 | msecs_to_jiffies(1000)); | |
701 | if (ret == 0) | |
90e6dc7c LPC |
702 | ret = -ETIMEDOUT; |
703 | if (ret < 0) { | |
704 | mutex_unlock(&st->lock); | |
0e589d5f | 705 | return ret; |
90e6dc7c | 706 | } |
0e589d5f MR |
707 | |
708 | *val = st->last_value; | |
709 | ||
710 | at91_adc_writel(st, AT91_ADC_CHDR, | |
711 | AT91_ADC_CH(chan->channel)); | |
d4f51956 | 712 | at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); |
0e589d5f MR |
713 | |
714 | st->last_value = 0; | |
715 | st->done = false; | |
716 | mutex_unlock(&st->lock); | |
717 | return IIO_VAL_INT; | |
718 | ||
719 | case IIO_CHAN_INFO_SCALE: | |
c45e561e LPC |
720 | *val = st->vref_mv; |
721 | *val2 = chan->scan_type.realbits; | |
722 | return IIO_VAL_FRACTIONAL_LOG2; | |
0e589d5f MR |
723 | default: |
724 | break; | |
725 | } | |
726 | return -EINVAL; | |
727 | } | |
728 | ||
47be16b6 LD |
729 | static int at91_adc_of_get_resolution(struct at91_adc_state *st, |
730 | struct platform_device *pdev) | |
731 | { | |
732 | struct iio_dev *idev = iio_priv_to_dev(st); | |
733 | struct device_node *np = pdev->dev.of_node; | |
734 | int count, i, ret = 0; | |
735 | char *res_name, *s; | |
736 | u32 *resolutions; | |
737 | ||
738 | count = of_property_count_strings(np, "atmel,adc-res-names"); | |
739 | if (count < 2) { | |
740 | dev_err(&idev->dev, "You must specified at least two resolution names for " | |
741 | "adc-res-names property in the DT\n"); | |
742 | return count; | |
743 | } | |
744 | ||
745 | resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL); | |
746 | if (!resolutions) | |
747 | return -ENOMEM; | |
748 | ||
749 | if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) { | |
750 | dev_err(&idev->dev, "Missing adc-res property in the DT.\n"); | |
751 | ret = -ENODEV; | |
752 | goto ret; | |
753 | } | |
754 | ||
755 | if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name)) | |
756 | res_name = "highres"; | |
757 | ||
758 | for (i = 0; i < count; i++) { | |
759 | if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s)) | |
760 | continue; | |
761 | ||
762 | if (strcmp(res_name, s)) | |
763 | continue; | |
764 | ||
765 | st->res = resolutions[i]; | |
766 | if (!strcmp(res_name, "lowres")) | |
767 | st->low_res = true; | |
768 | else | |
769 | st->low_res = false; | |
770 | ||
771 | dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); | |
772 | goto ret; | |
773 | } | |
774 | ||
775 | dev_err(&idev->dev, "There is no resolution for %s\n", res_name); | |
776 | ||
777 | ret: | |
778 | kfree(resolutions); | |
779 | return ret; | |
780 | } | |
781 | ||
2ab5f39b | 782 | static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz) |
c4601666 JW |
783 | { |
784 | /* | |
785 | * Number of ticks needed to cover the startup time of the ADC | |
786 | * as defined in the electrical characteristics of the board, | |
787 | * divided by 8. The formula thus is : | |
788 | * Startup Time = (ticks + 1) * 8 / ADC Clock | |
789 | */ | |
790 | return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8; | |
791 | } | |
792 | ||
2ab5f39b | 793 | static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz) |
c4601666 JW |
794 | { |
795 | /* | |
796 | * For sama5d3x and at91sam9x5, the formula changes to: | |
797 | * Startup Time = <lookup_table_value> / ADC Clock | |
798 | */ | |
799 | const int startup_lookup[] = { | |
800 | 0 , 8 , 16 , 24 , | |
801 | 64 , 80 , 96 , 112, | |
802 | 512, 576, 640, 704, | |
803 | 768, 832, 896, 960 | |
804 | }; | |
805 | int i, size = ARRAY_SIZE(startup_lookup); | |
806 | unsigned int ticks; | |
807 | ||
808 | ticks = startup_time * adc_clk_khz / 1000; | |
809 | for (i = 0; i < size; i++) | |
810 | if (ticks < startup_lookup[i]) | |
811 | break; | |
812 | ||
813 | ticks = i; | |
814 | if (ticks == size) | |
815 | /* Reach the end of lookup table */ | |
816 | ticks = size - 1; | |
817 | ||
818 | return ticks; | |
819 | } | |
820 | ||
e1811f97 JW |
821 | static const struct of_device_id at91_adc_dt_ids[]; |
822 | ||
c8b11de0 JW |
823 | static int at91_adc_probe_dt_ts(struct device_node *node, |
824 | struct at91_adc_state *st, struct device *dev) | |
825 | { | |
826 | int ret; | |
827 | u32 prop; | |
828 | ||
829 | ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop); | |
830 | if (ret) { | |
831 | dev_info(dev, "ADC Touch screen is disabled.\n"); | |
832 | return 0; | |
833 | } | |
834 | ||
835 | switch (prop) { | |
836 | case 4: | |
837 | case 5: | |
838 | st->touchscreen_type = prop; | |
839 | break; | |
840 | default: | |
841 | dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop); | |
842 | return -EINVAL; | |
843 | } | |
844 | ||
84882b06 AB |
845 | if (!st->caps->has_tsmr) |
846 | return 0; | |
c8b11de0 JW |
847 | prop = 0; |
848 | of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop); | |
849 | st->ts_pressure_threshold = prop; | |
850 | if (st->ts_pressure_threshold) { | |
851 | return 0; | |
852 | } else { | |
853 | dev_err(dev, "Invalid pressure threshold for the touchscreen\n"); | |
854 | return -EINVAL; | |
855 | } | |
856 | } | |
857 | ||
e364185f MR |
858 | static int at91_adc_probe_dt(struct at91_adc_state *st, |
859 | struct platform_device *pdev) | |
860 | { | |
861 | struct iio_dev *idev = iio_priv_to_dev(st); | |
862 | struct device_node *node = pdev->dev.of_node; | |
863 | struct device_node *trig_node; | |
864 | int i = 0, ret; | |
865 | u32 prop; | |
866 | ||
867 | if (!node) | |
868 | return -EINVAL; | |
869 | ||
e1811f97 JW |
870 | st->caps = (struct at91_adc_caps *) |
871 | of_match_device(at91_adc_dt_ids, &pdev->dev)->data; | |
872 | ||
e364185f MR |
873 | st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); |
874 | ||
875 | if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { | |
876 | dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); | |
877 | ret = -EINVAL; | |
878 | goto error_ret; | |
879 | } | |
880 | st->channels_mask = prop; | |
881 | ||
e748783c JCPV |
882 | st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); |
883 | ||
e364185f MR |
884 | if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { |
885 | dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); | |
886 | ret = -EINVAL; | |
887 | goto error_ret; | |
888 | } | |
889 | st->startup_time = prop; | |
890 | ||
beca9e76 JCPV |
891 | prop = 0; |
892 | of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); | |
893 | st->sample_hold_time = prop; | |
e364185f MR |
894 | |
895 | if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { | |
896 | dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); | |
897 | ret = -EINVAL; | |
898 | goto error_ret; | |
899 | } | |
900 | st->vref_mv = prop; | |
901 | ||
47be16b6 LD |
902 | ret = at91_adc_of_get_resolution(st, pdev); |
903 | if (ret) | |
904 | goto error_ret; | |
905 | ||
e1811f97 | 906 | st->registers = &st->caps->registers; |
2b6d598b | 907 | st->num_channels = st->caps->num_channels; |
e364185f | 908 | st->trigger_number = of_get_child_count(node); |
6b3aa313 AL |
909 | st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number * |
910 | sizeof(struct at91_adc_trigger), | |
911 | GFP_KERNEL); | |
e364185f MR |
912 | if (!st->trigger_list) { |
913 | dev_err(&idev->dev, "Could not allocate trigger list memory.\n"); | |
914 | ret = -ENOMEM; | |
915 | goto error_ret; | |
916 | } | |
917 | ||
918 | for_each_child_of_node(node, trig_node) { | |
919 | struct at91_adc_trigger *trig = st->trigger_list + i; | |
920 | const char *name; | |
921 | ||
922 | if (of_property_read_string(trig_node, "trigger-name", &name)) { | |
923 | dev_err(&idev->dev, "Missing trigger-name property in the DT.\n"); | |
924 | ret = -EINVAL; | |
925 | goto error_ret; | |
926 | } | |
927 | trig->name = name; | |
928 | ||
929 | if (of_property_read_u32(trig_node, "trigger-value", &prop)) { | |
930 | dev_err(&idev->dev, "Missing trigger-value property in the DT.\n"); | |
931 | ret = -EINVAL; | |
932 | goto error_ret; | |
933 | } | |
934 | trig->value = prop; | |
935 | trig->is_external = of_property_read_bool(trig_node, "trigger-external"); | |
936 | i++; | |
937 | } | |
938 | ||
c8b11de0 JW |
939 | /* Check if touchscreen is supported. */ |
940 | if (st->caps->has_ts) | |
941 | return at91_adc_probe_dt_ts(node, st, &idev->dev); | |
942 | else | |
943 | dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n"); | |
944 | ||
e364185f MR |
945 | return 0; |
946 | ||
947 | error_ret: | |
948 | return ret; | |
949 | } | |
950 | ||
0e589d5f MR |
951 | static int at91_adc_probe_pdata(struct at91_adc_state *st, |
952 | struct platform_device *pdev) | |
953 | { | |
954 | struct at91_adc_data *pdata = pdev->dev.platform_data; | |
955 | ||
956 | if (!pdata) | |
957 | return -EINVAL; | |
958 | ||
467a44b0 AB |
959 | st->caps = (struct at91_adc_caps *) |
960 | platform_get_device_id(pdev)->driver_data; | |
961 | ||
0e589d5f MR |
962 | st->use_external = pdata->use_external_triggers; |
963 | st->vref_mv = pdata->vref; | |
964 | st->channels_mask = pdata->channels_used; | |
467a44b0 | 965 | st->num_channels = st->caps->num_channels; |
0e589d5f MR |
966 | st->startup_time = pdata->startup_time; |
967 | st->trigger_number = pdata->trigger_number; | |
968 | st->trigger_list = pdata->trigger_list; | |
467a44b0 | 969 | st->registers = &st->caps->registers; |
84882b06 | 970 | st->touchscreen_type = pdata->touchscreen_type; |
0e589d5f MR |
971 | |
972 | return 0; | |
973 | } | |
974 | ||
975 | static const struct iio_info at91_adc_info = { | |
976 | .driver_module = THIS_MODULE, | |
977 | .read_raw = &at91_adc_read_raw, | |
978 | }; | |
979 | ||
c8b11de0 JW |
980 | /* Touchscreen related functions */ |
981 | static int atmel_ts_open(struct input_dev *dev) | |
982 | { | |
983 | struct at91_adc_state *st = input_get_drvdata(dev); | |
984 | ||
84882b06 AB |
985 | if (st->caps->has_tsmr) |
986 | at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); | |
987 | else | |
988 | at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); | |
c8b11de0 JW |
989 | return 0; |
990 | } | |
991 | ||
992 | static void atmel_ts_close(struct input_dev *dev) | |
993 | { | |
994 | struct at91_adc_state *st = input_get_drvdata(dev); | |
995 | ||
84882b06 AB |
996 | if (st->caps->has_tsmr) |
997 | at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); | |
998 | else | |
999 | at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); | |
c8b11de0 JW |
1000 | } |
1001 | ||
1002 | static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz) | |
1003 | { | |
84882b06 | 1004 | u32 reg = 0; |
c8b11de0 JW |
1005 | int i = 0; |
1006 | ||
c8b11de0 JW |
1007 | /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid |
1008 | * pen detect noise. | |
1009 | * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock | |
1010 | */ | |
84882b06 AB |
1011 | st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / |
1012 | 1000, 1); | |
c8b11de0 | 1013 | |
84882b06 | 1014 | while (st->ts_pendbc >> ++i) |
c8b11de0 | 1015 | ; /* Empty! Find the shift offset */ |
84882b06 AB |
1016 | if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1)))) |
1017 | st->ts_pendbc = i; | |
c8b11de0 | 1018 | else |
84882b06 | 1019 | st->ts_pendbc = i - 1; |
c8b11de0 | 1020 | |
84882b06 AB |
1021 | if (!st->caps->has_tsmr) { |
1022 | reg = at91_adc_readl(st, AT91_ADC_MR); | |
1023 | reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; | |
1024 | ||
1025 | reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; | |
1026 | at91_adc_writel(st, AT91_ADC_MR, reg); | |
1027 | ||
1028 | reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; | |
1029 | at91_adc_writel(st, AT91_ADC_TSR, reg); | |
1030 | ||
1031 | st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL * | |
1032 | adc_clk_khz / 1000) - 1, 1); | |
1033 | ||
1034 | return 0; | |
c8b11de0 JW |
1035 | } |
1036 | ||
84882b06 AB |
1037 | if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) |
1038 | reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; | |
1039 | else | |
1040 | reg = AT91_ADC_TSMR_TSMODE_5WIRE; | |
1041 | ||
1042 | reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) | |
1043 | & AT91_ADC_TSMR_TSAV; | |
1044 | reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; | |
1045 | reg |= AT91_ADC_TSMR_NOTSDMA; | |
1046 | reg |= AT91_ADC_TSMR_PENDET_ENA; | |
1047 | reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ | |
1048 | ||
1049 | at91_adc_writel(st, AT91_ADC_TSMR, reg); | |
1050 | ||
c8b11de0 JW |
1051 | /* Change adc internal resistor value for better pen detection, |
1052 | * default value is 100 kOhm. | |
1053 | * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm | |
1054 | * option only available on ES2 and higher | |
1055 | */ | |
1056 | at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity | |
1057 | & AT91_ADC_ACR_PENDETSENS); | |
1058 | ||
84882b06 | 1059 | /* Sample Period Time = (TRGPER + 1) / ADCClock */ |
c8b11de0 JW |
1060 | st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US * |
1061 | adc_clk_khz / 1000) - 1, 1); | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static int at91_ts_register(struct at91_adc_state *st, | |
1067 | struct platform_device *pdev) | |
1068 | { | |
1069 | struct input_dev *input; | |
1070 | struct iio_dev *idev = iio_priv_to_dev(st); | |
1071 | int ret; | |
1072 | ||
1073 | input = input_allocate_device(); | |
1074 | if (!input) { | |
1075 | dev_err(&idev->dev, "Failed to allocate TS device!\n"); | |
1076 | return -ENOMEM; | |
1077 | } | |
1078 | ||
1079 | input->name = DRIVER_NAME; | |
1080 | input->id.bustype = BUS_HOST; | |
1081 | input->dev.parent = &pdev->dev; | |
1082 | input->open = atmel_ts_open; | |
1083 | input->close = atmel_ts_close; | |
1084 | ||
1085 | __set_bit(EV_ABS, input->evbit); | |
1086 | __set_bit(EV_KEY, input->evbit); | |
1087 | __set_bit(BTN_TOUCH, input->keybit); | |
84882b06 AB |
1088 | if (st->caps->has_tsmr) { |
1089 | input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1, | |
1090 | 0, 0); | |
1091 | input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1, | |
1092 | 0, 0); | |
1093 | input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0); | |
1094 | } else { | |
1095 | if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) { | |
1096 | dev_err(&pdev->dev, | |
1097 | "This touchscreen controller only support 4 wires\n"); | |
1098 | ret = -EINVAL; | |
1099 | goto err; | |
1100 | } | |
1101 | ||
1102 | input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1, | |
1103 | 0, 0); | |
1104 | input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1, | |
1105 | 0, 0); | |
1106 | } | |
c8b11de0 JW |
1107 | |
1108 | st->ts_input = input; | |
1109 | input_set_drvdata(input, st); | |
1110 | ||
1111 | ret = input_register_device(input); | |
1112 | if (ret) | |
84882b06 AB |
1113 | goto err; |
1114 | ||
1115 | return ret; | |
c8b11de0 | 1116 | |
84882b06 AB |
1117 | err: |
1118 | input_free_device(st->ts_input); | |
c8b11de0 JW |
1119 | return ret; |
1120 | } | |
1121 | ||
1122 | static void at91_ts_unregister(struct at91_adc_state *st) | |
1123 | { | |
1124 | input_unregister_device(st->ts_input); | |
1125 | } | |
1126 | ||
fc52692c | 1127 | static int at91_adc_probe(struct platform_device *pdev) |
0e589d5f | 1128 | { |
db10e201 | 1129 | unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; |
0e589d5f MR |
1130 | int ret; |
1131 | struct iio_dev *idev; | |
1132 | struct at91_adc_state *st; | |
1133 | struct resource *res; | |
e748783c | 1134 | u32 reg; |
0e589d5f | 1135 | |
f8837532 SK |
1136 | idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); |
1137 | if (!idev) | |
1138 | return -ENOMEM; | |
0e589d5f MR |
1139 | |
1140 | st = iio_priv(idev); | |
1141 | ||
e364185f MR |
1142 | if (pdev->dev.of_node) |
1143 | ret = at91_adc_probe_dt(st, pdev); | |
1144 | else | |
1145 | ret = at91_adc_probe_pdata(st, pdev); | |
1146 | ||
0e589d5f MR |
1147 | if (ret) { |
1148 | dev_err(&pdev->dev, "No platform data available.\n"); | |
f8837532 | 1149 | return -EINVAL; |
0e589d5f MR |
1150 | } |
1151 | ||
0e589d5f MR |
1152 | platform_set_drvdata(pdev, idev); |
1153 | ||
1154 | idev->dev.parent = &pdev->dev; | |
1155 | idev->name = dev_name(&pdev->dev); | |
1156 | idev->modes = INDIO_DIRECT_MODE; | |
1157 | idev->info = &at91_adc_info; | |
1158 | ||
1159 | st->irq = platform_get_irq(pdev, 0); | |
1160 | if (st->irq < 0) { | |
1161 | dev_err(&pdev->dev, "No IRQ ID is designated\n"); | |
f8837532 | 1162 | return -ENODEV; |
0e589d5f MR |
1163 | } |
1164 | ||
390d75c1 | 1165 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
0e589d5f | 1166 | |
5fd98466 TR |
1167 | st->reg_base = devm_ioremap_resource(&pdev->dev, res); |
1168 | if (IS_ERR(st->reg_base)) { | |
f8837532 | 1169 | return PTR_ERR(st->reg_base); |
0e589d5f MR |
1170 | } |
1171 | ||
1172 | /* | |
1173 | * Disable all IRQs before setting up the handler | |
1174 | */ | |
1175 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); | |
1176 | at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); | |
84882b06 AB |
1177 | |
1178 | if (st->caps->has_tsmr) | |
1179 | ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0, | |
1180 | pdev->dev.driver->name, idev); | |
1181 | else | |
1182 | ret = request_irq(st->irq, at91_adc_rl_interrupt, 0, | |
1183 | pdev->dev.driver->name, idev); | |
0e589d5f MR |
1184 | if (ret) { |
1185 | dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); | |
f8837532 | 1186 | return ret; |
0e589d5f MR |
1187 | } |
1188 | ||
390d75c1 | 1189 | st->clk = devm_clk_get(&pdev->dev, "adc_clk"); |
0e589d5f MR |
1190 | if (IS_ERR(st->clk)) { |
1191 | dev_err(&pdev->dev, "Failed to get the clock.\n"); | |
1192 | ret = PTR_ERR(st->clk); | |
1193 | goto error_free_irq; | |
1194 | } | |
1195 | ||
00062a9c | 1196 | ret = clk_prepare_enable(st->clk); |
0e589d5f | 1197 | if (ret) { |
00062a9c JL |
1198 | dev_err(&pdev->dev, |
1199 | "Could not prepare or enable the clock.\n"); | |
390d75c1 | 1200 | goto error_free_irq; |
0e589d5f MR |
1201 | } |
1202 | ||
390d75c1 | 1203 | st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); |
0e589d5f MR |
1204 | if (IS_ERR(st->adc_clk)) { |
1205 | dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); | |
f755bbbf | 1206 | ret = PTR_ERR(st->adc_clk); |
0e589d5f MR |
1207 | goto error_disable_clk; |
1208 | } | |
1209 | ||
00062a9c | 1210 | ret = clk_prepare_enable(st->adc_clk); |
0e589d5f | 1211 | if (ret) { |
00062a9c JL |
1212 | dev_err(&pdev->dev, |
1213 | "Could not prepare or enable the ADC clock.\n"); | |
390d75c1 | 1214 | goto error_disable_clk; |
0e589d5f MR |
1215 | } |
1216 | ||
0e589d5f MR |
1217 | /* |
1218 | * Prescaler rate computation using the formula from the Atmel's | |
1219 | * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being | |
1220 | * specified by the electrical characteristics of the board. | |
1221 | */ | |
1222 | mstrclk = clk_get_rate(st->clk); | |
1223 | adc_clk = clk_get_rate(st->adc_clk); | |
db10e201 | 1224 | adc_clk_khz = adc_clk / 1000; |
c8b11de0 JW |
1225 | |
1226 | dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n", | |
1227 | mstrclk, adc_clk); | |
1228 | ||
0e589d5f MR |
1229 | prsc = (mstrclk / (2 * adc_clk)) - 1; |
1230 | ||
1231 | if (!st->startup_time) { | |
1232 | dev_err(&pdev->dev, "No startup time available.\n"); | |
1233 | ret = -EINVAL; | |
1234 | goto error_disable_adc_clk; | |
1235 | } | |
c4601666 | 1236 | ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); |
0e589d5f | 1237 | |
beca9e76 JCPV |
1238 | /* |
1239 | * a minimal Sample and Hold Time is necessary for the ADC to guarantee | |
1240 | * the best converted final value between two channels selection | |
1241 | * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock | |
1242 | */ | |
8f32b6ba AB |
1243 | if (st->sample_hold_time > 0) |
1244 | shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000) | |
1245 | - 1, 1); | |
1246 | else | |
1247 | shtim = 0; | |
beca9e76 | 1248 | |
9120c0be JW |
1249 | reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; |
1250 | reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; | |
47be16b6 | 1251 | if (st->low_res) |
e748783c JCPV |
1252 | reg |= AT91_ADC_LOWRES; |
1253 | if (st->sleep_mode) | |
1254 | reg |= AT91_ADC_SLEEP; | |
beca9e76 | 1255 | reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; |
e748783c | 1256 | at91_adc_writel(st, AT91_ADC_MR, reg); |
0e589d5f MR |
1257 | |
1258 | /* Setup the ADC channels available on the board */ | |
1259 | ret = at91_adc_channel_init(idev); | |
1260 | if (ret < 0) { | |
1261 | dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); | |
1262 | goto error_disable_adc_clk; | |
1263 | } | |
1264 | ||
1265 | init_waitqueue_head(&st->wq_data_avail); | |
1266 | mutex_init(&st->lock); | |
1267 | ||
c8b11de0 JW |
1268 | /* |
1269 | * Since touch screen will set trigger register as period trigger. So | |
1270 | * when touch screen is enabled, then we have to disable hardware | |
1271 | * trigger for classic adc. | |
1272 | */ | |
1273 | if (!st->touchscreen_type) { | |
1274 | ret = at91_adc_buffer_init(idev); | |
1275 | if (ret < 0) { | |
1276 | dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); | |
1277 | goto error_disable_adc_clk; | |
1278 | } | |
0e589d5f | 1279 | |
c8b11de0 JW |
1280 | ret = at91_adc_trigger_init(idev); |
1281 | if (ret < 0) { | |
1282 | dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); | |
1283 | at91_adc_buffer_remove(idev); | |
1284 | goto error_disable_adc_clk; | |
1285 | } | |
1286 | } else { | |
c8b11de0 JW |
1287 | ret = at91_ts_register(st, pdev); |
1288 | if (ret) | |
1289 | goto error_disable_adc_clk; | |
1290 | ||
1291 | at91_ts_hw_init(st, adc_clk_khz); | |
0e589d5f MR |
1292 | } |
1293 | ||
1294 | ret = iio_device_register(idev); | |
1295 | if (ret < 0) { | |
1296 | dev_err(&pdev->dev, "Couldn't register the device.\n"); | |
c8b11de0 | 1297 | goto error_iio_device_register; |
0e589d5f MR |
1298 | } |
1299 | ||
1300 | return 0; | |
1301 | ||
c8b11de0 JW |
1302 | error_iio_device_register: |
1303 | if (!st->touchscreen_type) { | |
1304 | at91_adc_trigger_remove(idev); | |
1305 | at91_adc_buffer_remove(idev); | |
1306 | } else { | |
1307 | at91_ts_unregister(st); | |
1308 | } | |
0e589d5f | 1309 | error_disable_adc_clk: |
00062a9c | 1310 | clk_disable_unprepare(st->adc_clk); |
0e589d5f | 1311 | error_disable_clk: |
00062a9c | 1312 | clk_disable_unprepare(st->clk); |
0e589d5f MR |
1313 | error_free_irq: |
1314 | free_irq(st->irq, idev); | |
0e589d5f MR |
1315 | return ret; |
1316 | } | |
1317 | ||
fc52692c | 1318 | static int at91_adc_remove(struct platform_device *pdev) |
0e589d5f MR |
1319 | { |
1320 | struct iio_dev *idev = platform_get_drvdata(pdev); | |
0e589d5f MR |
1321 | struct at91_adc_state *st = iio_priv(idev); |
1322 | ||
1323 | iio_device_unregister(idev); | |
c8b11de0 JW |
1324 | if (!st->touchscreen_type) { |
1325 | at91_adc_trigger_remove(idev); | |
1326 | at91_adc_buffer_remove(idev); | |
1327 | } else { | |
1328 | at91_ts_unregister(st); | |
1329 | } | |
0e589d5f | 1330 | clk_disable_unprepare(st->adc_clk); |
00062a9c | 1331 | clk_disable_unprepare(st->clk); |
0e589d5f | 1332 | free_irq(st->irq, idev); |
0e589d5f MR |
1333 | |
1334 | return 0; | |
1335 | } | |
1336 | ||
e1811f97 | 1337 | static struct at91_adc_caps at91sam9260_caps = { |
c4601666 | 1338 | .calc_startup_ticks = calc_startup_ticks_9260, |
2b6d598b | 1339 | .num_channels = 4, |
e1811f97 JW |
1340 | .registers = { |
1341 | .channel_base = AT91_ADC_CHR(0), | |
1342 | .drdy_mask = AT91_ADC_DRDY, | |
1343 | .status_register = AT91_ADC_SR, | |
1344 | .trigger_register = AT91_ADC_TRGR_9260, | |
9120c0be JW |
1345 | .mr_prescal_mask = AT91_ADC_PRESCAL_9260, |
1346 | .mr_startup_mask = AT91_ADC_STARTUP_9260, | |
e1811f97 JW |
1347 | }, |
1348 | }; | |
1349 | ||
65b1fdba AB |
1350 | static struct at91_adc_caps at91sam9rl_caps = { |
1351 | .has_ts = true, | |
1352 | .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ | |
1353 | .num_channels = 6, | |
1354 | .registers = { | |
1355 | .channel_base = AT91_ADC_CHR(0), | |
1356 | .drdy_mask = AT91_ADC_DRDY, | |
1357 | .status_register = AT91_ADC_SR, | |
1358 | .trigger_register = AT91_ADC_TRGR_9G45, | |
1359 | .mr_prescal_mask = AT91_ADC_PRESCAL_9260, | |
1360 | .mr_startup_mask = AT91_ADC_STARTUP_9G45, | |
1361 | }, | |
1362 | }; | |
1363 | ||
e1811f97 | 1364 | static struct at91_adc_caps at91sam9g45_caps = { |
c8b11de0 | 1365 | .has_ts = true, |
c4601666 | 1366 | .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ |
2b6d598b | 1367 | .num_channels = 8, |
e1811f97 JW |
1368 | .registers = { |
1369 | .channel_base = AT91_ADC_CHR(0), | |
1370 | .drdy_mask = AT91_ADC_DRDY, | |
1371 | .status_register = AT91_ADC_SR, | |
1372 | .trigger_register = AT91_ADC_TRGR_9G45, | |
9120c0be JW |
1373 | .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, |
1374 | .mr_startup_mask = AT91_ADC_STARTUP_9G45, | |
e1811f97 JW |
1375 | }, |
1376 | }; | |
1377 | ||
1378 | static struct at91_adc_caps at91sam9x5_caps = { | |
c8b11de0 JW |
1379 | .has_ts = true, |
1380 | .has_tsmr = true, | |
1381 | .ts_filter_average = 3, | |
1382 | .ts_pen_detect_sensitivity = 2, | |
c4601666 | 1383 | .calc_startup_ticks = calc_startup_ticks_9x5, |
2b6d598b | 1384 | .num_channels = 12, |
e1811f97 JW |
1385 | .registers = { |
1386 | .channel_base = AT91_ADC_CDR0_9X5, | |
1387 | .drdy_mask = AT91_ADC_SR_DRDY_9X5, | |
1388 | .status_register = AT91_ADC_SR_9X5, | |
1389 | .trigger_register = AT91_ADC_TRGR_9X5, | |
9120c0be JW |
1390 | /* prescal mask is same as 9G45 */ |
1391 | .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, | |
1392 | .mr_startup_mask = AT91_ADC_STARTUP_9X5, | |
e1811f97 JW |
1393 | }, |
1394 | }; | |
1395 | ||
e364185f | 1396 | static const struct of_device_id at91_adc_dt_ids[] = { |
e1811f97 | 1397 | { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps }, |
65b1fdba | 1398 | { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps }, |
e1811f97 JW |
1399 | { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps }, |
1400 | { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps }, | |
e364185f MR |
1401 | {}, |
1402 | }; | |
1403 | MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); | |
467a44b0 AB |
1404 | |
1405 | static const struct platform_device_id at91_adc_ids[] = { | |
1406 | { | |
1407 | .name = "at91sam9260-adc", | |
1408 | .driver_data = (unsigned long)&at91sam9260_caps, | |
65b1fdba AB |
1409 | }, { |
1410 | .name = "at91sam9rl-adc", | |
1411 | .driver_data = (unsigned long)&at91sam9rl_caps, | |
467a44b0 AB |
1412 | }, { |
1413 | .name = "at91sam9g45-adc", | |
1414 | .driver_data = (unsigned long)&at91sam9g45_caps, | |
1415 | }, { | |
1416 | .name = "at91sam9x5-adc", | |
1417 | .driver_data = (unsigned long)&at91sam9x5_caps, | |
1418 | }, { | |
1419 | /* terminator */ | |
1420 | } | |
1421 | }; | |
1422 | MODULE_DEVICE_TABLE(platform, at91_adc_ids); | |
e364185f | 1423 | |
0e589d5f MR |
1424 | static struct platform_driver at91_adc_driver = { |
1425 | .probe = at91_adc_probe, | |
fc52692c | 1426 | .remove = at91_adc_remove, |
467a44b0 | 1427 | .id_table = at91_adc_ids, |
0e589d5f | 1428 | .driver = { |
c8b11de0 | 1429 | .name = DRIVER_NAME, |
e364185f | 1430 | .of_match_table = of_match_ptr(at91_adc_dt_ids), |
0e589d5f MR |
1431 | }, |
1432 | }; | |
1433 | ||
1434 | module_platform_driver(at91_adc_driver); | |
1435 | ||
1436 | MODULE_LICENSE("GPL"); | |
1437 | MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); | |
1438 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |