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Commit | Line | Data |
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0e589d5f MR |
1 | /* |
2 | * Driver for the ADC present in the Atmel AT91 evaluation boards. | |
3 | * | |
4 | * Copyright 2011 Free Electrons | |
5 | * | |
6 | * Licensed under the GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/bitmap.h> | |
10 | #include <linux/bitops.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
e364185f MR |
18 | #include <linux/of.h> |
19 | #include <linux/of_device.h> | |
0e589d5f MR |
20 | #include <linux/platform_device.h> |
21 | #include <linux/sched.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/wait.h> | |
24 | ||
25 | #include <linux/platform_data/at91_adc.h> | |
26 | ||
27 | #include <linux/iio/iio.h> | |
28 | #include <linux/iio/buffer.h> | |
0e589d5f MR |
29 | #include <linux/iio/trigger.h> |
30 | #include <linux/iio/trigger_consumer.h> | |
90032e4e | 31 | #include <linux/iio/triggered_buffer.h> |
0e589d5f MR |
32 | |
33 | #include <mach/at91_adc.h> | |
34 | ||
35 | #define AT91_ADC_CHAN(st, ch) \ | |
36 | (st->registers->channel_base + (ch * 4)) | |
37 | #define at91_adc_readl(st, reg) \ | |
38 | (readl_relaxed(st->reg_base + reg)) | |
39 | #define at91_adc_writel(st, reg, val) \ | |
40 | (writel_relaxed(val, st->reg_base + reg)) | |
41 | ||
e1811f97 JW |
42 | struct at91_adc_caps { |
43 | struct at91_adc_reg_desc registers; | |
44 | }; | |
45 | ||
0e589d5f MR |
46 | struct at91_adc_state { |
47 | struct clk *adc_clk; | |
48 | u16 *buffer; | |
49 | unsigned long channels_mask; | |
50 | struct clk *clk; | |
51 | bool done; | |
52 | int irq; | |
0e589d5f MR |
53 | u16 last_value; |
54 | struct mutex lock; | |
55 | u8 num_channels; | |
56 | void __iomem *reg_base; | |
57 | struct at91_adc_reg_desc *registers; | |
58 | u8 startup_time; | |
beca9e76 | 59 | u8 sample_hold_time; |
e748783c | 60 | bool sleep_mode; |
0e589d5f MR |
61 | struct iio_trigger **trig; |
62 | struct at91_adc_trigger *trigger_list; | |
63 | u32 trigger_number; | |
64 | bool use_external; | |
65 | u32 vref_mv; | |
47be16b6 LD |
66 | u32 res; /* resolution used for convertions */ |
67 | bool low_res; /* the resolution corresponds to the lowest one */ | |
0e589d5f | 68 | wait_queue_head_t wq_data_avail; |
e1811f97 | 69 | struct at91_adc_caps *caps; |
0e589d5f MR |
70 | }; |
71 | ||
72 | static irqreturn_t at91_adc_trigger_handler(int irq, void *p) | |
73 | { | |
74 | struct iio_poll_func *pf = p; | |
75 | struct iio_dev *idev = pf->indio_dev; | |
76 | struct at91_adc_state *st = iio_priv(idev); | |
0e589d5f MR |
77 | int i, j = 0; |
78 | ||
79 | for (i = 0; i < idev->masklength; i++) { | |
80 | if (!test_bit(i, idev->active_scan_mask)) | |
81 | continue; | |
82 | st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i)); | |
83 | j++; | |
84 | } | |
85 | ||
86 | if (idev->scan_timestamp) { | |
87 | s64 *timestamp = (s64 *)((u8 *)st->buffer + | |
88 | ALIGN(j, sizeof(s64))); | |
89 | *timestamp = pf->timestamp; | |
90 | } | |
91 | ||
11679767 | 92 | iio_push_to_buffers(idev, (u8 *)st->buffer); |
0e589d5f MR |
93 | |
94 | iio_trigger_notify_done(idev->trig); | |
0e589d5f MR |
95 | |
96 | /* Needed to ACK the DRDY interruption */ | |
97 | at91_adc_readl(st, AT91_ADC_LCDR); | |
98 | ||
99 | enable_irq(st->irq); | |
100 | ||
101 | return IRQ_HANDLED; | |
102 | } | |
103 | ||
104 | static irqreturn_t at91_adc_eoc_trigger(int irq, void *private) | |
105 | { | |
106 | struct iio_dev *idev = private; | |
107 | struct at91_adc_state *st = iio_priv(idev); | |
108 | u32 status = at91_adc_readl(st, st->registers->status_register); | |
109 | ||
110 | if (!(status & st->registers->drdy_mask)) | |
111 | return IRQ_HANDLED; | |
112 | ||
113 | if (iio_buffer_enabled(idev)) { | |
114 | disable_irq_nosync(irq); | |
0e589d5f MR |
115 | iio_trigger_poll(idev->trig, iio_get_time_ns()); |
116 | } else { | |
117 | st->last_value = at91_adc_readl(st, AT91_ADC_LCDR); | |
118 | st->done = true; | |
119 | wake_up_interruptible(&st->wq_data_avail); | |
120 | } | |
121 | ||
122 | return IRQ_HANDLED; | |
123 | } | |
124 | ||
125 | static int at91_adc_channel_init(struct iio_dev *idev) | |
126 | { | |
127 | struct at91_adc_state *st = iio_priv(idev); | |
128 | struct iio_chan_spec *chan_array, *timestamp; | |
129 | int bit, idx = 0; | |
130 | ||
131 | idev->num_channels = bitmap_weight(&st->channels_mask, | |
132 | st->num_channels) + 1; | |
133 | ||
6b3aa313 AL |
134 | chan_array = devm_kzalloc(&idev->dev, |
135 | ((idev->num_channels + 1) * | |
136 | sizeof(struct iio_chan_spec)), | |
137 | GFP_KERNEL); | |
0e589d5f MR |
138 | |
139 | if (!chan_array) | |
140 | return -ENOMEM; | |
141 | ||
142 | for_each_set_bit(bit, &st->channels_mask, st->num_channels) { | |
143 | struct iio_chan_spec *chan = chan_array + idx; | |
144 | ||
145 | chan->type = IIO_VOLTAGE; | |
146 | chan->indexed = 1; | |
147 | chan->channel = bit; | |
148 | chan->scan_index = idx; | |
149 | chan->scan_type.sign = 'u'; | |
47be16b6 | 150 | chan->scan_type.realbits = st->res; |
0e589d5f | 151 | chan->scan_type.storagebits = 16; |
01bdab66 JC |
152 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); |
153 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); | |
0e589d5f MR |
154 | idx++; |
155 | } | |
156 | timestamp = chan_array + idx; | |
157 | ||
158 | timestamp->type = IIO_TIMESTAMP; | |
159 | timestamp->channel = -1; | |
160 | timestamp->scan_index = idx; | |
161 | timestamp->scan_type.sign = 's'; | |
162 | timestamp->scan_type.realbits = 64; | |
163 | timestamp->scan_type.storagebits = 64; | |
164 | ||
165 | idev->channels = chan_array; | |
166 | return idev->num_channels; | |
167 | } | |
168 | ||
169 | static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev, | |
170 | struct at91_adc_trigger *triggers, | |
171 | const char *trigger_name) | |
172 | { | |
173 | struct at91_adc_state *st = iio_priv(idev); | |
174 | u8 value = 0; | |
175 | int i; | |
176 | ||
177 | for (i = 0; i < st->trigger_number; i++) { | |
178 | char *name = kasprintf(GFP_KERNEL, | |
179 | "%s-dev%d-%s", | |
180 | idev->name, | |
181 | idev->id, | |
182 | triggers[i].name); | |
183 | if (!name) | |
184 | return -ENOMEM; | |
185 | ||
186 | if (strcmp(trigger_name, name) == 0) { | |
187 | value = triggers[i].value; | |
188 | kfree(name); | |
189 | break; | |
190 | } | |
191 | ||
192 | kfree(name); | |
193 | } | |
194 | ||
195 | return value; | |
196 | } | |
197 | ||
198 | static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) | |
199 | { | |
1e9663c6 | 200 | struct iio_dev *idev = iio_trigger_get_drvdata(trig); |
0e589d5f MR |
201 | struct at91_adc_state *st = iio_priv(idev); |
202 | struct iio_buffer *buffer = idev->buffer; | |
203 | struct at91_adc_reg_desc *reg = st->registers; | |
204 | u32 status = at91_adc_readl(st, reg->trigger_register); | |
205 | u8 value; | |
206 | u8 bit; | |
207 | ||
208 | value = at91_adc_get_trigger_value_by_name(idev, | |
209 | st->trigger_list, | |
210 | idev->trig->name); | |
211 | if (value == 0) | |
212 | return -EINVAL; | |
213 | ||
214 | if (state) { | |
215 | st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); | |
216 | if (st->buffer == NULL) | |
217 | return -ENOMEM; | |
218 | ||
219 | at91_adc_writel(st, reg->trigger_register, | |
220 | status | value); | |
221 | ||
222 | for_each_set_bit(bit, buffer->scan_mask, | |
223 | st->num_channels) { | |
224 | struct iio_chan_spec const *chan = idev->channels + bit; | |
225 | at91_adc_writel(st, AT91_ADC_CHER, | |
226 | AT91_ADC_CH(chan->channel)); | |
227 | } | |
228 | ||
229 | at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); | |
230 | ||
231 | } else { | |
232 | at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); | |
233 | ||
234 | at91_adc_writel(st, reg->trigger_register, | |
235 | status & ~value); | |
236 | ||
237 | for_each_set_bit(bit, buffer->scan_mask, | |
238 | st->num_channels) { | |
239 | struct iio_chan_spec const *chan = idev->channels + bit; | |
240 | at91_adc_writel(st, AT91_ADC_CHDR, | |
241 | AT91_ADC_CH(chan->channel)); | |
242 | } | |
243 | kfree(st->buffer); | |
244 | } | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | static const struct iio_trigger_ops at91_adc_trigger_ops = { | |
250 | .owner = THIS_MODULE, | |
251 | .set_trigger_state = &at91_adc_configure_trigger, | |
252 | }; | |
253 | ||
254 | static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, | |
255 | struct at91_adc_trigger *trigger) | |
256 | { | |
257 | struct iio_trigger *trig; | |
258 | int ret; | |
259 | ||
260 | trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, | |
261 | idev->id, trigger->name); | |
262 | if (trig == NULL) | |
263 | return NULL; | |
264 | ||
265 | trig->dev.parent = idev->dev.parent; | |
1e9663c6 | 266 | iio_trigger_set_drvdata(trig, idev); |
0e589d5f MR |
267 | trig->ops = &at91_adc_trigger_ops; |
268 | ||
269 | ret = iio_trigger_register(trig); | |
270 | if (ret) | |
271 | return NULL; | |
272 | ||
273 | return trig; | |
274 | } | |
275 | ||
276 | static int at91_adc_trigger_init(struct iio_dev *idev) | |
277 | { | |
278 | struct at91_adc_state *st = iio_priv(idev); | |
279 | int i, ret; | |
280 | ||
6b3aa313 AL |
281 | st->trig = devm_kzalloc(&idev->dev, |
282 | st->trigger_number * sizeof(st->trig), | |
283 | GFP_KERNEL); | |
0e589d5f MR |
284 | |
285 | if (st->trig == NULL) { | |
286 | ret = -ENOMEM; | |
287 | goto error_ret; | |
288 | } | |
289 | ||
290 | for (i = 0; i < st->trigger_number; i++) { | |
291 | if (st->trigger_list[i].is_external && !(st->use_external)) | |
292 | continue; | |
293 | ||
294 | st->trig[i] = at91_adc_allocate_trigger(idev, | |
295 | st->trigger_list + i); | |
296 | if (st->trig[i] == NULL) { | |
297 | dev_err(&idev->dev, | |
298 | "Could not allocate trigger %d\n", i); | |
299 | ret = -ENOMEM; | |
300 | goto error_trigger; | |
301 | } | |
302 | } | |
303 | ||
304 | return 0; | |
305 | ||
306 | error_trigger: | |
307 | for (i--; i >= 0; i--) { | |
308 | iio_trigger_unregister(st->trig[i]); | |
309 | iio_trigger_free(st->trig[i]); | |
310 | } | |
311 | error_ret: | |
312 | return ret; | |
313 | } | |
314 | ||
315 | static void at91_adc_trigger_remove(struct iio_dev *idev) | |
316 | { | |
317 | struct at91_adc_state *st = iio_priv(idev); | |
318 | int i; | |
319 | ||
320 | for (i = 0; i < st->trigger_number; i++) { | |
321 | iio_trigger_unregister(st->trig[i]); | |
322 | iio_trigger_free(st->trig[i]); | |
323 | } | |
324 | } | |
325 | ||
0e589d5f MR |
326 | static int at91_adc_buffer_init(struct iio_dev *idev) |
327 | { | |
90032e4e LPC |
328 | return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, |
329 | &at91_adc_trigger_handler, NULL); | |
0e589d5f MR |
330 | } |
331 | ||
332 | static void at91_adc_buffer_remove(struct iio_dev *idev) | |
333 | { | |
90032e4e | 334 | iio_triggered_buffer_cleanup(idev); |
0e589d5f MR |
335 | } |
336 | ||
337 | static int at91_adc_read_raw(struct iio_dev *idev, | |
338 | struct iio_chan_spec const *chan, | |
339 | int *val, int *val2, long mask) | |
340 | { | |
341 | struct at91_adc_state *st = iio_priv(idev); | |
342 | int ret; | |
343 | ||
344 | switch (mask) { | |
345 | case IIO_CHAN_INFO_RAW: | |
346 | mutex_lock(&st->lock); | |
347 | ||
348 | at91_adc_writel(st, AT91_ADC_CHER, | |
349 | AT91_ADC_CH(chan->channel)); | |
350 | at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask); | |
351 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); | |
352 | ||
353 | ret = wait_event_interruptible_timeout(st->wq_data_avail, | |
354 | st->done, | |
355 | msecs_to_jiffies(1000)); | |
356 | if (ret == 0) | |
90e6dc7c LPC |
357 | ret = -ETIMEDOUT; |
358 | if (ret < 0) { | |
359 | mutex_unlock(&st->lock); | |
0e589d5f | 360 | return ret; |
90e6dc7c | 361 | } |
0e589d5f MR |
362 | |
363 | *val = st->last_value; | |
364 | ||
365 | at91_adc_writel(st, AT91_ADC_CHDR, | |
366 | AT91_ADC_CH(chan->channel)); | |
367 | at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask); | |
368 | ||
369 | st->last_value = 0; | |
370 | st->done = false; | |
371 | mutex_unlock(&st->lock); | |
372 | return IIO_VAL_INT; | |
373 | ||
374 | case IIO_CHAN_INFO_SCALE: | |
375 | *val = (st->vref_mv * 1000) >> chan->scan_type.realbits; | |
376 | *val2 = 0; | |
377 | return IIO_VAL_INT_PLUS_MICRO; | |
378 | default: | |
379 | break; | |
380 | } | |
381 | return -EINVAL; | |
382 | } | |
383 | ||
47be16b6 LD |
384 | static int at91_adc_of_get_resolution(struct at91_adc_state *st, |
385 | struct platform_device *pdev) | |
386 | { | |
387 | struct iio_dev *idev = iio_priv_to_dev(st); | |
388 | struct device_node *np = pdev->dev.of_node; | |
389 | int count, i, ret = 0; | |
390 | char *res_name, *s; | |
391 | u32 *resolutions; | |
392 | ||
393 | count = of_property_count_strings(np, "atmel,adc-res-names"); | |
394 | if (count < 2) { | |
395 | dev_err(&idev->dev, "You must specified at least two resolution names for " | |
396 | "adc-res-names property in the DT\n"); | |
397 | return count; | |
398 | } | |
399 | ||
400 | resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL); | |
401 | if (!resolutions) | |
402 | return -ENOMEM; | |
403 | ||
404 | if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) { | |
405 | dev_err(&idev->dev, "Missing adc-res property in the DT.\n"); | |
406 | ret = -ENODEV; | |
407 | goto ret; | |
408 | } | |
409 | ||
410 | if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name)) | |
411 | res_name = "highres"; | |
412 | ||
413 | for (i = 0; i < count; i++) { | |
414 | if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s)) | |
415 | continue; | |
416 | ||
417 | if (strcmp(res_name, s)) | |
418 | continue; | |
419 | ||
420 | st->res = resolutions[i]; | |
421 | if (!strcmp(res_name, "lowres")) | |
422 | st->low_res = true; | |
423 | else | |
424 | st->low_res = false; | |
425 | ||
426 | dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); | |
427 | goto ret; | |
428 | } | |
429 | ||
430 | dev_err(&idev->dev, "There is no resolution for %s\n", res_name); | |
431 | ||
432 | ret: | |
433 | kfree(resolutions); | |
434 | return ret; | |
435 | } | |
436 | ||
e1811f97 JW |
437 | static const struct of_device_id at91_adc_dt_ids[]; |
438 | ||
e364185f MR |
439 | static int at91_adc_probe_dt(struct at91_adc_state *st, |
440 | struct platform_device *pdev) | |
441 | { | |
442 | struct iio_dev *idev = iio_priv_to_dev(st); | |
443 | struct device_node *node = pdev->dev.of_node; | |
444 | struct device_node *trig_node; | |
445 | int i = 0, ret; | |
446 | u32 prop; | |
447 | ||
448 | if (!node) | |
449 | return -EINVAL; | |
450 | ||
e1811f97 JW |
451 | st->caps = (struct at91_adc_caps *) |
452 | of_match_device(at91_adc_dt_ids, &pdev->dev)->data; | |
453 | ||
e364185f MR |
454 | st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); |
455 | ||
456 | if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { | |
457 | dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); | |
458 | ret = -EINVAL; | |
459 | goto error_ret; | |
460 | } | |
461 | st->channels_mask = prop; | |
462 | ||
463 | if (of_property_read_u32(node, "atmel,adc-num-channels", &prop)) { | |
464 | dev_err(&idev->dev, "Missing adc-num-channels property in the DT.\n"); | |
465 | ret = -EINVAL; | |
466 | goto error_ret; | |
467 | } | |
468 | st->num_channels = prop; | |
469 | ||
e748783c JCPV |
470 | st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); |
471 | ||
e364185f MR |
472 | if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { |
473 | dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); | |
474 | ret = -EINVAL; | |
475 | goto error_ret; | |
476 | } | |
477 | st->startup_time = prop; | |
478 | ||
beca9e76 JCPV |
479 | prop = 0; |
480 | of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); | |
481 | st->sample_hold_time = prop; | |
e364185f MR |
482 | |
483 | if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { | |
484 | dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); | |
485 | ret = -EINVAL; | |
486 | goto error_ret; | |
487 | } | |
488 | st->vref_mv = prop; | |
489 | ||
47be16b6 LD |
490 | ret = at91_adc_of_get_resolution(st, pdev); |
491 | if (ret) | |
492 | goto error_ret; | |
493 | ||
e1811f97 | 494 | st->registers = &st->caps->registers; |
e364185f | 495 | st->trigger_number = of_get_child_count(node); |
6b3aa313 AL |
496 | st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number * |
497 | sizeof(struct at91_adc_trigger), | |
498 | GFP_KERNEL); | |
e364185f MR |
499 | if (!st->trigger_list) { |
500 | dev_err(&idev->dev, "Could not allocate trigger list memory.\n"); | |
501 | ret = -ENOMEM; | |
502 | goto error_ret; | |
503 | } | |
504 | ||
505 | for_each_child_of_node(node, trig_node) { | |
506 | struct at91_adc_trigger *trig = st->trigger_list + i; | |
507 | const char *name; | |
508 | ||
509 | if (of_property_read_string(trig_node, "trigger-name", &name)) { | |
510 | dev_err(&idev->dev, "Missing trigger-name property in the DT.\n"); | |
511 | ret = -EINVAL; | |
512 | goto error_ret; | |
513 | } | |
514 | trig->name = name; | |
515 | ||
516 | if (of_property_read_u32(trig_node, "trigger-value", &prop)) { | |
517 | dev_err(&idev->dev, "Missing trigger-value property in the DT.\n"); | |
518 | ret = -EINVAL; | |
519 | goto error_ret; | |
520 | } | |
521 | trig->value = prop; | |
522 | trig->is_external = of_property_read_bool(trig_node, "trigger-external"); | |
523 | i++; | |
524 | } | |
525 | ||
526 | return 0; | |
527 | ||
528 | error_ret: | |
529 | return ret; | |
530 | } | |
531 | ||
0e589d5f MR |
532 | static int at91_adc_probe_pdata(struct at91_adc_state *st, |
533 | struct platform_device *pdev) | |
534 | { | |
535 | struct at91_adc_data *pdata = pdev->dev.platform_data; | |
536 | ||
537 | if (!pdata) | |
538 | return -EINVAL; | |
539 | ||
540 | st->use_external = pdata->use_external_triggers; | |
541 | st->vref_mv = pdata->vref; | |
542 | st->channels_mask = pdata->channels_used; | |
543 | st->num_channels = pdata->num_channels; | |
544 | st->startup_time = pdata->startup_time; | |
545 | st->trigger_number = pdata->trigger_number; | |
546 | st->trigger_list = pdata->trigger_list; | |
547 | st->registers = pdata->registers; | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | static const struct iio_info at91_adc_info = { | |
553 | .driver_module = THIS_MODULE, | |
554 | .read_raw = &at91_adc_read_raw, | |
555 | }; | |
556 | ||
fc52692c | 557 | static int at91_adc_probe(struct platform_device *pdev) |
0e589d5f | 558 | { |
db10e201 | 559 | unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; |
0e589d5f MR |
560 | int ret; |
561 | struct iio_dev *idev; | |
562 | struct at91_adc_state *st; | |
563 | struct resource *res; | |
e748783c | 564 | u32 reg; |
0e589d5f | 565 | |
f8837532 SK |
566 | idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); |
567 | if (!idev) | |
568 | return -ENOMEM; | |
0e589d5f MR |
569 | |
570 | st = iio_priv(idev); | |
571 | ||
e364185f MR |
572 | if (pdev->dev.of_node) |
573 | ret = at91_adc_probe_dt(st, pdev); | |
574 | else | |
575 | ret = at91_adc_probe_pdata(st, pdev); | |
576 | ||
0e589d5f MR |
577 | if (ret) { |
578 | dev_err(&pdev->dev, "No platform data available.\n"); | |
f8837532 | 579 | return -EINVAL; |
0e589d5f MR |
580 | } |
581 | ||
0e589d5f MR |
582 | platform_set_drvdata(pdev, idev); |
583 | ||
584 | idev->dev.parent = &pdev->dev; | |
585 | idev->name = dev_name(&pdev->dev); | |
586 | idev->modes = INDIO_DIRECT_MODE; | |
587 | idev->info = &at91_adc_info; | |
588 | ||
589 | st->irq = platform_get_irq(pdev, 0); | |
590 | if (st->irq < 0) { | |
591 | dev_err(&pdev->dev, "No IRQ ID is designated\n"); | |
f8837532 | 592 | return -ENODEV; |
0e589d5f MR |
593 | } |
594 | ||
390d75c1 | 595 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
0e589d5f | 596 | |
5fd98466 TR |
597 | st->reg_base = devm_ioremap_resource(&pdev->dev, res); |
598 | if (IS_ERR(st->reg_base)) { | |
f8837532 | 599 | return PTR_ERR(st->reg_base); |
0e589d5f MR |
600 | } |
601 | ||
602 | /* | |
603 | * Disable all IRQs before setting up the handler | |
604 | */ | |
605 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); | |
606 | at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); | |
607 | ret = request_irq(st->irq, | |
608 | at91_adc_eoc_trigger, | |
609 | 0, | |
610 | pdev->dev.driver->name, | |
611 | idev); | |
612 | if (ret) { | |
613 | dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); | |
f8837532 | 614 | return ret; |
0e589d5f MR |
615 | } |
616 | ||
390d75c1 | 617 | st->clk = devm_clk_get(&pdev->dev, "adc_clk"); |
0e589d5f MR |
618 | if (IS_ERR(st->clk)) { |
619 | dev_err(&pdev->dev, "Failed to get the clock.\n"); | |
620 | ret = PTR_ERR(st->clk); | |
621 | goto error_free_irq; | |
622 | } | |
623 | ||
00062a9c | 624 | ret = clk_prepare_enable(st->clk); |
0e589d5f | 625 | if (ret) { |
00062a9c JL |
626 | dev_err(&pdev->dev, |
627 | "Could not prepare or enable the clock.\n"); | |
390d75c1 | 628 | goto error_free_irq; |
0e589d5f MR |
629 | } |
630 | ||
390d75c1 | 631 | st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); |
0e589d5f MR |
632 | if (IS_ERR(st->adc_clk)) { |
633 | dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); | |
f755bbbf | 634 | ret = PTR_ERR(st->adc_clk); |
0e589d5f MR |
635 | goto error_disable_clk; |
636 | } | |
637 | ||
00062a9c | 638 | ret = clk_prepare_enable(st->adc_clk); |
0e589d5f | 639 | if (ret) { |
00062a9c JL |
640 | dev_err(&pdev->dev, |
641 | "Could not prepare or enable the ADC clock.\n"); | |
390d75c1 | 642 | goto error_disable_clk; |
0e589d5f MR |
643 | } |
644 | ||
0e589d5f MR |
645 | /* |
646 | * Prescaler rate computation using the formula from the Atmel's | |
647 | * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being | |
648 | * specified by the electrical characteristics of the board. | |
649 | */ | |
650 | mstrclk = clk_get_rate(st->clk); | |
651 | adc_clk = clk_get_rate(st->adc_clk); | |
db10e201 | 652 | adc_clk_khz = adc_clk / 1000; |
0e589d5f MR |
653 | prsc = (mstrclk / (2 * adc_clk)) - 1; |
654 | ||
655 | if (!st->startup_time) { | |
656 | dev_err(&pdev->dev, "No startup time available.\n"); | |
657 | ret = -EINVAL; | |
658 | goto error_disable_adc_clk; | |
659 | } | |
660 | ||
661 | /* | |
662 | * Number of ticks needed to cover the startup time of the ADC as | |
663 | * defined in the electrical characteristics of the board, divided by 8. | |
664 | * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock | |
665 | */ | |
db10e201 JW |
666 | ticks = round_up((st->startup_time * adc_clk_khz / |
667 | 1000) - 1, 8) / 8; | |
beca9e76 JCPV |
668 | /* |
669 | * a minimal Sample and Hold Time is necessary for the ADC to guarantee | |
670 | * the best converted final value between two channels selection | |
671 | * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock | |
672 | */ | |
db10e201 JW |
673 | shtim = round_up((st->sample_hold_time * adc_clk_khz / |
674 | 1000) - 1, 1); | |
beca9e76 | 675 | |
9120c0be JW |
676 | reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; |
677 | reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; | |
47be16b6 | 678 | if (st->low_res) |
e748783c JCPV |
679 | reg |= AT91_ADC_LOWRES; |
680 | if (st->sleep_mode) | |
681 | reg |= AT91_ADC_SLEEP; | |
beca9e76 | 682 | reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; |
e748783c | 683 | at91_adc_writel(st, AT91_ADC_MR, reg); |
0e589d5f MR |
684 | |
685 | /* Setup the ADC channels available on the board */ | |
686 | ret = at91_adc_channel_init(idev); | |
687 | if (ret < 0) { | |
688 | dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); | |
689 | goto error_disable_adc_clk; | |
690 | } | |
691 | ||
692 | init_waitqueue_head(&st->wq_data_avail); | |
693 | mutex_init(&st->lock); | |
694 | ||
695 | ret = at91_adc_buffer_init(idev); | |
696 | if (ret < 0) { | |
697 | dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); | |
698 | goto error_disable_adc_clk; | |
699 | } | |
700 | ||
701 | ret = at91_adc_trigger_init(idev); | |
702 | if (ret < 0) { | |
703 | dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); | |
704 | goto error_unregister_buffer; | |
705 | } | |
706 | ||
707 | ret = iio_device_register(idev); | |
708 | if (ret < 0) { | |
709 | dev_err(&pdev->dev, "Couldn't register the device.\n"); | |
710 | goto error_remove_triggers; | |
711 | } | |
712 | ||
713 | return 0; | |
714 | ||
715 | error_remove_triggers: | |
716 | at91_adc_trigger_remove(idev); | |
717 | error_unregister_buffer: | |
718 | at91_adc_buffer_remove(idev); | |
719 | error_disable_adc_clk: | |
00062a9c | 720 | clk_disable_unprepare(st->adc_clk); |
0e589d5f | 721 | error_disable_clk: |
00062a9c | 722 | clk_disable_unprepare(st->clk); |
0e589d5f MR |
723 | error_free_irq: |
724 | free_irq(st->irq, idev); | |
0e589d5f MR |
725 | return ret; |
726 | } | |
727 | ||
fc52692c | 728 | static int at91_adc_remove(struct platform_device *pdev) |
0e589d5f MR |
729 | { |
730 | struct iio_dev *idev = platform_get_drvdata(pdev); | |
0e589d5f MR |
731 | struct at91_adc_state *st = iio_priv(idev); |
732 | ||
733 | iio_device_unregister(idev); | |
734 | at91_adc_trigger_remove(idev); | |
735 | at91_adc_buffer_remove(idev); | |
736 | clk_disable_unprepare(st->adc_clk); | |
00062a9c | 737 | clk_disable_unprepare(st->clk); |
0e589d5f | 738 | free_irq(st->irq, idev); |
0e589d5f MR |
739 | |
740 | return 0; | |
741 | } | |
742 | ||
00738ff6 | 743 | #ifdef CONFIG_OF |
e1811f97 JW |
744 | static struct at91_adc_caps at91sam9260_caps = { |
745 | .registers = { | |
746 | .channel_base = AT91_ADC_CHR(0), | |
747 | .drdy_mask = AT91_ADC_DRDY, | |
748 | .status_register = AT91_ADC_SR, | |
749 | .trigger_register = AT91_ADC_TRGR_9260, | |
9120c0be JW |
750 | .mr_prescal_mask = AT91_ADC_PRESCAL_9260, |
751 | .mr_startup_mask = AT91_ADC_STARTUP_9260, | |
e1811f97 JW |
752 | }, |
753 | }; | |
754 | ||
755 | static struct at91_adc_caps at91sam9g45_caps = { | |
756 | .registers = { | |
757 | .channel_base = AT91_ADC_CHR(0), | |
758 | .drdy_mask = AT91_ADC_DRDY, | |
759 | .status_register = AT91_ADC_SR, | |
760 | .trigger_register = AT91_ADC_TRGR_9G45, | |
9120c0be JW |
761 | .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, |
762 | .mr_startup_mask = AT91_ADC_STARTUP_9G45, | |
e1811f97 JW |
763 | }, |
764 | }; | |
765 | ||
766 | static struct at91_adc_caps at91sam9x5_caps = { | |
767 | .registers = { | |
768 | .channel_base = AT91_ADC_CDR0_9X5, | |
769 | .drdy_mask = AT91_ADC_SR_DRDY_9X5, | |
770 | .status_register = AT91_ADC_SR_9X5, | |
771 | .trigger_register = AT91_ADC_TRGR_9X5, | |
9120c0be JW |
772 | /* prescal mask is same as 9G45 */ |
773 | .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, | |
774 | .mr_startup_mask = AT91_ADC_STARTUP_9X5, | |
e1811f97 JW |
775 | }, |
776 | }; | |
777 | ||
e364185f | 778 | static const struct of_device_id at91_adc_dt_ids[] = { |
e1811f97 JW |
779 | { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps }, |
780 | { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps }, | |
781 | { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps }, | |
e364185f MR |
782 | {}, |
783 | }; | |
784 | MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); | |
00738ff6 | 785 | #endif |
e364185f | 786 | |
0e589d5f MR |
787 | static struct platform_driver at91_adc_driver = { |
788 | .probe = at91_adc_probe, | |
fc52692c | 789 | .remove = at91_adc_remove, |
0e589d5f MR |
790 | .driver = { |
791 | .name = "at91_adc", | |
e364185f | 792 | .of_match_table = of_match_ptr(at91_adc_dt_ids), |
0e589d5f MR |
793 | }, |
794 | }; | |
795 | ||
796 | module_platform_driver(at91_adc_driver); | |
797 | ||
798 | MODULE_LICENSE("GPL"); | |
799 | MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); | |
800 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |