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0e589d5f MR |
1 | /* |
2 | * Driver for the ADC present in the Atmel AT91 evaluation boards. | |
3 | * | |
4 | * Copyright 2011 Free Electrons | |
5 | * | |
6 | * Licensed under the GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/bitmap.h> | |
10 | #include <linux/bitops.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
e364185f MR |
18 | #include <linux/of.h> |
19 | #include <linux/of_device.h> | |
0e589d5f MR |
20 | #include <linux/platform_device.h> |
21 | #include <linux/sched.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/wait.h> | |
24 | ||
25 | #include <linux/platform_data/at91_adc.h> | |
26 | ||
27 | #include <linux/iio/iio.h> | |
28 | #include <linux/iio/buffer.h> | |
0e589d5f MR |
29 | #include <linux/iio/trigger.h> |
30 | #include <linux/iio/trigger_consumer.h> | |
90032e4e | 31 | #include <linux/iio/triggered_buffer.h> |
0e589d5f MR |
32 | |
33 | #include <mach/at91_adc.h> | |
34 | ||
35 | #define AT91_ADC_CHAN(st, ch) \ | |
36 | (st->registers->channel_base + (ch * 4)) | |
37 | #define at91_adc_readl(st, reg) \ | |
38 | (readl_relaxed(st->reg_base + reg)) | |
39 | #define at91_adc_writel(st, reg, val) \ | |
40 | (writel_relaxed(val, st->reg_base + reg)) | |
41 | ||
42 | struct at91_adc_state { | |
43 | struct clk *adc_clk; | |
44 | u16 *buffer; | |
45 | unsigned long channels_mask; | |
46 | struct clk *clk; | |
47 | bool done; | |
48 | int irq; | |
0e589d5f MR |
49 | u16 last_value; |
50 | struct mutex lock; | |
51 | u8 num_channels; | |
52 | void __iomem *reg_base; | |
53 | struct at91_adc_reg_desc *registers; | |
54 | u8 startup_time; | |
e748783c | 55 | bool sleep_mode; |
0e589d5f MR |
56 | struct iio_trigger **trig; |
57 | struct at91_adc_trigger *trigger_list; | |
58 | u32 trigger_number; | |
59 | bool use_external; | |
60 | u32 vref_mv; | |
47be16b6 LD |
61 | u32 res; /* resolution used for convertions */ |
62 | bool low_res; /* the resolution corresponds to the lowest one */ | |
0e589d5f MR |
63 | wait_queue_head_t wq_data_avail; |
64 | }; | |
65 | ||
66 | static irqreturn_t at91_adc_trigger_handler(int irq, void *p) | |
67 | { | |
68 | struct iio_poll_func *pf = p; | |
69 | struct iio_dev *idev = pf->indio_dev; | |
70 | struct at91_adc_state *st = iio_priv(idev); | |
0e589d5f MR |
71 | int i, j = 0; |
72 | ||
73 | for (i = 0; i < idev->masklength; i++) { | |
74 | if (!test_bit(i, idev->active_scan_mask)) | |
75 | continue; | |
76 | st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i)); | |
77 | j++; | |
78 | } | |
79 | ||
80 | if (idev->scan_timestamp) { | |
81 | s64 *timestamp = (s64 *)((u8 *)st->buffer + | |
82 | ALIGN(j, sizeof(s64))); | |
83 | *timestamp = pf->timestamp; | |
84 | } | |
85 | ||
11679767 | 86 | iio_push_to_buffers(idev, (u8 *)st->buffer); |
0e589d5f MR |
87 | |
88 | iio_trigger_notify_done(idev->trig); | |
0e589d5f MR |
89 | |
90 | /* Needed to ACK the DRDY interruption */ | |
91 | at91_adc_readl(st, AT91_ADC_LCDR); | |
92 | ||
93 | enable_irq(st->irq); | |
94 | ||
95 | return IRQ_HANDLED; | |
96 | } | |
97 | ||
98 | static irqreturn_t at91_adc_eoc_trigger(int irq, void *private) | |
99 | { | |
100 | struct iio_dev *idev = private; | |
101 | struct at91_adc_state *st = iio_priv(idev); | |
102 | u32 status = at91_adc_readl(st, st->registers->status_register); | |
103 | ||
104 | if (!(status & st->registers->drdy_mask)) | |
105 | return IRQ_HANDLED; | |
106 | ||
107 | if (iio_buffer_enabled(idev)) { | |
108 | disable_irq_nosync(irq); | |
0e589d5f MR |
109 | iio_trigger_poll(idev->trig, iio_get_time_ns()); |
110 | } else { | |
111 | st->last_value = at91_adc_readl(st, AT91_ADC_LCDR); | |
112 | st->done = true; | |
113 | wake_up_interruptible(&st->wq_data_avail); | |
114 | } | |
115 | ||
116 | return IRQ_HANDLED; | |
117 | } | |
118 | ||
119 | static int at91_adc_channel_init(struct iio_dev *idev) | |
120 | { | |
121 | struct at91_adc_state *st = iio_priv(idev); | |
122 | struct iio_chan_spec *chan_array, *timestamp; | |
123 | int bit, idx = 0; | |
124 | ||
125 | idev->num_channels = bitmap_weight(&st->channels_mask, | |
126 | st->num_channels) + 1; | |
127 | ||
6b3aa313 AL |
128 | chan_array = devm_kzalloc(&idev->dev, |
129 | ((idev->num_channels + 1) * | |
130 | sizeof(struct iio_chan_spec)), | |
131 | GFP_KERNEL); | |
0e589d5f MR |
132 | |
133 | if (!chan_array) | |
134 | return -ENOMEM; | |
135 | ||
136 | for_each_set_bit(bit, &st->channels_mask, st->num_channels) { | |
137 | struct iio_chan_spec *chan = chan_array + idx; | |
138 | ||
139 | chan->type = IIO_VOLTAGE; | |
140 | chan->indexed = 1; | |
141 | chan->channel = bit; | |
142 | chan->scan_index = idx; | |
143 | chan->scan_type.sign = 'u'; | |
47be16b6 | 144 | chan->scan_type.realbits = st->res; |
0e589d5f | 145 | chan->scan_type.storagebits = 16; |
01bdab66 JC |
146 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); |
147 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); | |
0e589d5f MR |
148 | idx++; |
149 | } | |
150 | timestamp = chan_array + idx; | |
151 | ||
152 | timestamp->type = IIO_TIMESTAMP; | |
153 | timestamp->channel = -1; | |
154 | timestamp->scan_index = idx; | |
155 | timestamp->scan_type.sign = 's'; | |
156 | timestamp->scan_type.realbits = 64; | |
157 | timestamp->scan_type.storagebits = 64; | |
158 | ||
159 | idev->channels = chan_array; | |
160 | return idev->num_channels; | |
161 | } | |
162 | ||
163 | static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev, | |
164 | struct at91_adc_trigger *triggers, | |
165 | const char *trigger_name) | |
166 | { | |
167 | struct at91_adc_state *st = iio_priv(idev); | |
168 | u8 value = 0; | |
169 | int i; | |
170 | ||
171 | for (i = 0; i < st->trigger_number; i++) { | |
172 | char *name = kasprintf(GFP_KERNEL, | |
173 | "%s-dev%d-%s", | |
174 | idev->name, | |
175 | idev->id, | |
176 | triggers[i].name); | |
177 | if (!name) | |
178 | return -ENOMEM; | |
179 | ||
180 | if (strcmp(trigger_name, name) == 0) { | |
181 | value = triggers[i].value; | |
182 | kfree(name); | |
183 | break; | |
184 | } | |
185 | ||
186 | kfree(name); | |
187 | } | |
188 | ||
189 | return value; | |
190 | } | |
191 | ||
192 | static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) | |
193 | { | |
1e9663c6 | 194 | struct iio_dev *idev = iio_trigger_get_drvdata(trig); |
0e589d5f MR |
195 | struct at91_adc_state *st = iio_priv(idev); |
196 | struct iio_buffer *buffer = idev->buffer; | |
197 | struct at91_adc_reg_desc *reg = st->registers; | |
198 | u32 status = at91_adc_readl(st, reg->trigger_register); | |
199 | u8 value; | |
200 | u8 bit; | |
201 | ||
202 | value = at91_adc_get_trigger_value_by_name(idev, | |
203 | st->trigger_list, | |
204 | idev->trig->name); | |
205 | if (value == 0) | |
206 | return -EINVAL; | |
207 | ||
208 | if (state) { | |
209 | st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); | |
210 | if (st->buffer == NULL) | |
211 | return -ENOMEM; | |
212 | ||
213 | at91_adc_writel(st, reg->trigger_register, | |
214 | status | value); | |
215 | ||
216 | for_each_set_bit(bit, buffer->scan_mask, | |
217 | st->num_channels) { | |
218 | struct iio_chan_spec const *chan = idev->channels + bit; | |
219 | at91_adc_writel(st, AT91_ADC_CHER, | |
220 | AT91_ADC_CH(chan->channel)); | |
221 | } | |
222 | ||
223 | at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); | |
224 | ||
225 | } else { | |
226 | at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); | |
227 | ||
228 | at91_adc_writel(st, reg->trigger_register, | |
229 | status & ~value); | |
230 | ||
231 | for_each_set_bit(bit, buffer->scan_mask, | |
232 | st->num_channels) { | |
233 | struct iio_chan_spec const *chan = idev->channels + bit; | |
234 | at91_adc_writel(st, AT91_ADC_CHDR, | |
235 | AT91_ADC_CH(chan->channel)); | |
236 | } | |
237 | kfree(st->buffer); | |
238 | } | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
243 | static const struct iio_trigger_ops at91_adc_trigger_ops = { | |
244 | .owner = THIS_MODULE, | |
245 | .set_trigger_state = &at91_adc_configure_trigger, | |
246 | }; | |
247 | ||
248 | static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, | |
249 | struct at91_adc_trigger *trigger) | |
250 | { | |
251 | struct iio_trigger *trig; | |
252 | int ret; | |
253 | ||
254 | trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, | |
255 | idev->id, trigger->name); | |
256 | if (trig == NULL) | |
257 | return NULL; | |
258 | ||
259 | trig->dev.parent = idev->dev.parent; | |
1e9663c6 | 260 | iio_trigger_set_drvdata(trig, idev); |
0e589d5f MR |
261 | trig->ops = &at91_adc_trigger_ops; |
262 | ||
263 | ret = iio_trigger_register(trig); | |
264 | if (ret) | |
265 | return NULL; | |
266 | ||
267 | return trig; | |
268 | } | |
269 | ||
270 | static int at91_adc_trigger_init(struct iio_dev *idev) | |
271 | { | |
272 | struct at91_adc_state *st = iio_priv(idev); | |
273 | int i, ret; | |
274 | ||
6b3aa313 AL |
275 | st->trig = devm_kzalloc(&idev->dev, |
276 | st->trigger_number * sizeof(st->trig), | |
277 | GFP_KERNEL); | |
0e589d5f MR |
278 | |
279 | if (st->trig == NULL) { | |
280 | ret = -ENOMEM; | |
281 | goto error_ret; | |
282 | } | |
283 | ||
284 | for (i = 0; i < st->trigger_number; i++) { | |
285 | if (st->trigger_list[i].is_external && !(st->use_external)) | |
286 | continue; | |
287 | ||
288 | st->trig[i] = at91_adc_allocate_trigger(idev, | |
289 | st->trigger_list + i); | |
290 | if (st->trig[i] == NULL) { | |
291 | dev_err(&idev->dev, | |
292 | "Could not allocate trigger %d\n", i); | |
293 | ret = -ENOMEM; | |
294 | goto error_trigger; | |
295 | } | |
296 | } | |
297 | ||
298 | return 0; | |
299 | ||
300 | error_trigger: | |
301 | for (i--; i >= 0; i--) { | |
302 | iio_trigger_unregister(st->trig[i]); | |
303 | iio_trigger_free(st->trig[i]); | |
304 | } | |
305 | error_ret: | |
306 | return ret; | |
307 | } | |
308 | ||
309 | static void at91_adc_trigger_remove(struct iio_dev *idev) | |
310 | { | |
311 | struct at91_adc_state *st = iio_priv(idev); | |
312 | int i; | |
313 | ||
314 | for (i = 0; i < st->trigger_number; i++) { | |
315 | iio_trigger_unregister(st->trig[i]); | |
316 | iio_trigger_free(st->trig[i]); | |
317 | } | |
318 | } | |
319 | ||
0e589d5f MR |
320 | static int at91_adc_buffer_init(struct iio_dev *idev) |
321 | { | |
90032e4e LPC |
322 | return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, |
323 | &at91_adc_trigger_handler, NULL); | |
0e589d5f MR |
324 | } |
325 | ||
326 | static void at91_adc_buffer_remove(struct iio_dev *idev) | |
327 | { | |
90032e4e | 328 | iio_triggered_buffer_cleanup(idev); |
0e589d5f MR |
329 | } |
330 | ||
331 | static int at91_adc_read_raw(struct iio_dev *idev, | |
332 | struct iio_chan_spec const *chan, | |
333 | int *val, int *val2, long mask) | |
334 | { | |
335 | struct at91_adc_state *st = iio_priv(idev); | |
336 | int ret; | |
337 | ||
338 | switch (mask) { | |
339 | case IIO_CHAN_INFO_RAW: | |
340 | mutex_lock(&st->lock); | |
341 | ||
342 | at91_adc_writel(st, AT91_ADC_CHER, | |
343 | AT91_ADC_CH(chan->channel)); | |
344 | at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask); | |
345 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); | |
346 | ||
347 | ret = wait_event_interruptible_timeout(st->wq_data_avail, | |
348 | st->done, | |
349 | msecs_to_jiffies(1000)); | |
350 | if (ret == 0) | |
90e6dc7c LPC |
351 | ret = -ETIMEDOUT; |
352 | if (ret < 0) { | |
353 | mutex_unlock(&st->lock); | |
0e589d5f | 354 | return ret; |
90e6dc7c | 355 | } |
0e589d5f MR |
356 | |
357 | *val = st->last_value; | |
358 | ||
359 | at91_adc_writel(st, AT91_ADC_CHDR, | |
360 | AT91_ADC_CH(chan->channel)); | |
361 | at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask); | |
362 | ||
363 | st->last_value = 0; | |
364 | st->done = false; | |
365 | mutex_unlock(&st->lock); | |
366 | return IIO_VAL_INT; | |
367 | ||
368 | case IIO_CHAN_INFO_SCALE: | |
369 | *val = (st->vref_mv * 1000) >> chan->scan_type.realbits; | |
370 | *val2 = 0; | |
371 | return IIO_VAL_INT_PLUS_MICRO; | |
372 | default: | |
373 | break; | |
374 | } | |
375 | return -EINVAL; | |
376 | } | |
377 | ||
47be16b6 LD |
378 | static int at91_adc_of_get_resolution(struct at91_adc_state *st, |
379 | struct platform_device *pdev) | |
380 | { | |
381 | struct iio_dev *idev = iio_priv_to_dev(st); | |
382 | struct device_node *np = pdev->dev.of_node; | |
383 | int count, i, ret = 0; | |
384 | char *res_name, *s; | |
385 | u32 *resolutions; | |
386 | ||
387 | count = of_property_count_strings(np, "atmel,adc-res-names"); | |
388 | if (count < 2) { | |
389 | dev_err(&idev->dev, "You must specified at least two resolution names for " | |
390 | "adc-res-names property in the DT\n"); | |
391 | return count; | |
392 | } | |
393 | ||
394 | resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL); | |
395 | if (!resolutions) | |
396 | return -ENOMEM; | |
397 | ||
398 | if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) { | |
399 | dev_err(&idev->dev, "Missing adc-res property in the DT.\n"); | |
400 | ret = -ENODEV; | |
401 | goto ret; | |
402 | } | |
403 | ||
404 | if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name)) | |
405 | res_name = "highres"; | |
406 | ||
407 | for (i = 0; i < count; i++) { | |
408 | if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s)) | |
409 | continue; | |
410 | ||
411 | if (strcmp(res_name, s)) | |
412 | continue; | |
413 | ||
414 | st->res = resolutions[i]; | |
415 | if (!strcmp(res_name, "lowres")) | |
416 | st->low_res = true; | |
417 | else | |
418 | st->low_res = false; | |
419 | ||
420 | dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); | |
421 | goto ret; | |
422 | } | |
423 | ||
424 | dev_err(&idev->dev, "There is no resolution for %s\n", res_name); | |
425 | ||
426 | ret: | |
427 | kfree(resolutions); | |
428 | return ret; | |
429 | } | |
430 | ||
e364185f MR |
431 | static int at91_adc_probe_dt(struct at91_adc_state *st, |
432 | struct platform_device *pdev) | |
433 | { | |
434 | struct iio_dev *idev = iio_priv_to_dev(st); | |
435 | struct device_node *node = pdev->dev.of_node; | |
436 | struct device_node *trig_node; | |
437 | int i = 0, ret; | |
438 | u32 prop; | |
439 | ||
440 | if (!node) | |
441 | return -EINVAL; | |
442 | ||
443 | st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); | |
444 | ||
445 | if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { | |
446 | dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); | |
447 | ret = -EINVAL; | |
448 | goto error_ret; | |
449 | } | |
450 | st->channels_mask = prop; | |
451 | ||
452 | if (of_property_read_u32(node, "atmel,adc-num-channels", &prop)) { | |
453 | dev_err(&idev->dev, "Missing adc-num-channels property in the DT.\n"); | |
454 | ret = -EINVAL; | |
455 | goto error_ret; | |
456 | } | |
457 | st->num_channels = prop; | |
458 | ||
e748783c JCPV |
459 | st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); |
460 | ||
e364185f MR |
461 | if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { |
462 | dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); | |
463 | ret = -EINVAL; | |
464 | goto error_ret; | |
465 | } | |
466 | st->startup_time = prop; | |
467 | ||
468 | ||
469 | if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { | |
470 | dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); | |
471 | ret = -EINVAL; | |
472 | goto error_ret; | |
473 | } | |
474 | st->vref_mv = prop; | |
475 | ||
47be16b6 LD |
476 | ret = at91_adc_of_get_resolution(st, pdev); |
477 | if (ret) | |
478 | goto error_ret; | |
479 | ||
e364185f MR |
480 | st->registers = devm_kzalloc(&idev->dev, |
481 | sizeof(struct at91_adc_reg_desc), | |
482 | GFP_KERNEL); | |
483 | if (!st->registers) { | |
484 | dev_err(&idev->dev, "Could not allocate register memory.\n"); | |
485 | ret = -ENOMEM; | |
486 | goto error_ret; | |
487 | } | |
488 | ||
489 | if (of_property_read_u32(node, "atmel,adc-channel-base", &prop)) { | |
490 | dev_err(&idev->dev, "Missing adc-channel-base property in the DT.\n"); | |
491 | ret = -EINVAL; | |
492 | goto error_ret; | |
493 | } | |
494 | st->registers->channel_base = prop; | |
495 | ||
496 | if (of_property_read_u32(node, "atmel,adc-drdy-mask", &prop)) { | |
497 | dev_err(&idev->dev, "Missing adc-drdy-mask property in the DT.\n"); | |
498 | ret = -EINVAL; | |
499 | goto error_ret; | |
500 | } | |
501 | st->registers->drdy_mask = prop; | |
502 | ||
503 | if (of_property_read_u32(node, "atmel,adc-status-register", &prop)) { | |
504 | dev_err(&idev->dev, "Missing adc-status-register property in the DT.\n"); | |
505 | ret = -EINVAL; | |
506 | goto error_ret; | |
507 | } | |
508 | st->registers->status_register = prop; | |
509 | ||
510 | if (of_property_read_u32(node, "atmel,adc-trigger-register", &prop)) { | |
511 | dev_err(&idev->dev, "Missing adc-trigger-register property in the DT.\n"); | |
512 | ret = -EINVAL; | |
513 | goto error_ret; | |
514 | } | |
515 | st->registers->trigger_register = prop; | |
516 | ||
517 | st->trigger_number = of_get_child_count(node); | |
6b3aa313 AL |
518 | st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number * |
519 | sizeof(struct at91_adc_trigger), | |
520 | GFP_KERNEL); | |
e364185f MR |
521 | if (!st->trigger_list) { |
522 | dev_err(&idev->dev, "Could not allocate trigger list memory.\n"); | |
523 | ret = -ENOMEM; | |
524 | goto error_ret; | |
525 | } | |
526 | ||
527 | for_each_child_of_node(node, trig_node) { | |
528 | struct at91_adc_trigger *trig = st->trigger_list + i; | |
529 | const char *name; | |
530 | ||
531 | if (of_property_read_string(trig_node, "trigger-name", &name)) { | |
532 | dev_err(&idev->dev, "Missing trigger-name property in the DT.\n"); | |
533 | ret = -EINVAL; | |
534 | goto error_ret; | |
535 | } | |
536 | trig->name = name; | |
537 | ||
538 | if (of_property_read_u32(trig_node, "trigger-value", &prop)) { | |
539 | dev_err(&idev->dev, "Missing trigger-value property in the DT.\n"); | |
540 | ret = -EINVAL; | |
541 | goto error_ret; | |
542 | } | |
543 | trig->value = prop; | |
544 | trig->is_external = of_property_read_bool(trig_node, "trigger-external"); | |
545 | i++; | |
546 | } | |
547 | ||
548 | return 0; | |
549 | ||
550 | error_ret: | |
551 | return ret; | |
552 | } | |
553 | ||
0e589d5f MR |
554 | static int at91_adc_probe_pdata(struct at91_adc_state *st, |
555 | struct platform_device *pdev) | |
556 | { | |
557 | struct at91_adc_data *pdata = pdev->dev.platform_data; | |
558 | ||
559 | if (!pdata) | |
560 | return -EINVAL; | |
561 | ||
562 | st->use_external = pdata->use_external_triggers; | |
563 | st->vref_mv = pdata->vref; | |
564 | st->channels_mask = pdata->channels_used; | |
565 | st->num_channels = pdata->num_channels; | |
566 | st->startup_time = pdata->startup_time; | |
567 | st->trigger_number = pdata->trigger_number; | |
568 | st->trigger_list = pdata->trigger_list; | |
569 | st->registers = pdata->registers; | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | static const struct iio_info at91_adc_info = { | |
575 | .driver_module = THIS_MODULE, | |
576 | .read_raw = &at91_adc_read_raw, | |
577 | }; | |
578 | ||
fc52692c | 579 | static int at91_adc_probe(struct platform_device *pdev) |
0e589d5f MR |
580 | { |
581 | unsigned int prsc, mstrclk, ticks, adc_clk; | |
582 | int ret; | |
583 | struct iio_dev *idev; | |
584 | struct at91_adc_state *st; | |
585 | struct resource *res; | |
e748783c | 586 | u32 reg; |
0e589d5f MR |
587 | |
588 | idev = iio_device_alloc(sizeof(struct at91_adc_state)); | |
589 | if (idev == NULL) { | |
590 | ret = -ENOMEM; | |
591 | goto error_ret; | |
592 | } | |
593 | ||
594 | st = iio_priv(idev); | |
595 | ||
e364185f MR |
596 | if (pdev->dev.of_node) |
597 | ret = at91_adc_probe_dt(st, pdev); | |
598 | else | |
599 | ret = at91_adc_probe_pdata(st, pdev); | |
600 | ||
0e589d5f MR |
601 | if (ret) { |
602 | dev_err(&pdev->dev, "No platform data available.\n"); | |
603 | ret = -EINVAL; | |
604 | goto error_free_device; | |
605 | } | |
606 | ||
0e589d5f MR |
607 | platform_set_drvdata(pdev, idev); |
608 | ||
609 | idev->dev.parent = &pdev->dev; | |
610 | idev->name = dev_name(&pdev->dev); | |
611 | idev->modes = INDIO_DIRECT_MODE; | |
612 | idev->info = &at91_adc_info; | |
613 | ||
614 | st->irq = platform_get_irq(pdev, 0); | |
615 | if (st->irq < 0) { | |
616 | dev_err(&pdev->dev, "No IRQ ID is designated\n"); | |
617 | ret = -ENODEV; | |
618 | goto error_free_device; | |
619 | } | |
620 | ||
390d75c1 | 621 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
0e589d5f | 622 | |
5fd98466 TR |
623 | st->reg_base = devm_ioremap_resource(&pdev->dev, res); |
624 | if (IS_ERR(st->reg_base)) { | |
625 | ret = PTR_ERR(st->reg_base); | |
390d75c1 | 626 | goto error_free_device; |
0e589d5f MR |
627 | } |
628 | ||
629 | /* | |
630 | * Disable all IRQs before setting up the handler | |
631 | */ | |
632 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); | |
633 | at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); | |
634 | ret = request_irq(st->irq, | |
635 | at91_adc_eoc_trigger, | |
636 | 0, | |
637 | pdev->dev.driver->name, | |
638 | idev); | |
639 | if (ret) { | |
640 | dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); | |
390d75c1 | 641 | goto error_free_device; |
0e589d5f MR |
642 | } |
643 | ||
390d75c1 | 644 | st->clk = devm_clk_get(&pdev->dev, "adc_clk"); |
0e589d5f MR |
645 | if (IS_ERR(st->clk)) { |
646 | dev_err(&pdev->dev, "Failed to get the clock.\n"); | |
647 | ret = PTR_ERR(st->clk); | |
648 | goto error_free_irq; | |
649 | } | |
650 | ||
00062a9c | 651 | ret = clk_prepare_enable(st->clk); |
0e589d5f | 652 | if (ret) { |
00062a9c JL |
653 | dev_err(&pdev->dev, |
654 | "Could not prepare or enable the clock.\n"); | |
390d75c1 | 655 | goto error_free_irq; |
0e589d5f MR |
656 | } |
657 | ||
390d75c1 | 658 | st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); |
0e589d5f MR |
659 | if (IS_ERR(st->adc_clk)) { |
660 | dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); | |
f755bbbf | 661 | ret = PTR_ERR(st->adc_clk); |
0e589d5f MR |
662 | goto error_disable_clk; |
663 | } | |
664 | ||
00062a9c | 665 | ret = clk_prepare_enable(st->adc_clk); |
0e589d5f | 666 | if (ret) { |
00062a9c JL |
667 | dev_err(&pdev->dev, |
668 | "Could not prepare or enable the ADC clock.\n"); | |
390d75c1 | 669 | goto error_disable_clk; |
0e589d5f MR |
670 | } |
671 | ||
0e589d5f MR |
672 | /* |
673 | * Prescaler rate computation using the formula from the Atmel's | |
674 | * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being | |
675 | * specified by the electrical characteristics of the board. | |
676 | */ | |
677 | mstrclk = clk_get_rate(st->clk); | |
678 | adc_clk = clk_get_rate(st->adc_clk); | |
679 | prsc = (mstrclk / (2 * adc_clk)) - 1; | |
680 | ||
681 | if (!st->startup_time) { | |
682 | dev_err(&pdev->dev, "No startup time available.\n"); | |
683 | ret = -EINVAL; | |
684 | goto error_disable_adc_clk; | |
685 | } | |
686 | ||
687 | /* | |
688 | * Number of ticks needed to cover the startup time of the ADC as | |
689 | * defined in the electrical characteristics of the board, divided by 8. | |
690 | * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock | |
691 | */ | |
692 | ticks = round_up((st->startup_time * adc_clk / | |
693 | 1000000) - 1, 8) / 8; | |
e748783c JCPV |
694 | reg = AT91_ADC_PRESCAL_(prsc) & AT91_ADC_PRESCAL; |
695 | reg |= AT91_ADC_STARTUP_(ticks) & AT91_ADC_STARTUP; | |
47be16b6 | 696 | if (st->low_res) |
e748783c JCPV |
697 | reg |= AT91_ADC_LOWRES; |
698 | if (st->sleep_mode) | |
699 | reg |= AT91_ADC_SLEEP; | |
700 | at91_adc_writel(st, AT91_ADC_MR, reg); | |
0e589d5f MR |
701 | |
702 | /* Setup the ADC channels available on the board */ | |
703 | ret = at91_adc_channel_init(idev); | |
704 | if (ret < 0) { | |
705 | dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); | |
706 | goto error_disable_adc_clk; | |
707 | } | |
708 | ||
709 | init_waitqueue_head(&st->wq_data_avail); | |
710 | mutex_init(&st->lock); | |
711 | ||
712 | ret = at91_adc_buffer_init(idev); | |
713 | if (ret < 0) { | |
714 | dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); | |
715 | goto error_disable_adc_clk; | |
716 | } | |
717 | ||
718 | ret = at91_adc_trigger_init(idev); | |
719 | if (ret < 0) { | |
720 | dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); | |
721 | goto error_unregister_buffer; | |
722 | } | |
723 | ||
724 | ret = iio_device_register(idev); | |
725 | if (ret < 0) { | |
726 | dev_err(&pdev->dev, "Couldn't register the device.\n"); | |
727 | goto error_remove_triggers; | |
728 | } | |
729 | ||
730 | return 0; | |
731 | ||
732 | error_remove_triggers: | |
733 | at91_adc_trigger_remove(idev); | |
734 | error_unregister_buffer: | |
735 | at91_adc_buffer_remove(idev); | |
736 | error_disable_adc_clk: | |
00062a9c | 737 | clk_disable_unprepare(st->adc_clk); |
0e589d5f | 738 | error_disable_clk: |
00062a9c | 739 | clk_disable_unprepare(st->clk); |
0e589d5f MR |
740 | error_free_irq: |
741 | free_irq(st->irq, idev); | |
0e589d5f MR |
742 | error_free_device: |
743 | iio_device_free(idev); | |
744 | error_ret: | |
745 | return ret; | |
746 | } | |
747 | ||
fc52692c | 748 | static int at91_adc_remove(struct platform_device *pdev) |
0e589d5f MR |
749 | { |
750 | struct iio_dev *idev = platform_get_drvdata(pdev); | |
0e589d5f MR |
751 | struct at91_adc_state *st = iio_priv(idev); |
752 | ||
753 | iio_device_unregister(idev); | |
754 | at91_adc_trigger_remove(idev); | |
755 | at91_adc_buffer_remove(idev); | |
756 | clk_disable_unprepare(st->adc_clk); | |
00062a9c | 757 | clk_disable_unprepare(st->clk); |
0e589d5f | 758 | free_irq(st->irq, idev); |
0e589d5f MR |
759 | iio_device_free(idev); |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
e364185f MR |
764 | static const struct of_device_id at91_adc_dt_ids[] = { |
765 | { .compatible = "atmel,at91sam9260-adc" }, | |
766 | {}, | |
767 | }; | |
768 | MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); | |
769 | ||
0e589d5f MR |
770 | static struct platform_driver at91_adc_driver = { |
771 | .probe = at91_adc_probe, | |
fc52692c | 772 | .remove = at91_adc_remove, |
0e589d5f MR |
773 | .driver = { |
774 | .name = "at91_adc", | |
e364185f | 775 | .of_match_table = of_match_ptr(at91_adc_dt_ids), |
0e589d5f MR |
776 | }, |
777 | }; | |
778 | ||
779 | module_platform_driver(at91_adc_driver); | |
780 | ||
781 | MODULE_LICENSE("GPL"); | |
782 | MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); | |
783 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |