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72aa29ce VB |
1 | /* |
2 | * Holt Integrated Circuits HI-8435 threshold detector driver | |
3 | * | |
4 | * Copyright (C) 2015 Zodiac Inflight Innovations | |
5 | * Copyright (C) 2015 Cogent Embedded, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/delay.h> | |
14 | #include <linux/iio/events.h> | |
15 | #include <linux/iio/iio.h> | |
16 | #include <linux/iio/sysfs.h> | |
17 | #include <linux/iio/trigger.h> | |
18 | #include <linux/iio/trigger_consumer.h> | |
19 | #include <linux/iio/triggered_event.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_gpio.h> | |
25 | #include <linux/spi/spi.h> | |
26 | #include <linux/gpio/consumer.h> | |
27 | ||
28 | #define DRV_NAME "hi8435" | |
29 | ||
30 | /* Register offsets for HI-8435 */ | |
31 | #define HI8435_CTRL_REG 0x02 | |
32 | #define HI8435_PSEN_REG 0x04 | |
33 | #define HI8435_TMDATA_REG 0x1E | |
34 | #define HI8435_GOCENHYS_REG 0x3A | |
35 | #define HI8435_SOCENHYS_REG 0x3C | |
36 | #define HI8435_SO7_0_REG 0x10 | |
37 | #define HI8435_SO15_8_REG 0x12 | |
38 | #define HI8435_SO23_16_REG 0x14 | |
39 | #define HI8435_SO31_24_REG 0x16 | |
40 | #define HI8435_SO31_0_REG 0x78 | |
41 | ||
42 | #define HI8435_WRITE_OPCODE 0x00 | |
43 | #define HI8435_READ_OPCODE 0x80 | |
44 | ||
45 | /* CTRL register bits */ | |
46 | #define HI8435_CTRL_TEST 0x01 | |
47 | #define HI8435_CTRL_SRST 0x02 | |
48 | ||
49 | struct hi8435_priv { | |
50 | struct spi_device *spi; | |
51 | struct mutex lock; | |
52 | ||
53 | unsigned long event_scan_mask; /* soft mask/unmask channels events */ | |
54 | unsigned int event_prev_val; | |
55 | ||
56 | unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */ | |
57 | unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */ | |
58 | u8 reg_buffer[3] ____cacheline_aligned; | |
59 | }; | |
60 | ||
61 | static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) | |
62 | { | |
63 | reg |= HI8435_READ_OPCODE; | |
64 | return spi_write_then_read(priv->spi, ®, 1, val, 1); | |
65 | } | |
66 | ||
67 | static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val) | |
68 | { | |
69 | int ret; | |
70 | __be16 be_val; | |
71 | ||
72 | reg |= HI8435_READ_OPCODE; | |
73 | ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 2); | |
74 | *val = be16_to_cpu(be_val); | |
75 | ||
76 | return ret; | |
77 | } | |
78 | ||
79 | static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val) | |
80 | { | |
81 | int ret; | |
82 | __be32 be_val; | |
83 | ||
84 | reg |= HI8435_READ_OPCODE; | |
85 | ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 4); | |
86 | *val = be32_to_cpu(be_val); | |
87 | ||
88 | return ret; | |
89 | } | |
90 | ||
91 | static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val) | |
92 | { | |
93 | priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; | |
94 | priv->reg_buffer[1] = val; | |
95 | ||
96 | return spi_write(priv->spi, priv->reg_buffer, 2); | |
97 | } | |
98 | ||
99 | static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val) | |
100 | { | |
101 | priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; | |
102 | priv->reg_buffer[1] = (val >> 8) & 0xff; | |
103 | priv->reg_buffer[2] = val & 0xff; | |
104 | ||
105 | return spi_write(priv->spi, priv->reg_buffer, 3); | |
106 | } | |
107 | ||
108 | static int hi8435_read_event_config(struct iio_dev *idev, | |
109 | const struct iio_chan_spec *chan, | |
110 | enum iio_event_type type, | |
111 | enum iio_event_direction dir) | |
112 | { | |
113 | struct hi8435_priv *priv = iio_priv(idev); | |
114 | ||
115 | return !!(priv->event_scan_mask & BIT(chan->channel)); | |
116 | } | |
117 | ||
118 | static int hi8435_write_event_config(struct iio_dev *idev, | |
119 | const struct iio_chan_spec *chan, | |
120 | enum iio_event_type type, | |
121 | enum iio_event_direction dir, int state) | |
122 | { | |
123 | struct hi8435_priv *priv = iio_priv(idev); | |
124 | ||
125 | priv->event_scan_mask &= ~BIT(chan->channel); | |
126 | if (state) | |
127 | priv->event_scan_mask |= BIT(chan->channel); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
132 | static int hi8435_read_event_value(struct iio_dev *idev, | |
133 | const struct iio_chan_spec *chan, | |
134 | enum iio_event_type type, | |
135 | enum iio_event_direction dir, | |
136 | enum iio_event_info info, | |
137 | int *val, int *val2) | |
138 | { | |
139 | struct hi8435_priv *priv = iio_priv(idev); | |
140 | int ret; | |
141 | u8 mode, psen; | |
142 | u16 reg; | |
143 | ||
144 | ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen); | |
145 | if (ret < 0) | |
146 | return ret; | |
147 | ||
148 | /* Supply-Open or GND-Open sensing mode */ | |
149 | mode = !!(psen & BIT(chan->channel / 8)); | |
150 | ||
151 | ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : | |
152 | HI8435_GOCENHYS_REG, ®); | |
153 | if (ret < 0) | |
154 | return ret; | |
155 | ||
156 | if (dir == IIO_EV_DIR_FALLING) | |
157 | *val = ((reg & 0xff) - (reg >> 8)) / 2; | |
158 | else if (dir == IIO_EV_DIR_RISING) | |
159 | *val = ((reg & 0xff) + (reg >> 8)) / 2; | |
160 | ||
161 | return IIO_VAL_INT; | |
162 | } | |
163 | ||
164 | static int hi8435_write_event_value(struct iio_dev *idev, | |
165 | const struct iio_chan_spec *chan, | |
166 | enum iio_event_type type, | |
167 | enum iio_event_direction dir, | |
168 | enum iio_event_info info, | |
169 | int val, int val2) | |
170 | { | |
171 | struct hi8435_priv *priv = iio_priv(idev); | |
172 | int ret; | |
173 | u8 mode, psen; | |
174 | u16 reg; | |
175 | ||
176 | ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen); | |
177 | if (ret < 0) | |
178 | return ret; | |
179 | ||
180 | /* Supply-Open or GND-Open sensing mode */ | |
181 | mode = !!(psen & BIT(chan->channel / 8)); | |
182 | ||
183 | ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : | |
184 | HI8435_GOCENHYS_REG, ®); | |
185 | if (ret < 0) | |
186 | return ret; | |
187 | ||
188 | if (dir == IIO_EV_DIR_FALLING) { | |
189 | /* falling threshold range 2..21V, hysteresis minimum 2V */ | |
190 | if (val < 2 || val > 21 || (val + 2) > priv->threshold_hi[mode]) | |
191 | return -EINVAL; | |
192 | ||
193 | if (val == priv->threshold_lo[mode]) | |
194 | return 0; | |
195 | ||
196 | priv->threshold_lo[mode] = val; | |
197 | ||
198 | /* hysteresis must not be odd */ | |
199 | if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2) | |
200 | priv->threshold_hi[mode]--; | |
201 | } else if (dir == IIO_EV_DIR_RISING) { | |
202 | /* rising threshold range 3..22V, hysteresis minimum 2V */ | |
203 | if (val < 3 || val > 22 || val < (priv->threshold_lo[mode] + 2)) | |
204 | return -EINVAL; | |
205 | ||
206 | if (val == priv->threshold_hi[mode]) | |
207 | return 0; | |
208 | ||
209 | priv->threshold_hi[mode] = val; | |
210 | ||
211 | /* hysteresis must not be odd */ | |
212 | if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2) | |
213 | priv->threshold_lo[mode]++; | |
214 | } | |
215 | ||
216 | /* program thresholds */ | |
217 | mutex_lock(&priv->lock); | |
218 | ||
219 | ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : | |
220 | HI8435_GOCENHYS_REG, ®); | |
221 | if (ret < 0) { | |
222 | mutex_unlock(&priv->lock); | |
223 | return ret; | |
224 | } | |
225 | ||
226 | /* hysteresis */ | |
227 | reg = priv->threshold_hi[mode] - priv->threshold_lo[mode]; | |
228 | reg <<= 8; | |
229 | /* threshold center */ | |
230 | reg |= (priv->threshold_hi[mode] + priv->threshold_lo[mode]); | |
231 | ||
232 | ret = hi8435_writew(priv, mode ? HI8435_SOCENHYS_REG : | |
233 | HI8435_GOCENHYS_REG, reg); | |
234 | ||
235 | mutex_unlock(&priv->lock); | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
240 | static int hi8435_debugfs_reg_access(struct iio_dev *idev, | |
241 | unsigned reg, unsigned writeval, | |
242 | unsigned *readval) | |
243 | { | |
244 | struct hi8435_priv *priv = iio_priv(idev); | |
245 | int ret; | |
246 | u8 val; | |
247 | ||
248 | if (readval != NULL) { | |
249 | ret = hi8435_readb(priv, reg, &val); | |
250 | *readval = val; | |
251 | } else { | |
252 | val = (u8)writeval; | |
253 | ret = hi8435_writeb(priv, reg, val); | |
254 | } | |
255 | ||
256 | return ret; | |
257 | } | |
258 | ||
259 | static const struct iio_event_spec hi8435_events[] = { | |
260 | { | |
261 | .type = IIO_EV_TYPE_THRESH, | |
262 | .dir = IIO_EV_DIR_RISING, | |
263 | .mask_separate = BIT(IIO_EV_INFO_VALUE), | |
264 | }, { | |
265 | .type = IIO_EV_TYPE_THRESH, | |
266 | .dir = IIO_EV_DIR_FALLING, | |
267 | .mask_separate = BIT(IIO_EV_INFO_VALUE), | |
268 | }, { | |
269 | .type = IIO_EV_TYPE_THRESH, | |
270 | .dir = IIO_EV_DIR_EITHER, | |
271 | .mask_separate = BIT(IIO_EV_INFO_ENABLE), | |
272 | }, | |
273 | }; | |
274 | ||
275 | static int hi8435_get_sensing_mode(struct iio_dev *idev, | |
276 | const struct iio_chan_spec *chan) | |
277 | { | |
278 | struct hi8435_priv *priv = iio_priv(idev); | |
279 | int ret; | |
280 | u8 reg; | |
281 | ||
282 | ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); | |
283 | if (ret < 0) | |
284 | return ret; | |
285 | ||
286 | return !!(reg & BIT(chan->channel / 8)); | |
287 | } | |
288 | ||
289 | static int hi8435_set_sensing_mode(struct iio_dev *idev, | |
290 | const struct iio_chan_spec *chan, | |
291 | unsigned int mode) | |
292 | { | |
293 | struct hi8435_priv *priv = iio_priv(idev); | |
294 | int ret; | |
295 | u8 reg; | |
296 | ||
297 | mutex_lock(&priv->lock); | |
298 | ||
299 | ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); | |
300 | if (ret < 0) { | |
301 | mutex_unlock(&priv->lock); | |
302 | return ret; | |
303 | } | |
304 | ||
305 | reg &= ~BIT(chan->channel / 8); | |
306 | if (mode) | |
307 | reg |= BIT(chan->channel / 8); | |
308 | ||
309 | ret = hi8435_writeb(priv, HI8435_PSEN_REG, reg); | |
310 | ||
311 | mutex_unlock(&priv->lock); | |
312 | ||
313 | return ret; | |
314 | } | |
315 | ||
316 | static const char * const hi8435_sensing_modes[] = { "GND-Open", | |
317 | "Supply-Open" }; | |
318 | ||
319 | static const struct iio_enum hi8435_sensing_mode = { | |
320 | .items = hi8435_sensing_modes, | |
321 | .num_items = ARRAY_SIZE(hi8435_sensing_modes), | |
322 | .get = hi8435_get_sensing_mode, | |
323 | .set = hi8435_set_sensing_mode, | |
324 | }; | |
325 | ||
326 | static const struct iio_chan_spec_ext_info hi8435_ext_info[] = { | |
327 | IIO_ENUM("sensing_mode", IIO_SEPARATE, &hi8435_sensing_mode), | |
328 | {}, | |
329 | }; | |
330 | ||
331 | #define HI8435_VOLTAGE_CHANNEL(num) \ | |
332 | { \ | |
333 | .type = IIO_VOLTAGE, \ | |
334 | .indexed = 1, \ | |
335 | .channel = num, \ | |
336 | .event_spec = hi8435_events, \ | |
337 | .num_event_specs = ARRAY_SIZE(hi8435_events), \ | |
338 | .ext_info = hi8435_ext_info, \ | |
339 | } | |
340 | ||
341 | static const struct iio_chan_spec hi8435_channels[] = { | |
342 | HI8435_VOLTAGE_CHANNEL(0), | |
343 | HI8435_VOLTAGE_CHANNEL(1), | |
344 | HI8435_VOLTAGE_CHANNEL(2), | |
345 | HI8435_VOLTAGE_CHANNEL(3), | |
346 | HI8435_VOLTAGE_CHANNEL(4), | |
347 | HI8435_VOLTAGE_CHANNEL(5), | |
348 | HI8435_VOLTAGE_CHANNEL(6), | |
349 | HI8435_VOLTAGE_CHANNEL(7), | |
350 | HI8435_VOLTAGE_CHANNEL(8), | |
351 | HI8435_VOLTAGE_CHANNEL(9), | |
352 | HI8435_VOLTAGE_CHANNEL(10), | |
353 | HI8435_VOLTAGE_CHANNEL(11), | |
354 | HI8435_VOLTAGE_CHANNEL(12), | |
355 | HI8435_VOLTAGE_CHANNEL(13), | |
356 | HI8435_VOLTAGE_CHANNEL(14), | |
357 | HI8435_VOLTAGE_CHANNEL(15), | |
358 | HI8435_VOLTAGE_CHANNEL(16), | |
359 | HI8435_VOLTAGE_CHANNEL(17), | |
360 | HI8435_VOLTAGE_CHANNEL(18), | |
361 | HI8435_VOLTAGE_CHANNEL(19), | |
362 | HI8435_VOLTAGE_CHANNEL(20), | |
363 | HI8435_VOLTAGE_CHANNEL(21), | |
364 | HI8435_VOLTAGE_CHANNEL(22), | |
365 | HI8435_VOLTAGE_CHANNEL(23), | |
366 | HI8435_VOLTAGE_CHANNEL(24), | |
367 | HI8435_VOLTAGE_CHANNEL(25), | |
368 | HI8435_VOLTAGE_CHANNEL(26), | |
369 | HI8435_VOLTAGE_CHANNEL(27), | |
370 | HI8435_VOLTAGE_CHANNEL(28), | |
371 | HI8435_VOLTAGE_CHANNEL(29), | |
372 | HI8435_VOLTAGE_CHANNEL(30), | |
373 | HI8435_VOLTAGE_CHANNEL(31), | |
374 | IIO_CHAN_SOFT_TIMESTAMP(32), | |
375 | }; | |
376 | ||
377 | static const struct iio_info hi8435_info = { | |
378 | .driver_module = THIS_MODULE, | |
379 | .read_event_config = &hi8435_read_event_config, | |
380 | .write_event_config = hi8435_write_event_config, | |
381 | .read_event_value = &hi8435_read_event_value, | |
382 | .write_event_value = &hi8435_write_event_value, | |
383 | .debugfs_reg_access = &hi8435_debugfs_reg_access, | |
384 | }; | |
385 | ||
386 | static void hi8435_iio_push_event(struct iio_dev *idev, unsigned int val) | |
387 | { | |
388 | struct hi8435_priv *priv = iio_priv(idev); | |
389 | enum iio_event_direction dir; | |
390 | unsigned int i; | |
391 | unsigned int status = priv->event_prev_val ^ val; | |
392 | ||
393 | if (!status) | |
394 | return; | |
395 | ||
396 | for_each_set_bit(i, &priv->event_scan_mask, 32) { | |
397 | if (status & BIT(i)) { | |
398 | dir = val & BIT(i) ? IIO_EV_DIR_RISING : | |
399 | IIO_EV_DIR_FALLING; | |
400 | iio_push_event(idev, | |
401 | IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i, | |
402 | IIO_EV_TYPE_THRESH, dir), | |
bc2b7dab | 403 | iio_get_time_ns(idev)); |
72aa29ce VB |
404 | } |
405 | } | |
406 | ||
407 | priv->event_prev_val = val; | |
408 | } | |
409 | ||
410 | static irqreturn_t hi8435_trigger_handler(int irq, void *private) | |
411 | { | |
412 | struct iio_poll_func *pf = private; | |
413 | struct iio_dev *idev = pf->indio_dev; | |
414 | struct hi8435_priv *priv = iio_priv(idev); | |
415 | u32 val; | |
416 | int ret; | |
417 | ||
418 | ret = hi8435_readl(priv, HI8435_SO31_0_REG, &val); | |
419 | if (ret < 0) | |
420 | goto err_read; | |
421 | ||
422 | hi8435_iio_push_event(idev, val); | |
423 | ||
424 | err_read: | |
425 | iio_trigger_notify_done(idev->trig); | |
426 | ||
427 | return IRQ_HANDLED; | |
428 | } | |
429 | ||
430 | static int hi8435_probe(struct spi_device *spi) | |
431 | { | |
432 | struct iio_dev *idev; | |
433 | struct hi8435_priv *priv; | |
434 | struct gpio_desc *reset_gpio; | |
435 | int ret; | |
436 | ||
437 | idev = devm_iio_device_alloc(&spi->dev, sizeof(*priv)); | |
438 | if (!idev) | |
439 | return -ENOMEM; | |
440 | ||
441 | priv = iio_priv(idev); | |
442 | priv->spi = spi; | |
443 | ||
444 | reset_gpio = devm_gpiod_get(&spi->dev, NULL, GPIOD_OUT_LOW); | |
445 | if (IS_ERR(reset_gpio)) { | |
446 | /* chip s/w reset if h/w reset failed */ | |
447 | hi8435_writeb(priv, HI8435_CTRL_REG, HI8435_CTRL_SRST); | |
448 | hi8435_writeb(priv, HI8435_CTRL_REG, 0); | |
449 | } else { | |
450 | udelay(5); | |
451 | gpiod_set_value(reset_gpio, 1); | |
452 | } | |
453 | ||
454 | spi_set_drvdata(spi, idev); | |
455 | mutex_init(&priv->lock); | |
456 | ||
457 | idev->dev.parent = &spi->dev; | |
b541eaff | 458 | idev->dev.of_node = spi->dev.of_node; |
72aa29ce VB |
459 | idev->name = spi_get_device_id(spi)->name; |
460 | idev->modes = INDIO_DIRECT_MODE; | |
461 | idev->info = &hi8435_info; | |
462 | idev->channels = hi8435_channels; | |
463 | idev->num_channels = ARRAY_SIZE(hi8435_channels); | |
464 | ||
465 | /* unmask all events */ | |
466 | priv->event_scan_mask = ~(0); | |
467 | /* | |
468 | * There is a restriction in the chip - the hysteresis can not be odd. | |
469 | * If the hysteresis is set to odd value then chip gets into lock state | |
470 | * and not functional anymore. | |
471 | * After chip reset the thresholds are in undefined state, so we need to | |
472 | * initialize thresholds to some initial values and then prevent | |
473 | * userspace setting odd hysteresis. | |
474 | * | |
475 | * Set threshold low voltage to 2V, threshold high voltage to 4V | |
476 | * for both GND-Open and Supply-Open sensing modes. | |
477 | */ | |
478 | priv->threshold_lo[0] = priv->threshold_lo[1] = 2; | |
479 | priv->threshold_hi[0] = priv->threshold_hi[1] = 4; | |
480 | hi8435_writew(priv, HI8435_GOCENHYS_REG, 0x206); | |
481 | hi8435_writew(priv, HI8435_SOCENHYS_REG, 0x206); | |
482 | ||
483 | ret = iio_triggered_event_setup(idev, NULL, hi8435_trigger_handler); | |
484 | if (ret) | |
485 | return ret; | |
486 | ||
487 | ret = iio_device_register(idev); | |
488 | if (ret < 0) { | |
489 | dev_err(&spi->dev, "unable to register device\n"); | |
490 | goto unregister_triggered_event; | |
491 | } | |
492 | ||
493 | return 0; | |
494 | ||
495 | unregister_triggered_event: | |
496 | iio_triggered_event_cleanup(idev); | |
497 | return ret; | |
498 | } | |
499 | ||
500 | static int hi8435_remove(struct spi_device *spi) | |
501 | { | |
502 | struct iio_dev *idev = spi_get_drvdata(spi); | |
503 | ||
504 | iio_device_unregister(idev); | |
505 | iio_triggered_event_cleanup(idev); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static const struct of_device_id hi8435_dt_ids[] = { | |
511 | { .compatible = "holt,hi8435" }, | |
512 | {}, | |
513 | }; | |
514 | MODULE_DEVICE_TABLE(of, hi8435_dt_ids); | |
515 | ||
516 | static const struct spi_device_id hi8435_id[] = { | |
517 | { "hi8435", 0}, | |
518 | { } | |
519 | }; | |
520 | MODULE_DEVICE_TABLE(spi, hi8435_id); | |
521 | ||
522 | static struct spi_driver hi8435_driver = { | |
523 | .driver = { | |
524 | .name = DRV_NAME, | |
525 | .of_match_table = of_match_ptr(hi8435_dt_ids), | |
526 | }, | |
527 | .probe = hi8435_probe, | |
528 | .remove = hi8435_remove, | |
529 | .id_table = hi8435_id, | |
530 | }; | |
531 | module_spi_driver(hi8435_driver); | |
532 | ||
533 | MODULE_LICENSE("GPL"); | |
534 | MODULE_AUTHOR("Vladimir Barinov"); | |
535 | MODULE_DESCRIPTION("HI-8435 threshold detector"); |