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d1325cf4 1 /*
82020b0e
JC		 2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
82b7afbc
VD		 11 * Driver for max1363 and similar chips.
12 *
82020b0e
JC		 13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
82020b0e 16 */
d1325cf4
JC		 17
18#include <linux/interrupt.h>
d1325cf4
JC		 19#include <linux/device.h>
20#include <linux/kernel.h>
21#include <linux/sysfs.h>
22#include <linux/list.h>
23#include <linux/i2c.h>
d1325cf4 24#include <linux/regulator/consumer.h>
5a0e3ad6 25#include <linux/slab.h>
c40ab874 26#include <linux/err.h>
99c97852 27#include <linux/module.h>
152c9aa0
FV		 28#include <linux/of.h>
29#include <linux/of_device.h>
d1325cf4 30
06458e27
JC		 31#include <linux/iio/iio.h>
32#include <linux/iio/sysfs.h>
33#include <linux/iio/events.h>
34#include <linux/iio/buffer.h>
35#include <linux/iio/driver.h>
b3bcbfcf
JC		 36#include <linux/iio/kfifo_buf.h>
37#include <linux/iio/trigger_consumer.h>
4389fbec 38#include <linux/iio/triggered_buffer.h>
b3bcbfcf
JC		 39
40#define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
41
42/* There is a fair bit more defined here than currently
43 * used, but the intention is to support everything these
44 * chips do in the long run */
45
46/* see data sheets */
47/* max1363 and max1236, max1237, max1238, max1239 */
48#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
49#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
50#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
51#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
52#define MAX1363_SETUP_POWER_UP_INT_REF 0x10
53#define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
54
71d2c120 55/* think about including max11600 etc - more settings */
b3bcbfcf
JC		 56#define MAX1363_SETUP_EXT_CLOCK 0x08
57#define MAX1363_SETUP_INT_CLOCK 0x00
58#define MAX1363_SETUP_UNIPOLAR 0x00
59#define MAX1363_SETUP_BIPOLAR 0x04
60#define MAX1363_SETUP_RESET 0x00
61#define MAX1363_SETUP_NORESET 0x02
62/* max1363 only - though don't care on others.
63 * For now monitor modes are not implemented as the relevant
64 * line is not connected on my test board.
65 * The definitions are here as I intend to add this soon.
66 */
67#define MAX1363_SETUP_MONITOR_SETUP 0x01
68
69/* Specific to the max1363 */
70#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
71#define MAX1363_MON_INT_ENABLE 0x01
72
73/* defined for readability reasons */
74/* All chips */
75#define MAX1363_CONFIG_BYTE(a) ((a))
76
77#define MAX1363_CONFIG_SE 0x01
78#define MAX1363_CONFIG_DE 0x00
79#define MAX1363_CONFIG_SCAN_TO_CS 0x00
80#define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
81#define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
82#define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
83/* max123{6-9} only */
84#define MAX1236_SCAN_MID_TO_CHANNEL 0x40
85
71d2c120 86/* max1363 only - merely part of channel selects or don't care for others */
b3bcbfcf
JC		 87#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
88
89#define MAX1363_CHANNEL_SEL(a) ((a) << 1)
90
91/* max1363 strictly 0x06 - but doesn't matter */
92#define MAX1363_CHANNEL_SEL_MASK 0x1E
93#define MAX1363_SCAN_MASK 0x60
94#define MAX1363_SE_DE_MASK 0x01
95
96#define MAX1363_MAX_CHANNELS 25
97/**
98 * struct max1363_mode - scan mode information
99 * @conf: The corresponding value of the configuration register
100 * @modemask: Bit mask corresponding to channels enabled in this mode
101 */
102struct max1363_mode {
103 int8_t conf;
104 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
105};
cdf38709 106
b3bcbfcf
JC		 107/* This must be maintained along side the max1363_mode_table in max1363_core */
108enum max1363_modes {
109 /* Single read of a single channel */
110 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
111 /* Differential single read */
112 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
113 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
114 /* Scan to channel and mid to channel where overlapping */
115 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
116 s6to7, s0to7, s6to8, s0to8, s6to9,
117 s0to9, s6to10, s0to10, s6to11, s0to11,
118 /* Differential scan to channel and mid to channel where overlapping */
119 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
120 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
121 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
122 d7m6to11m10, d1m0to11m10,
123};
124
125/**
126 * struct max1363_chip_info - chip specifc information
b3bcbfcf 127 * @info: iio core function callbacks structure
2593b13a
JC		 128 * @channels: channel specification
129 * @num_channels: number of channels
b3bcbfcf 130 * @mode_list: array of available scan modes
b3bcbfcf 131 * @default_mode: the scan mode in which the chip starts up
2593b13a 132 * @int_vref_mv: the internal reference voltage
71d2c120 133 * @num_modes: number of modes
2593b13a 134 * @bits: accuracy of the adc in bits
b3bcbfcf
JC		 135 */
136struct max1363_chip_info {
137 const struct iio_info *info;
2593b13a
JC		 138 const struct iio_chan_spec *channels;
139 int num_channels;
b3bcbfcf
JC		 140 const enum max1363_modes *mode_list;
141 enum max1363_modes default_mode;
142 u16 int_vref_mv;
143 u8 num_modes;
144 u8 bits;
145};
146
147/**
148 * struct max1363_state - driver instance specific data
149 * @client: i2c_client
150 * @setupbyte: cache of current device setup byte
151 * @configbyte: cache of current device config byte
71d2c120 152 * @chip_info: chip model specific constants, available modes, etc.
b3bcbfcf
JC		 153 * @current_mode: the scan mode of this chip
154 * @requestedmask: a valid requested set of channels
155 * @reg: supply regulator
156 * @monitor_on: whether monitor mode is enabled
157 * @monitor_speed: parameter corresponding to device monitor speed setting
158 * @mask_high: bitmask for enabled high thresholds
159 * @mask_low: bitmask for enabled low thresholds
160 * @thresh_high: high threshold values
161 * @thresh_low: low threshold values
a405b00e
GR		 162 * @vref: Reference voltage regulator
163 * @vref_uv: Actual (external or internal) reference voltage
61bdda69
VD		 164 * @send: function used to send data to the chip
165 * @recv: function used to receive data from the chip
b3bcbfcf
JC		 166 */
167struct max1363_state {
168 struct i2c_client *client;
169 u8 setupbyte;
170 u8 configbyte;
171 const struct max1363_chip_info *chip_info;
172 const struct max1363_mode *current_mode;
173 u32 requestedmask;
174 struct regulator *reg;
175
176 /* Using monitor modes and buffer at the same time is
177 currently not supported */
178 bool monitor_on;
179 unsigned int monitor_speed:3;
180 u8 mask_high;
181 u8 mask_low;
182 /* 4x unipolar first then the fours bipolar ones */
183 s16 thresh_high[8];
184 s16 thresh_low[8];
a405b00e
GR		 185 struct regulator *vref;
186 u32 vref_uv;
61bdda69
VD		 187 int (*send)(const struct i2c_client *client,
188 const char *buf, int count);
189 int (*recv)(const struct i2c_client *client,
190 char *buf, int count);
b3bcbfcf 191};
d1325cf4 192
58f0a255
JC		 193#define MAX1363_MODE_SINGLE(_num, _mask) { \
194 .conf = MAX1363_CHANNEL_SEL(_num) \
195 | MAX1363_CONFIG_SCAN_SINGLE_1 \
196 | MAX1363_CONFIG_SE, \
32b5eeca 197 .modemask[0] = _mask, \
58f0a255
JC		 198 }
199
200#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
201 .conf = MAX1363_CHANNEL_SEL(_num) \
202 | MAX1363_CONFIG_SCAN_TO_CS \
203 | MAX1363_CONFIG_SE, \
32b5eeca 204 .modemask[0] = _mask, \
58f0a255
JC		 205 }
206
207/* note not available for max1363 hence naming */
208#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
209 .conf = MAX1363_CHANNEL_SEL(_num) \
210 | MAX1236_SCAN_MID_TO_CHANNEL \
211 | MAX1363_CONFIG_SE, \
32b5eeca 212 .modemask[0] = _mask \
58f0a255
JC		 213}
214
215#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
216 .conf = MAX1363_CHANNEL_SEL(_nump) \
217 | MAX1363_CONFIG_SCAN_SINGLE_1 \
218 | MAX1363_CONFIG_DE, \
32b5eeca 219 .modemask[0] = _mask \
58f0a255
JC		 220 }
221
222/* Can't think how to automate naming so specify for now */
223#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
224 .conf = MAX1363_CHANNEL_SEL(_num) \
225 | MAX1363_CONFIG_SCAN_TO_CS \
226 | MAX1363_CONFIG_DE, \
32b5eeca 227 .modemask[0] = _mask \
58f0a255
JC		 228 }
229
230/* note only available for max1363 hence naming */
231#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
232 .conf = MAX1363_CHANNEL_SEL(_num) \
233 | MAX1236_SCAN_MID_TO_CHANNEL \
234 | MAX1363_CONFIG_SE, \
32b5eeca 235 .modemask[0] = _mask \
58f0a255 236}
82020b0e 237
82020b0e
JC		 238static const struct max1363_mode max1363_mode_table[] = {
239 /* All of the single channel options first */
240 MAX1363_MODE_SINGLE(0, 1 << 0),
241 MAX1363_MODE_SINGLE(1, 1 << 1),
242 MAX1363_MODE_SINGLE(2, 1 << 2),
243 MAX1363_MODE_SINGLE(3, 1 << 3),
244 MAX1363_MODE_SINGLE(4, 1 << 4),
245 MAX1363_MODE_SINGLE(5, 1 << 5),
246 MAX1363_MODE_SINGLE(6, 1 << 6),
247 MAX1363_MODE_SINGLE(7, 1 << 7),
248 MAX1363_MODE_SINGLE(8, 1 << 8),
249 MAX1363_MODE_SINGLE(9, 1 << 9),
250 MAX1363_MODE_SINGLE(10, 1 << 10),
251 MAX1363_MODE_SINGLE(11, 1 << 11),
252
253 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
254 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
255 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
256 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
257 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
258 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
259 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
260 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
261 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
262 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
263 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
264 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
265
266 /* The multichannel scans next */
267 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
268 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
269 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
270 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
271 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
272 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
273 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
279 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
281 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
282 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
283 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
284
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
286 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
290 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
293 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
297 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
298 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
d1325cf4
JC		 299};
300
b3bcbfcf 301static const struct max1363_mode
c52cfb63 302*max1363_match_mode(const unsigned long *mask,
71d2c120 303 const struct max1363_chip_info *ci)
1b183e4b 304{
82020b0e
JC		 305 int i;
306 if (mask)
307 for (i = 0; i < ci->num_modes; i++)
32b5eeca
JC		 308 if (bitmap_subset(mask,
309 max1363_mode_table[ci->mode_list[i]].
310 modemask,
311 MAX1363_MAX_CHANNELS))
1b183e4b
GKH		 312 return &max1363_mode_table[ci->mode_list[i]];
313 return NULL;
c608cb01 314}
82020b0e 315
61bdda69
VD		 316static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
317 int count)
82020b0e 318{
61bdda69 319 int i, err;
82020b0e 320
61bdda69
VD		 321 for (i = err = 0; err == 0 && i < count; ++i)
322 err = i2c_smbus_write_byte(client, buf[i]);
323
324 return err ? err : count;
325}
326
327static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
328 int count)
329{
330 int i, ret;
331
332 for (i = 0; i < count; ++i) {
333 ret = i2c_smbus_read_byte(client);
334 if (ret < 0)
335 return ret;
336 buf[i] = ret;
337 }
338
339 return count;
340}
341
342static int max1363_write_basic_config(struct max1363_state *st)
343{
344 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
345
346 return st->send(st->client, tx_buf, 2);
82020b0e
JC		 347}
348
b3bcbfcf 349static int max1363_set_scan_mode(struct max1363_state *st)
82020b0e
JC		 350{
351 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
352 | MAX1363_SCAN_MASK
353 | MAX1363_SE_DE_MASK);
354 st->configbyte |= st->current_mode->conf;
355
61bdda69 356 return max1363_write_basic_config(st);
82020b0e
JC		 357}
358
298cd976
JC		 359static int max1363_read_single_chan(struct iio_dev *indio_dev,
360 struct iio_chan_spec const *chan,
361 int *val,
362 long m)
82020b0e 363{
298cd976
JC		 364 int ret = 0;
365 s32 data;
482bb4e6 366 u8 rxbuf[2];
298cd976
JC		 367 struct max1363_state *st = iio_priv(indio_dev);
368 struct i2c_client *client = st->client;
82020b0e 369
b6b7068c 370 mutex_lock(&indio_dev->mlock);
440a5200
JC		 371 /*
372 * If monitor mode is enabled, the method for reading a single
373 * channel will have to be rather different and has not yet
374 * been implemented.
3ca34cc4
JC		 375 *
376 * Also, cannot read directly if buffered capture enabled.
440a5200 377 */
3ca34cc4 378 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
440a5200
JC		 379 ret = -EBUSY;
380 goto error_ret;
381 }
382
3ca34cc4
JC		 383 /* Check to see if current scan mode is correct */
384 if (st->current_mode != &max1363_mode_table[chan->address]) {
385 /* Update scan mode if needed */
386 st->current_mode = &max1363_mode_table[chan->address];
387 ret = max1363_set_scan_mode(st);
388 if (ret < 0)
389 goto error_ret;
390 }
391 if (st->chip_info->bits != 8) {
392 /* Get reading */
61bdda69 393 data = st->recv(client, rxbuf, 2);
82020b0e
JC		 394 if (data < 0) {
395 ret = data;
396 goto error_ret;
397 }
482bb4e6
GR		 398 data = (rxbuf[1] | rxbuf[0] << 8) &
399 ((1 << st->chip_info->bits) - 1);
82020b0e 400 } else {
3ca34cc4 401 /* Get reading */
61bdda69 402 data = st->recv(client, rxbuf, 1);
3ca34cc4
JC		 403 if (data < 0) {
404 ret = data;
405 goto error_ret;
82020b0e 406 }
3ca34cc4 407 data = rxbuf[0];
82020b0e 408 }
298cd976 409 *val = data;
82020b0e 410error_ret:
b6b7068c 411 mutex_unlock(&indio_dev->mlock);
298cd976
JC		 412 return ret;
413
82020b0e
JC		 414}
415
298cd976
JC		 416static int max1363_read_raw(struct iio_dev *indio_dev,
417 struct iio_chan_spec const *chan,
418 int *val,
419 int *val2,
420 long m)
82020b0e 421{
298cd976
JC		 422 struct max1363_state *st = iio_priv(indio_dev);
423 int ret;
a405b00e 424
298cd976 425 switch (m) {
b11f98ff 426 case IIO_CHAN_INFO_RAW:
298cd976 427 ret = max1363_read_single_chan(indio_dev, chan, val, m);
cd038019 428 if (ret < 0)
298cd976
JC		 429 return ret;
430 return IIO_VAL_INT;
c8a9f805 431 case IIO_CHAN_INFO_SCALE:
b2171677
LPC		 432 *val = st->vref_uv / 1000;
433 *val2 = st->chip_info->bits;
434 return IIO_VAL_FRACTIONAL_LOG2;
298cd976
JC		 435 default:
436 return -EINVAL;
437 }
438 return 0;
82020b0e
JC		 439}
440
d1325cf4
JC		 441/* Applies to max1363 */
442static const enum max1363_modes max1363_mode_list[] = {
443 _s0, _s1, _s2, _s3,
d1325cf4
JC		 444 s0to1, s0to2, s0to3,
445 d0m1, d2m3, d1m0, d3m2,
d1325cf4
JC		 446 d0m1to2m3, d1m0to3m2,
447};
448
e4ec84f8
LPC		 449static const struct iio_event_spec max1363_events[] = {
450 {
451 .type = IIO_EV_TYPE_THRESH,
452 .dir = IIO_EV_DIR_RISING,
453 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
454 BIT(IIO_EV_INFO_ENABLE),
455 }, {
456 .type = IIO_EV_TYPE_THRESH,
457 .dir = IIO_EV_DIR_FALLING,
458 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
459 BIT(IIO_EV_INFO_ENABLE),
460 },
461};
f6e52e59 462
e4ec84f8 463#define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
ade7ef7b
JC		 464 { \
465 .type = IIO_VOLTAGE, \
466 .indexed = 1, \
467 .channel = num, \
468 .address = addr, \
f6e52e59
JC		 469 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
470 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
bc234e72 471 .datasheet_name = "AIN"#num, \
18cffbed
JC		 472 .scan_type = { \
473 .sign = 'u', \
474 .realbits = bits, \
475 .storagebits = (bits > 8) ? 16 : 8, \
476 .endianness = IIO_BE, \
477 }, \
ade7ef7b 478 .scan_index = si, \
e4ec84f8
LPC		 479 .event_spec = ev_spec, \
480 .num_event_specs = num_ev_spec, \
ade7ef7b 481 }
298cd976 482
298cd976 483/* bipolar channel */
e4ec84f8 484#define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
ade7ef7b
JC		 485 { \
486 .type = IIO_VOLTAGE, \
487 .differential = 1, \
488 .indexed = 1, \
489 .channel = num, \
490 .channel2 = num2, \
491 .address = addr, \
f6e52e59
JC		 492 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
493 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
bc234e72 494 .datasheet_name = "AIN"#num"-AIN"#num2, \
18cffbed
JC		 495 .scan_type = { \
496 .sign = 's', \
497 .realbits = bits, \
498 .storagebits = (bits > 8) ? 16 : 8, \
499 .endianness = IIO_BE, \
500 }, \
ade7ef7b 501 .scan_index = si, \
e4ec84f8
LPC		 502 .event_spec = ev_spec, \
503 .num_event_specs = num_ev_spec, \
298cd976
JC		 504 }
505
e4ec84f8
LPC		 506#define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
507 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
511 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
512 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
513 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
514 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
515 IIO_CHAN_SOFT_TIMESTAMP(8) \
ade7ef7b
JC		 516 }
517
e4ec84f8
LPC		 518static const struct iio_chan_spec max1036_channels[] =
519 MAX1363_4X_CHANS(8, NULL, 0);
520static const struct iio_chan_spec max1136_channels[] =
521 MAX1363_4X_CHANS(10, NULL, 0);
522static const struct iio_chan_spec max1236_channels[] =
523 MAX1363_4X_CHANS(12, NULL, 0);
f4e4b955 524static const struct iio_chan_spec max1361_channels[] =
e4ec84f8 525 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
f4e4b955 526static const struct iio_chan_spec max1363_channels[] =
e4ec84f8 527 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
298cd976 528
4abf6f8b 529/* Applies to max1236, max1237 */
d1325cf4
JC		 530static const enum max1363_modes max1236_mode_list[] = {
531 _s0, _s1, _s2, _s3,
d1325cf4
JC		 532 s0to1, s0to2, s0to3,
533 d0m1, d2m3, d1m0, d3m2,
d1325cf4
JC		 534 d0m1to2m3, d1m0to3m2,
535 s2to3,
536};
537
538/* Applies to max1238, max1239 */
539static const enum max1363_modes max1238_mode_list[] = {
540 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
d1325cf4
JC		 541 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
542 s0to7, s0to8, s0to9, s0to10, s0to11,
543 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
544 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
d1325cf4
JC		 545 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
546 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
547 s6to7, s6to8, s6to9, s6to10, s6to11,
82020b0e 548 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
d1325cf4
JC		 549};
550
e4ec84f8
LPC		 551#define MAX1363_12X_CHANS(bits) { \
552 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
553 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
554 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
555 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
556 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
557 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
558 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
559 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
560 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
561 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
562 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
563 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
564 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
565 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
566 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
567 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
568 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
569 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
570 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
571 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
572 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
573 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
574 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
575 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
576 IIO_CHAN_SOFT_TIMESTAMP(24) \
298cd976 577 }
f4e4b955
LPC		 578static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
579static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
580static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
d1325cf4 581
c3fa0fdd
JC		 582static const enum max1363_modes max11607_mode_list[] = {
583 _s0, _s1, _s2, _s3,
584 s0to1, s0to2, s0to3,
585 s2to3,
586 d0m1, d2m3, d1m0, d3m2,
587 d0m1to2m3, d1m0to3m2,
588};
589
590static const enum max1363_modes max11608_mode_list[] = {
591 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
592 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
593 s6to7,
594 d0m1, d2m3, d4m5, d6m7,
595 d1m0, d3m2, d5m4, d7m6,
596 d0m1to2m3, d0m1to4m5, d0m1to6m7,
597 d1m0to3m2, d1m0to5m4, d1m0to7m6,
598};
599
ade7ef7b 600#define MAX1363_8X_CHANS(bits) { \
e4ec84f8
LPC		 601 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
602 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
603 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
604 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
605 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
606 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
607 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
608 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
609 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
610 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
611 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
612 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
613 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
614 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
615 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
616 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
ade7ef7b
JC		 617 IIO_CHAN_SOFT_TIMESTAMP(16) \
618}
f4e4b955
LPC		 619static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
620static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
621static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
c3fa0fdd 622
586d1525
JC		 623static const enum max1363_modes max11644_mode_list[] = {
624 _s0, _s1, s0to1, d0m1, d1m0,
625};
626
627#define MAX1363_2X_CHANS(bits) { \
e4ec84f8
LPC		 628 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
629 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
630 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
631 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
586d1525
JC		 632 IIO_CHAN_SOFT_TIMESTAMP(4) \
633 }
634
f4e4b955
LPC		 635static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
636static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
586d1525 637
d1325cf4
JC		 638enum { max1361,
639 max1362,
640 max1363,
641 max1364,
3bf877c1
JC		 642 max1036,
643 max1037,
644 max1038,
645 max1039,
d1325cf4
JC		 646 max1136,
647 max1137,
648 max1138,
649 max1139,
650 max1236,
651 max1237,
652 max1238,
653 max1239,
3bf877c1
JC		 654 max11600,
655 max11601,
656 max11602,
657 max11603,
658 max11604,
659 max11605,
c3fa0fdd
JC		 660 max11606,
661 max11607,
662 max11608,
663 max11609,
664 max11610,
665 max11611,
666 max11612,
667 max11613,
668 max11614,
669 max11615,
670 max11616,
671 max11617,
586d1525
JC		 672 max11644,
673 max11645,
674 max11646,
675 max11647
d1325cf4
JC		 676};
677
440a5200
JC		 678static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
679 8300, 4200, 2000, 1000 };
680
681static ssize_t max1363_monitor_show_freq(struct device *dev,
682 struct device_attribute *attr,
683 char *buf)
684{
62c51839 685 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
440a5200
JC		 686 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
687}
688
689static ssize_t max1363_monitor_store_freq(struct device *dev,
690 struct device_attribute *attr,
691 const char *buf,
692 size_t len)
693{
62c51839 694 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
3dba81ba 695 struct max1363_state *st = iio_priv(indio_dev);
440a5200
JC		 696 int i, ret;
697 unsigned long val;
698 bool found = false;
699
ddeb64f3 700 ret = kstrtoul(buf, 10, &val);
440a5200
JC		 701 if (ret)
702 return -EINVAL;
703 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
704 if (val == max1363_monitor_speeds[i]) {
705 found = true;
706 break;
707 }
708 if (!found)
709 return -EINVAL;
710
b6b7068c 711 mutex_lock(&indio_dev->mlock);
440a5200 712 st->monitor_speed = i;
b6b7068c 713 mutex_unlock(&indio_dev->mlock);
440a5200
JC		 714
715 return 0;
716}
717
718static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
719 max1363_monitor_show_freq,
720 max1363_monitor_store_freq);
721
722static IIO_CONST_ATTR(sampling_frequency_available,
723 "133000 665000 33300 16600 8300 4200 2000 1000");
724
298cd976 725static int max1363_read_thresh(struct iio_dev *indio_dev,
e4ec84f8
LPC		 726 const struct iio_chan_spec *chan, enum iio_event_type type,
727 enum iio_event_direction dir, enum iio_event_info info, int *val,
728 int *val2)
440a5200 729{
3dba81ba 730 struct max1363_state *st = iio_priv(indio_dev);
e4ec84f8
LPC		 731 if (dir == IIO_EV_DIR_FALLING)
732 *val = st->thresh_low[chan->channel];
440a5200 733 else
e4ec84f8
LPC		 734 *val = st->thresh_high[chan->channel];
735 return IIO_VAL_INT;
440a5200
JC		 736}
737
298cd976 738static int max1363_write_thresh(struct iio_dev *indio_dev,
e4ec84f8
LPC		 739 const struct iio_chan_spec *chan, enum iio_event_type type,
740 enum iio_event_direction dir, enum iio_event_info info, int val,
741 int val2)
440a5200 742{
298cd976
JC		 743 struct max1363_state *st = iio_priv(indio_dev);
744 /* make it handle signed correctly as well */
440a5200
JC		 745 switch (st->chip_info->bits) {
746 case 10:
747 if (val > 0x3FF)
748 return -EINVAL;
749 break;
750 case 12:
751 if (val > 0xFFF)
752 return -EINVAL;
753 break;
754 }
755
e4ec84f8 756 switch (dir) {
298cd976 757 case IIO_EV_DIR_FALLING:
e4ec84f8 758 st->thresh_low[chan->channel] = val;
440a5200 759 break;
298cd976 760 case IIO_EV_DIR_RISING:
e4ec84f8 761 st->thresh_high[chan->channel] = val;
440a5200 762 break;
e4ec84f8
LPC		 763 default:
764 return -EINVAL;
440a5200
JC		 765 }
766
440a5200
JC		 767 return 0;
768}
769
330c6c57 770static const u64 max1363_event_codes[] = {
6835cb6b
JC		 771 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
772 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
773 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
774 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
783 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
784 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
785 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
786 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
58f0a255
JC		 787};
788
aaf370db 789static irqreturn_t max1363_event_handler(int irq, void *private)
440a5200 790{
aaf370db
JC		 791 struct iio_dev *indio_dev = private;
792 struct max1363_state *st = iio_priv(indio_dev);
bc2b7dab 793 s64 timestamp = iio_get_time_ns(indio_dev);
58f0a255 794 unsigned long mask, loc;
440a5200
JC		 795 u8 rx;
796 u8 tx[2] = { st->setupbyte,
797 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
798
61bdda69 799 st->recv(st->client, &rx, 1);
58f0a255
JC		 800 mask = rx;
801 for_each_set_bit(loc, &mask, 8)
5aa96188 802 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
61bdda69 803 st->send(st->client, tx, 2);
aaf370db
JC		 804
805 return IRQ_HANDLED;
440a5200
JC		 806}
807
298cd976 808static int max1363_read_event_config(struct iio_dev *indio_dev,
e4ec84f8
LPC		 809 const struct iio_chan_spec *chan, enum iio_event_type type,
810 enum iio_event_direction dir)
440a5200 811{
3dba81ba 812 struct max1363_state *st = iio_priv(indio_dev);
298cd976 813 int val;
e4ec84f8 814 int number = chan->channel;
0d9fa2ce 815
b6b7068c 816 mutex_lock(&indio_dev->mlock);
e4ec84f8 817 if (dir == IIO_EV_DIR_FALLING)
298cd976 818 val = (1 << number) & st->mask_low;
440a5200 819 else
298cd976 820 val = (1 << number) & st->mask_high;
b6b7068c 821 mutex_unlock(&indio_dev->mlock);
440a5200 822
298cd976 823 return val;
440a5200
JC		 824}
825
826static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
827{
828 u8 *tx_buf;
829 int ret, i = 3, j;
830 unsigned long numelements;
831 int len;
32b5eeca 832 const long *modemask;
440a5200
JC		 833
834 if (!enabled) {
ec443728 835 /* transition to buffered capture is not currently supported */
440a5200
JC		 836 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
837 st->configbyte &= ~MAX1363_SCAN_MASK;
838 st->monitor_on = false;
61bdda69 839 return max1363_write_basic_config(st);
440a5200
JC		 840 }
841
842 /* Ensure we are in the relevant mode */
843 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
844 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
845 | MAX1363_SCAN_MASK
846 | MAX1363_SE_DE_MASK);
847 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
848 if ((st->mask_low | st->mask_high) & 0x0F) {
849 st->configbyte |= max1363_mode_table[s0to3].conf;
850 modemask = max1363_mode_table[s0to3].modemask;
851 } else if ((st->mask_low | st->mask_high) & 0x30) {
852 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
853 modemask = max1363_mode_table[d0m1to2m3].modemask;
854 } else {
855 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
856 modemask = max1363_mode_table[d1m0to3m2].modemask;
857 }
32b5eeca 858 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
440a5200
JC		 859 len = 3 * numelements + 3;
860 tx_buf = kmalloc(len, GFP_KERNEL);
861 if (!tx_buf) {
862 ret = -ENOMEM;
863 goto error_ret;
864 }
865 tx_buf[0] = st->configbyte;
866 tx_buf[1] = st->setupbyte;
867 tx_buf[2] = (st->monitor_speed << 1);
868
869 /*
870 * So we need to do yet another bit of nefarious scan mode
871 * setup to match what we need.
872 */
873 for (j = 0; j < 8; j++)
32b5eeca 874 if (test_bit(j, modemask)) {
440a5200
JC		 875 /* Establish the mode is in the scan */
876 if (st->mask_low & (1 << j)) {
877 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
878 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
879 } else if (j < 4) {
880 tx_buf[i] = 0;
881 tx_buf[i + 1] = 0;
882 } else {
883 tx_buf[i] = 0x80;
884 tx_buf[i + 1] = 0;
885 }
886 if (st->mask_high & (1 << j)) {
887 tx_buf[i + 1] |=
888 (st->thresh_high[j] >> 8) & 0x0F;
889 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
890 } else if (j < 4) {
891 tx_buf[i + 1] |= 0x0F;
892 tx_buf[i + 2] = 0xFF;
893 } else {
894 tx_buf[i + 1] |= 0x07;
895 tx_buf[i + 2] = 0xFF;
896 }
897 i += 3;
898 }
899
900
61bdda69 901 ret = st->send(st->client, tx_buf, len);
440a5200
JC		 902 if (ret < 0)
903 goto error_ret;
904 if (ret != len) {
905 ret = -EIO;
906 goto error_ret;
907 }
908
909 /*
910 * Now that we hopefully have sensible thresholds in place it is
911 * time to turn the interrupts on.
912 * It is unclear from the data sheet if this should be necessary
913 * (i.e. whether monitor mode setup is atomic) but it appears to
914 * be in practice.
915 */
916 tx_buf[0] = st->setupbyte;
917 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
61bdda69 918 ret = st->send(st->client, tx_buf, 2);
440a5200
JC		 919 if (ret < 0)
920 goto error_ret;
921 if (ret != 2) {
922 ret = -EIO;
923 goto error_ret;
924 }
925 ret = 0;
926 st->monitor_on = true;
927error_ret:
928
929 kfree(tx_buf);
930
931 return ret;
932}
933
934/*
25985edc 935 * To keep this manageable we always use one of 3 scan modes.
440a5200
JC		 936 * Scan 0...3, 0-1,2-3 and 1-0,3-2
937 */
298cd976 938
440a5200
JC		 939static inline int __max1363_check_event_mask(int thismask, int checkmask)
940{
941 int ret = 0;
942 /* Is it unipolar */
943 if (thismask < 4) {
944 if (checkmask & ~0x0F) {
945 ret = -EBUSY;
946 goto error_ret;
947 }
948 } else if (thismask < 6) {
949 if (checkmask & ~0x30) {
950 ret = -EBUSY;
951 goto error_ret;
952 }
953 } else if (checkmask & ~0xC0)
954 ret = -EBUSY;
955error_ret:
956 return ret;
957}
958
298cd976 959static int max1363_write_event_config(struct iio_dev *indio_dev,
e4ec84f8
LPC		 960 const struct iio_chan_spec *chan, enum iio_event_type type,
961 enum iio_event_direction dir, int state)
440a5200 962{
298cd976 963 int ret = 0;
3dba81ba 964 struct max1363_state *st = iio_priv(indio_dev);
440a5200 965 u16 unifiedmask;
e4ec84f8 966 int number = chan->channel;
298cd976 967
3dba81ba 968 mutex_lock(&indio_dev->mlock);
440a5200 969 unifiedmask = st->mask_low | st->mask_high;
e4ec84f8 970 if (dir == IIO_EV_DIR_FALLING) {
298cd976
JC		 971
972 if (state == 0)
973 st->mask_low &= ~(1 << number);
440a5200 974 else {
298cd976
JC		 975 ret = __max1363_check_event_mask((1 << number),
976 unifiedmask);
440a5200
JC		 977 if (ret)
978 goto error_ret;
298cd976 979 st->mask_low |= (1 << number);
440a5200
JC		 980 }
981 } else {
298cd976
JC		 982 if (state == 0)
983 st->mask_high &= ~(1 << number);
440a5200 984 else {
298cd976
JC		 985 ret = __max1363_check_event_mask((1 << number),
986 unifiedmask);
440a5200
JC		 987 if (ret)
988 goto error_ret;
298cd976 989 st->mask_high |= (1 << number);
440a5200
JC		 990 }
991 }
440a5200
JC		 992
993 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
994error_ret:
3dba81ba 995 mutex_unlock(&indio_dev->mlock);
440a5200 996
298cd976 997 return ret;
440a5200
JC		 998}
999
440a5200
JC		 1000/*
1001 * As with scan_elements, only certain sets of these can
1002 * be combined.
1003 */
1004static struct attribute *max1363_event_attributes[] = {
440a5200
JC		 1005 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1006 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
440a5200
JC		 1007 NULL,
1008};
1009
c94645b1 1010static const struct attribute_group max1363_event_attribute_group = {
6fe8135f
JC		 1011 .attrs = max1363_event_attributes,
1012};
1013
b3bcbfcf
JC		 1014static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1015 const unsigned long *scan_mask)
1016{
1017 struct max1363_state *st = iio_priv(indio_dev);
1018
1019 /*
1020 * Need to figure out the current mode based upon the requested
1021 * scan mask in iio_dev
1022 */
1023 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1024 if (!st->current_mode)
1025 return -EINVAL;
1026 max1363_set_scan_mode(st);
1027 return 0;
1028}
6fe8135f
JC		 1029
1030static const struct iio_info max1238_info = {
1031 .read_raw = &max1363_read_raw,
1032 .driver_module = THIS_MODULE,
a9ea1b17 1033 .update_scan_mode = &max1363_update_scan_mode,
6fe8135f
JC		 1034};
1035
1036static const struct iio_info max1363_info = {
cb955852
LPC		 1037 .read_event_value = &max1363_read_thresh,
1038 .write_event_value = &max1363_write_thresh,
1039 .read_event_config = &max1363_read_event_config,
1040 .write_event_config = &max1363_write_event_config,
6fe8135f 1041 .read_raw = &max1363_read_raw,
c52cfb63 1042 .update_scan_mode = &max1363_update_scan_mode,
6fe8135f 1043 .driver_module = THIS_MODULE,
6fe8135f
JC		 1044 .event_attrs = &max1363_event_attribute_group,
1045};
1046
1047/* max1363 and max1368 tested - rest from data sheet */
1048static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1049 [max1361] = {
1050 .bits = 10,
1051 .int_vref_mv = 2048,
1052 .mode_list = max1363_mode_list,
1053 .num_modes = ARRAY_SIZE(max1363_mode_list),
1054 .default_mode = s0to3,
1055 .channels = max1361_channels,
1056 .num_channels = ARRAY_SIZE(max1361_channels),
1057 .info = &max1363_info,
1058 },
1059 [max1362] = {
1060 .bits = 10,
1061 .int_vref_mv = 4096,
1062 .mode_list = max1363_mode_list,
1063 .num_modes = ARRAY_SIZE(max1363_mode_list),
1064 .default_mode = s0to3,
1065 .channels = max1361_channels,
1066 .num_channels = ARRAY_SIZE(max1361_channels),
1067 .info = &max1363_info,
1068 },
1069 [max1363] = {
1070 .bits = 12,
1071 .int_vref_mv = 2048,
1072 .mode_list = max1363_mode_list,
1073 .num_modes = ARRAY_SIZE(max1363_mode_list),
1074 .default_mode = s0to3,
1075 .channels = max1363_channels,
1076 .num_channels = ARRAY_SIZE(max1363_channels),
1077 .info = &max1363_info,
1078 },
1079 [max1364] = {
1080 .bits = 12,
1081 .int_vref_mv = 4096,
1082 .mode_list = max1363_mode_list,
1083 .num_modes = ARRAY_SIZE(max1363_mode_list),
1084 .default_mode = s0to3,
1085 .channels = max1363_channels,
1086 .num_channels = ARRAY_SIZE(max1363_channels),
1087 .info = &max1363_info,
1088 },
1089 [max1036] = {
1090 .bits = 8,
1091 .int_vref_mv = 4096,
1092 .mode_list = max1236_mode_list,
1093 .num_modes = ARRAY_SIZE(max1236_mode_list),
1094 .default_mode = s0to3,
1095 .info = &max1238_info,
1096 .channels = max1036_channels,
1097 .num_channels = ARRAY_SIZE(max1036_channels),
1098 },
1099 [max1037] = {
1100 .bits = 8,
1101 .int_vref_mv = 2048,
1102 .mode_list = max1236_mode_list,
1103 .num_modes = ARRAY_SIZE(max1236_mode_list),
1104 .default_mode = s0to3,
1105 .info = &max1238_info,
1106 .channels = max1036_channels,
1107 .num_channels = ARRAY_SIZE(max1036_channels),
1108 },
1109 [max1038] = {
1110 .bits = 8,
1111 .int_vref_mv = 4096,
1112 .mode_list = max1238_mode_list,
1113 .num_modes = ARRAY_SIZE(max1238_mode_list),
1114 .default_mode = s0to11,
1115 .info = &max1238_info,
1116 .channels = max1038_channels,
1117 .num_channels = ARRAY_SIZE(max1038_channels),
1118 },
1119 [max1039] = {
1120 .bits = 8,
1121 .int_vref_mv = 2048,
1122 .mode_list = max1238_mode_list,
1123 .num_modes = ARRAY_SIZE(max1238_mode_list),
1124 .default_mode = s0to11,
1125 .info = &max1238_info,
1126 .channels = max1038_channels,
1127 .num_channels = ARRAY_SIZE(max1038_channels),
1128 },
1129 [max1136] = {
1130 .bits = 10,
1131 .int_vref_mv = 4096,
1132 .mode_list = max1236_mode_list,
1133 .num_modes = ARRAY_SIZE(max1236_mode_list),
1134 .default_mode = s0to3,
1135 .info = &max1238_info,
1136 .channels = max1136_channels,
1137 .num_channels = ARRAY_SIZE(max1136_channels),
1138 },
1139 [max1137] = {
1140 .bits = 10,
1141 .int_vref_mv = 2048,
1142 .mode_list = max1236_mode_list,
1143 .num_modes = ARRAY_SIZE(max1236_mode_list),
1144 .default_mode = s0to3,
1145 .info = &max1238_info,
1146 .channels = max1136_channels,
1147 .num_channels = ARRAY_SIZE(max1136_channels),
1148 },
1149 [max1138] = {
1150 .bits = 10,
1151 .int_vref_mv = 4096,
1152 .mode_list = max1238_mode_list,
1153 .num_modes = ARRAY_SIZE(max1238_mode_list),
1154 .default_mode = s0to11,
1155 .info = &max1238_info,
1156 .channels = max1138_channels,
1157 .num_channels = ARRAY_SIZE(max1138_channels),
1158 },
1159 [max1139] = {
1160 .bits = 10,
1161 .int_vref_mv = 2048,
1162 .mode_list = max1238_mode_list,
1163 .num_modes = ARRAY_SIZE(max1238_mode_list),
1164 .default_mode = s0to11,
1165 .info = &max1238_info,
1166 .channels = max1138_channels,
1167 .num_channels = ARRAY_SIZE(max1138_channels),
1168 },
1169 [max1236] = {
1170 .bits = 12,
1171 .int_vref_mv = 4096,
1172 .mode_list = max1236_mode_list,
1173 .num_modes = ARRAY_SIZE(max1236_mode_list),
1174 .default_mode = s0to3,
1175 .info = &max1238_info,
1176 .channels = max1236_channels,
1177 .num_channels = ARRAY_SIZE(max1236_channels),
1178 },
1179 [max1237] = {
1180 .bits = 12,
1181 .int_vref_mv = 2048,
1182 .mode_list = max1236_mode_list,
1183 .num_modes = ARRAY_SIZE(max1236_mode_list),
1184 .default_mode = s0to3,
1185 .info = &max1238_info,
1186 .channels = max1236_channels,
1187 .num_channels = ARRAY_SIZE(max1236_channels),
1188 },
1189 [max1238] = {
1190 .bits = 12,
1191 .int_vref_mv = 4096,
1192 .mode_list = max1238_mode_list,
1193 .num_modes = ARRAY_SIZE(max1238_mode_list),
1194 .default_mode = s0to11,
1195 .info = &max1238_info,
1196 .channels = max1238_channels,
1197 .num_channels = ARRAY_SIZE(max1238_channels),
1198 },
1199 [max1239] = {
1200 .bits = 12,
1201 .int_vref_mv = 2048,
1202 .mode_list = max1238_mode_list,
1203 .num_modes = ARRAY_SIZE(max1238_mode_list),
1204 .default_mode = s0to11,
1205 .info = &max1238_info,
1206 .channels = max1238_channels,
1207 .num_channels = ARRAY_SIZE(max1238_channels),
1208 },
1209 [max11600] = {
1210 .bits = 8,
1211 .int_vref_mv = 4096,
1212 .mode_list = max11607_mode_list,
1213 .num_modes = ARRAY_SIZE(max11607_mode_list),
1214 .default_mode = s0to3,
1215 .info = &max1238_info,
1216 .channels = max1036_channels,
1217 .num_channels = ARRAY_SIZE(max1036_channels),
1218 },
1219 [max11601] = {
1220 .bits = 8,
1221 .int_vref_mv = 2048,
1222 .mode_list = max11607_mode_list,
1223 .num_modes = ARRAY_SIZE(max11607_mode_list),
1224 .default_mode = s0to3,
1225 .info = &max1238_info,
1226 .channels = max1036_channels,
1227 .num_channels = ARRAY_SIZE(max1036_channels),
1228 },
1229 [max11602] = {
1230 .bits = 8,
1231 .int_vref_mv = 4096,
1232 .mode_list = max11608_mode_list,
1233 .num_modes = ARRAY_SIZE(max11608_mode_list),
1234 .default_mode = s0to7,
1235 .info = &max1238_info,
1236 .channels = max11602_channels,
1237 .num_channels = ARRAY_SIZE(max11602_channels),
1238 },
1239 [max11603] = {
1240 .bits = 8,
1241 .int_vref_mv = 2048,
1242 .mode_list = max11608_mode_list,
1243 .num_modes = ARRAY_SIZE(max11608_mode_list),
1244 .default_mode = s0to7,
1245 .info = &max1238_info,
1246 .channels = max11602_channels,
1247 .num_channels = ARRAY_SIZE(max11602_channels),
1248 },
1249 [max11604] = {
1250 .bits = 8,
b8a70aef 1251 .int_vref_mv = 4096,
6fe8135f
JC		 1252 .mode_list = max1238_mode_list,
1253 .num_modes = ARRAY_SIZE(max1238_mode_list),
1254 .default_mode = s0to11,
1255 .info = &max1238_info,
a91a73c8
JC		 1256 .channels = max1038_channels,
1257 .num_channels = ARRAY_SIZE(max1038_channels),
6fe8135f
JC		 1258 },
1259 [max11605] = {
1260 .bits = 8,
1261 .int_vref_mv = 2048,
1262 .mode_list = max1238_mode_list,
1263 .num_modes = ARRAY_SIZE(max1238_mode_list),
1264 .default_mode = s0to11,
1265 .info = &max1238_info,
a91a73c8
JC		 1266 .channels = max1038_channels,
1267 .num_channels = ARRAY_SIZE(max1038_channels),
6fe8135f
JC		 1268 },
1269 [max11606] = {
1270 .bits = 10,
1271 .int_vref_mv = 4096,
1272 .mode_list = max11607_mode_list,
1273 .num_modes = ARRAY_SIZE(max11607_mode_list),
1274 .default_mode = s0to3,
1275 .info = &max1238_info,
1276 .channels = max1136_channels,
1277 .num_channels = ARRAY_SIZE(max1136_channels),
1278 },
1279 [max11607] = {
1280 .bits = 10,
1281 .int_vref_mv = 2048,
1282 .mode_list = max11607_mode_list,
1283 .num_modes = ARRAY_SIZE(max11607_mode_list),
1284 .default_mode = s0to3,
1285 .info = &max1238_info,
1286 .channels = max1136_channels,
1287 .num_channels = ARRAY_SIZE(max1136_channels),
1288 },
1289 [max11608] = {
1290 .bits = 10,
1291 .int_vref_mv = 4096,
1292 .mode_list = max11608_mode_list,
1293 .num_modes = ARRAY_SIZE(max11608_mode_list),
1294 .default_mode = s0to7,
1295 .info = &max1238_info,
1296 .channels = max11608_channels,
1297 .num_channels = ARRAY_SIZE(max11608_channels),
1298 },
1299 [max11609] = {
1300 .bits = 10,
1301 .int_vref_mv = 2048,
1302 .mode_list = max11608_mode_list,
1303 .num_modes = ARRAY_SIZE(max11608_mode_list),
1304 .default_mode = s0to7,
1305 .info = &max1238_info,
1306 .channels = max11608_channels,
1307 .num_channels = ARRAY_SIZE(max11608_channels),
1308 },
1309 [max11610] = {
1310 .bits = 10,
b8a70aef 1311 .int_vref_mv = 4096,
6fe8135f
JC		 1312 .mode_list = max1238_mode_list,
1313 .num_modes = ARRAY_SIZE(max1238_mode_list),
1314 .default_mode = s0to11,
1315 .info = &max1238_info,
a91a73c8
JC		 1316 .channels = max1138_channels,
1317 .num_channels = ARRAY_SIZE(max1138_channels),
6fe8135f
JC		 1318 },
1319 [max11611] = {
1320 .bits = 10,
1321 .int_vref_mv = 2048,
1322 .mode_list = max1238_mode_list,
1323 .num_modes = ARRAY_SIZE(max1238_mode_list),
1324 .default_mode = s0to11,
1325 .info = &max1238_info,
a91a73c8
JC		 1326 .channels = max1138_channels,
1327 .num_channels = ARRAY_SIZE(max1138_channels),
6fe8135f
JC		 1328 },
1329 [max11612] = {
1330 .bits = 12,
1331 .int_vref_mv = 4096,
1332 .mode_list = max11607_mode_list,
1333 .num_modes = ARRAY_SIZE(max11607_mode_list),
1334 .default_mode = s0to3,
1335 .info = &max1238_info,
1336 .channels = max1363_channels,
1337 .num_channels = ARRAY_SIZE(max1363_channels),
1338 },
1339 [max11613] = {
1340 .bits = 12,
1341 .int_vref_mv = 2048,
1342 .mode_list = max11607_mode_list,
1343 .num_modes = ARRAY_SIZE(max11607_mode_list),
1344 .default_mode = s0to3,
1345 .info = &max1238_info,
1346 .channels = max1363_channels,
1347 .num_channels = ARRAY_SIZE(max1363_channels),
1348 },
1349 [max11614] = {
1350 .bits = 12,
1351 .int_vref_mv = 4096,
1352 .mode_list = max11608_mode_list,
1353 .num_modes = ARRAY_SIZE(max11608_mode_list),
1354 .default_mode = s0to7,
1355 .info = &max1238_info,
1356 .channels = max11614_channels,
1357 .num_channels = ARRAY_SIZE(max11614_channels),
1358 },
1359 [max11615] = {
1360 .bits = 12,
1361 .int_vref_mv = 2048,
1362 .mode_list = max11608_mode_list,
1363 .num_modes = ARRAY_SIZE(max11608_mode_list),
1364 .default_mode = s0to7,
1365 .info = &max1238_info,
1366 .channels = max11614_channels,
1367 .num_channels = ARRAY_SIZE(max11614_channels),
1368 },
1369 [max11616] = {
1370 .bits = 12,
b8a70aef 1371 .int_vref_mv = 4096,
6fe8135f
JC		 1372 .mode_list = max1238_mode_list,
1373 .num_modes = ARRAY_SIZE(max1238_mode_list),
1374 .default_mode = s0to11,
1375 .info = &max1238_info,
1376 .channels = max1238_channels,
1377 .num_channels = ARRAY_SIZE(max1238_channels),
1378 },
1379 [max11617] = {
1380 .bits = 12,
1381 .int_vref_mv = 2048,
1382 .mode_list = max1238_mode_list,
1383 .num_modes = ARRAY_SIZE(max1238_mode_list),
1384 .default_mode = s0to11,
1385 .info = &max1238_info,
1386 .channels = max1238_channels,
1387 .num_channels = ARRAY_SIZE(max1238_channels),
1388 },
1389 [max11644] = {
1390 .bits = 12,
5c913eb9 1391 .int_vref_mv = 4096,
6fe8135f
JC		 1392 .mode_list = max11644_mode_list,
1393 .num_modes = ARRAY_SIZE(max11644_mode_list),
1394 .default_mode = s0to1,
1395 .info = &max1238_info,
1396 .channels = max11644_channels,
1397 .num_channels = ARRAY_SIZE(max11644_channels),
1398 },
1399 [max11645] = {
1400 .bits = 12,
5c913eb9 1401 .int_vref_mv = 2048,
6fe8135f
JC		 1402 .mode_list = max11644_mode_list,
1403 .num_modes = ARRAY_SIZE(max11644_mode_list),
1404 .default_mode = s0to1,
1405 .info = &max1238_info,
1406 .channels = max11644_channels,
1407 .num_channels = ARRAY_SIZE(max11644_channels),
1408 },
1409 [max11646] = {
1410 .bits = 10,
5c913eb9 1411 .int_vref_mv = 4096,
6fe8135f
JC		 1412 .mode_list = max11644_mode_list,
1413 .num_modes = ARRAY_SIZE(max11644_mode_list),
1414 .default_mode = s0to1,
1415 .info = &max1238_info,
1416 .channels = max11646_channels,
1417 .num_channels = ARRAY_SIZE(max11646_channels),
1418 },
1419 [max11647] = {
1420 .bits = 10,
5c913eb9 1421 .int_vref_mv = 2048,
6fe8135f
JC		 1422 .mode_list = max11644_mode_list,
1423 .num_modes = ARRAY_SIZE(max11644_mode_list),
1424 .default_mode = s0to1,
1425 .info = &max1238_info,
1426 .channels = max11646_channels,
1427 .num_channels = ARRAY_SIZE(max11646_channels),
1428 },
1429};
1430
d1325cf4
JC		 1431static int max1363_initial_setup(struct max1363_state *st)
1432{
a405b00e 1433 st->setupbyte = MAX1363_SETUP_INT_CLOCK
d1325cf4
JC		 1434 | MAX1363_SETUP_UNIPOLAR
1435 | MAX1363_SETUP_NORESET;
1436
a405b00e
GR		 1437 if (st->vref)
1438 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1439 else
1440 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1441 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1442
71d2c120 1443 /* Set scan mode writes the config anyway so wait until then */
d1325cf4
JC		 1444 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1445 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1446 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1447
1448 return max1363_set_scan_mode(st);
1449}
1450
fc52692c 1451static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
cd4361c7
MH		 1452{
1453 struct max1363_state *st = iio_priv(indio_dev);
1454 unsigned long *masks;
1455 int i;
1456
7c3e8675
GR		 1457 masks = devm_kzalloc(&indio_dev->dev,
1458 BITS_TO_LONGS(MAX1363_MAX_CHANNELS) * sizeof(long) *
1459 (st->chip_info->num_modes + 1), GFP_KERNEL);
cd4361c7
MH		 1460 if (!masks)
1461 return -ENOMEM;
1462
1463 for (i = 0; i < st->chip_info->num_modes; i++)
1464 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1465 max1363_mode_table[st->chip_info->mode_list[i]]
1466 .modemask, MAX1363_MAX_CHANNELS);
1467
1468 indio_dev->available_scan_masks = masks;
1469
1470 return 0;
1471}
1472
b3bcbfcf
JC		 1473static irqreturn_t max1363_trigger_handler(int irq, void *p)
1474{
1475 struct iio_poll_func *pf = p;
1476 struct iio_dev *indio_dev = pf->indio_dev;
1477 struct max1363_state *st = iio_priv(indio_dev);
b3bcbfcf
JC		 1478 __u8 *rxbuf;
1479 int b_sent;
1480 size_t d_size;
1481 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1482 MAX1363_MAX_CHANNELS);
1483
1484 /* Ensure the timestamp is 8 byte aligned */
1485 if (st->chip_info->bits != 8)
1486 d_size = numvals*2;
1487 else
1488 d_size = numvals;
1489 if (indio_dev->scan_timestamp) {
1490 d_size += sizeof(s64);
1491 if (d_size % sizeof(s64))
1492 d_size += sizeof(s64) - (d_size % sizeof(s64));
1493 }
1494 /* Monitor mode prevents reading. Whilst not currently implemented
1495 * might as well have this test in here in the meantime as it does
1496 * no harm.
1497 */
1498 if (numvals == 0)
1499 goto done;
1500
1501 rxbuf = kmalloc(d_size, GFP_KERNEL);
1502 if (rxbuf == NULL)
1503 goto done;
1504 if (st->chip_info->bits != 8)
61bdda69 1505 b_sent = st->recv(st->client, rxbuf, numvals * 2);
b3bcbfcf 1506 else
61bdda69 1507 b_sent = st->recv(st->client, rxbuf, numvals);
b3bcbfcf
JC		 1508 if (b_sent < 0)
1509 goto done_free;
1510
bc2b7dab
GB		 1511 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1512 iio_get_time_ns(indio_dev));
b3bcbfcf
JC		 1513
1514done_free:
1515 kfree(rxbuf);
1516done:
1517 iio_trigger_notify_done(indio_dev->trig);
1518
1519 return IRQ_HANDLED;
1520}
1521
152c9aa0
FV		 1522#ifdef CONFIG_OF
1523
1524#define MAX1363_COMPATIBLE(of_compatible, cfg) { \
1525 .compatible = of_compatible, \
1526 .data = &max1363_chip_info_tbl[cfg], \
1527}
1528
1529static const struct of_device_id max1363_of_match[] = {
1530 MAX1363_COMPATIBLE("maxim,max1361", max1361),
1531 MAX1363_COMPATIBLE("maxim,max1362", max1362),
1532 MAX1363_COMPATIBLE("maxim,max1363", max1363),
1533 MAX1363_COMPATIBLE("maxim,max1364", max1364),
1534 MAX1363_COMPATIBLE("maxim,max1036", max1036),
1535 MAX1363_COMPATIBLE("maxim,max1037", max1037),
1536 MAX1363_COMPATIBLE("maxim,max1038", max1038),
1537 MAX1363_COMPATIBLE("maxim,max1039", max1039),
1538 MAX1363_COMPATIBLE("maxim,max1136", max1136),
1539 MAX1363_COMPATIBLE("maxim,max1137", max1137),
1540 MAX1363_COMPATIBLE("maxim,max1138", max1138),
1541 MAX1363_COMPATIBLE("maxim,max1139", max1139),
1542 MAX1363_COMPATIBLE("maxim,max1236", max1236),
1543 MAX1363_COMPATIBLE("maxim,max1237", max1237),
1544 MAX1363_COMPATIBLE("maxim,max1238", max1238),
1545 MAX1363_COMPATIBLE("maxim,max1239", max1239),
1546 MAX1363_COMPATIBLE("maxim,max11600", max11600),
1547 MAX1363_COMPATIBLE("maxim,max11601", max11601),
1548 MAX1363_COMPATIBLE("maxim,max11602", max11602),
1549 MAX1363_COMPATIBLE("maxim,max11603", max11603),
1550 MAX1363_COMPATIBLE("maxim,max11604", max11604),
1551 MAX1363_COMPATIBLE("maxim,max11605", max11605),
1552 MAX1363_COMPATIBLE("maxim,max11606", max11606),
1553 MAX1363_COMPATIBLE("maxim,max11607", max11607),
1554 MAX1363_COMPATIBLE("maxim,max11608", max11608),
1555 MAX1363_COMPATIBLE("maxim,max11609", max11609),
1556 MAX1363_COMPATIBLE("maxim,max11610", max11610),
1557 MAX1363_COMPATIBLE("maxim,max11611", max11611),
1558 MAX1363_COMPATIBLE("maxim,max11612", max11612),
1559 MAX1363_COMPATIBLE("maxim,max11613", max11613),
1560 MAX1363_COMPATIBLE("maxim,max11614", max11614),
1561 MAX1363_COMPATIBLE("maxim,max11615", max11615),
1562 MAX1363_COMPATIBLE("maxim,max11616", max11616),
1563 MAX1363_COMPATIBLE("maxim,max11617", max11617),
1564 MAX1363_COMPATIBLE("maxim,max11644", max11644),
1565 MAX1363_COMPATIBLE("maxim,max11645", max11645),
1566 MAX1363_COMPATIBLE("maxim,max11646", max11646),
1567 MAX1363_COMPATIBLE("maxim,max11647", max11647),
1568 { /* sentinel */ }
1569};
99be230d 1570MODULE_DEVICE_TABLE(of, max1363_of_match);
152c9aa0
FV		 1571#endif
1572
fc52692c
GKH		 1573static int max1363_probe(struct i2c_client *client,
1574 const struct i2c_device_id *id)
d1325cf4 1575{
cd4361c7 1576 int ret;
3dba81ba
JC		 1577 struct max1363_state *st;
1578 struct iio_dev *indio_dev;
a405b00e 1579 struct regulator *vref;
152c9aa0 1580 const struct of_device_id *match;
f88af7e7 1581
6917e1d9
SK		 1582 indio_dev = devm_iio_device_alloc(&client->dev,
1583 sizeof(struct max1363_state));
1584 if (!indio_dev)
1585 return -ENOMEM;
b77b8f8c 1586
315ce4b8 1587 indio_dev->dev.of_node = client->dev.of_node;
0b27d678
JC		 1588 ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1589 if (ret < 0)
6917e1d9 1590 return ret;
b77b8f8c 1591
3dba81ba 1592 st = iio_priv(indio_dev);
b77b8f8c 1593
7c3e8675 1594 st->reg = devm_regulator_get(&client->dev, "vcc");
b77b8f8c
JC		 1595 if (IS_ERR(st->reg)) {
1596 ret = PTR_ERR(st->reg);
1597 goto error_unregister_map;
1598 }
1599
1600 ret = regulator_enable(st->reg);
1601 if (ret)
7c3e8675 1602 goto error_unregister_map;
b77b8f8c 1603
3dba81ba
JC		 1604 /* this is only used for device removal purposes */
1605 i2c_set_clientdata(client, indio_dev);
1606
152c9aa0
FV		 1607 match = of_match_device(of_match_ptr(max1363_of_match),
1608 &client->dev);
1609 if (match)
1610 st->chip_info = of_device_get_match_data(&client->dev);
1611 else
1612 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
3dba81ba 1613 st->client = client;
d1325cf4 1614
a405b00e 1615 st->vref_uv = st->chip_info->int_vref_mv * 1000;
55b40d37 1616 vref = devm_regulator_get_optional(&client->dev, "vref");
a405b00e
GR		 1617 if (!IS_ERR(vref)) {
1618 int vref_uv;
1619
1620 ret = regulator_enable(vref);
1621 if (ret)
1622 goto error_disable_reg;
1623 st->vref = vref;
1624 vref_uv = regulator_get_voltage(vref);
1625 if (vref_uv <= 0) {
1626 ret = -EINVAL;
1627 goto error_disable_reg;
1628 }
1629 st->vref_uv = vref_uv;
1630 }
1631
61bdda69
VD		 1632 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1633 st->send = i2c_master_send;
1634 st->recv = i2c_master_recv;
1635 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1636 && st->chip_info->bits == 8) {
1637 st->send = max1363_smbus_send;
1638 st->recv = max1363_smbus_recv;
1639 } else {
1640 ret = -EOPNOTSUPP;
1641 goto error_disable_reg;
1642 }
1643
cd4361c7
MH		 1644 ret = max1363_alloc_scan_masks(indio_dev);
1645 if (ret)
b77b8f8c 1646 goto error_disable_reg;
82020b0e 1647
71d2c120 1648 /* Establish that the iio_dev is a child of the i2c device */
3dba81ba 1649 indio_dev->dev.parent = &client->dev;
b541eaff 1650 indio_dev->dev.of_node = client->dev.of_node;
845bd12a 1651 indio_dev->name = id->name;
8e7d9672
JC		 1652 indio_dev->channels = st->chip_info->channels;
1653 indio_dev->num_channels = st->chip_info->num_channels;
6fe8135f
JC		 1654 indio_dev->info = st->chip_info->info;
1655 indio_dev->modes = INDIO_DIRECT_MODE;
d1325cf4 1656 ret = max1363_initial_setup(st);
58f0a255 1657 if (ret < 0)
7c3e8675 1658 goto error_disable_reg;
d1325cf4 1659
4389fbec 1660 ret = iio_triggered_buffer_setup(indio_dev, NULL,
7a1aeba7 1661 &max1363_trigger_handler, NULL);
d1325cf4 1662 if (ret)
7c3e8675 1663 goto error_disable_reg;
d1325cf4 1664
6fe8135f 1665 if (client->irq) {
7c3e8675 1666 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
aaf370db
JC		 1667 NULL,
1668 &max1363_event_handler,
1669 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1670 "max1363_event",
1671 indio_dev);
298cd976 1672
440a5200 1673 if (ret)
ec443728 1674 goto error_uninit_buffer;
440a5200
JC		 1675 }
1676
26d25ae3
JC		 1677 ret = iio_device_register(indio_dev);
1678 if (ret < 0)
7c3e8675 1679 goto error_uninit_buffer;
f88af7e7 1680
26d25ae3 1681 return 0;
7c3e8675 1682
ec443728 1683error_uninit_buffer:
4389fbec 1684 iio_triggered_buffer_cleanup(indio_dev);
d1325cf4 1685error_disable_reg:
a405b00e
GR		 1686 if (st->vref)
1687 regulator_disable(st->vref);
b77b8f8c 1688 regulator_disable(st->reg);
678fb42e 1689error_unregister_map:
6cb2afd7 1690 iio_map_array_unregister(indio_dev);
d1325cf4
JC		 1691 return ret;
1692}
1693
fc52692c 1694static int max1363_remove(struct i2c_client *client)
d1325cf4 1695{
3dba81ba
JC		 1696 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1697 struct max1363_state *st = iio_priv(indio_dev);
440a5200 1698
d2fffd6c 1699 iio_device_unregister(indio_dev);
4389fbec 1700 iio_triggered_buffer_cleanup(indio_dev);
a405b00e
GR		 1701 if (st->vref)
1702 regulator_disable(st->vref);
678fb42e 1703 regulator_disable(st->reg);
6cb2afd7 1704 iio_map_array_unregister(indio_dev);
d1325cf4
JC		 1705
1706 return 0;
1707}
1708
1709static const struct i2c_device_id max1363_id[] = {
1710 { "max1361", max1361 },
1711 { "max1362", max1362 },
1712 { "max1363", max1363 },
1713 { "max1364", max1364 },
3bf877c1
JC		 1714 { "max1036", max1036 },
1715 { "max1037", max1037 },
1716 { "max1038", max1038 },
1717 { "max1039", max1039 },
d1325cf4
JC		 1718 { "max1136", max1136 },
1719 { "max1137", max1137 },
1720 { "max1138", max1138 },
1721 { "max1139", max1139 },
1722 { "max1236", max1236 },
1723 { "max1237", max1237 },
1724 { "max1238", max1238 },
1725 { "max1239", max1239 },
3bf877c1
JC		 1726 { "max11600", max11600 },
1727 { "max11601", max11601 },
1728 { "max11602", max11602 },
1729 { "max11603", max11603 },
1730 { "max11604", max11604 },
1731 { "max11605", max11605 },
c3fa0fdd
JC		 1732 { "max11606", max11606 },
1733 { "max11607", max11607 },
1734 { "max11608", max11608 },
1735 { "max11609", max11609 },
1736 { "max11610", max11610 },
1737 { "max11611", max11611 },
1738 { "max11612", max11612 },
1739 { "max11613", max11613 },
1740 { "max11614", max11614 },
1741 { "max11615", max11615 },
1742 { "max11616", max11616 },
1743 { "max11617", max11617 },
3fb77e29
SE		 1744 { "max11644", max11644 },
1745 { "max11645", max11645 },
1746 { "max11646", max11646 },
1747 { "max11647", max11647 },
d1325cf4
JC		 1748 {}
1749};
1750
1751MODULE_DEVICE_TABLE(i2c, max1363_id);
1752
1753static struct i2c_driver max1363_driver = {
1754 .driver = {
1755 .name = "max1363",
152c9aa0 1756 .of_match_table = of_match_ptr(max1363_of_match),
d1325cf4
JC		 1757 },
1758 .probe = max1363_probe,
fc52692c 1759 .remove = max1363_remove,
d1325cf4
JC		 1760 .id_table = max1363_id,
1761};
6e5af184 1762module_i2c_driver(max1363_driver);
d1325cf4 1763
0f8c9620 1764MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
d1325cf4
JC		 1765MODULE_DESCRIPTION("Maxim 1363 ADC");
1766MODULE_LICENSE("GPL v2");
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