[mirror_ubuntu-bionic-kernel.git] / drivers / iio / adc / nau7802.c

/*
 * Driver for the Nuvoton NAU7802 ADC
 *
 * Copyright 2013 Free Electrons
 *
 * Licensed under the GPLv2 or later.
 */

#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/wait.h>
#include <linux/log2.h>
#include <linux/of.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>

#define NAU7802_REG_PUCTRL	0x00
#define NAU7802_PUCTRL_RR(x)		(x << 0)
#define NAU7802_PUCTRL_RR_BIT		NAU7802_PUCTRL_RR(1)
#define NAU7802_PUCTRL_PUD(x)		(x << 1)
#define NAU7802_PUCTRL_PUD_BIT		NAU7802_PUCTRL_PUD(1)
#define NAU7802_PUCTRL_PUA(x)		(x << 2)
#define NAU7802_PUCTRL_PUA_BIT		NAU7802_PUCTRL_PUA(1)
#define NAU7802_PUCTRL_PUR(x)		(x << 3)
#define NAU7802_PUCTRL_PUR_BIT		NAU7802_PUCTRL_PUR(1)
#define NAU7802_PUCTRL_CS(x)		(x << 4)
#define NAU7802_PUCTRL_CS_BIT		NAU7802_PUCTRL_CS(1)
#define NAU7802_PUCTRL_CR(x)		(x << 5)
#define NAU7802_PUCTRL_CR_BIT		NAU7802_PUCTRL_CR(1)
#define NAU7802_PUCTRL_AVDDS(x)		(x << 7)
#define NAU7802_PUCTRL_AVDDS_BIT	NAU7802_PUCTRL_AVDDS(1)
#define NAU7802_REG_CTRL1	0x01
#define NAU7802_CTRL1_VLDO(x)		(x << 3)
#define NAU7802_CTRL1_GAINS(x)		(x)
#define NAU7802_CTRL1_GAINS_BITS	0x07
#define NAU7802_REG_CTRL2	0x02
#define NAU7802_CTRL2_CHS(x)		(x << 7)
#define NAU7802_CTRL2_CRS(x)		(x << 4)
#define NAU7802_SAMP_FREQ_320	0x07
#define NAU7802_CTRL2_CHS_BIT		NAU7802_CTRL2_CHS(1)
#define NAU7802_REG_ADC_B2	0x12
#define NAU7802_REG_ADC_B1	0x13
#define NAU7802_REG_ADC_B0	0x14
#define NAU7802_REG_ADC_CTRL	0x15

#define NAU7802_MIN_CONVERSIONS 6

struct nau7802_state {
	struct i2c_client	*client;
	s32			last_value;
	struct mutex		lock;
	struct mutex		data_lock;
	u32			vref_mv;
	u32			conversion_count;
	u32			min_conversions;
	u8			sample_rate;
	u32			scale_avail[8];
	struct completion	value_ok;
};

#define NAU7802_CHANNEL(chan) {					\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.channel = (chan),					\
	.scan_index = (chan),					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ)	\
}

static const struct iio_chan_spec nau7802_chan_array[] = {
	NAU7802_CHANNEL(0),
	NAU7802_CHANNEL(1),
};

static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80,
						10, 10, 10, 320};

static ssize_t nau7802_show_scales(struct device *dev,
				   struct device_attribute *attr, char *buf)
{
	struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev));
	int i, len = 0;

	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
		len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09d ",
				 st->scale_avail[i]);

	buf[len-1] = '\n';

	return len;
}

static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320");

static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, nau7802_show_scales,
		       NULL, 0);

static struct attribute *nau7802_attributes[] = {
	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
	&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
	NULL
};

static const struct attribute_group nau7802_attribute_group = {
	.attrs = nau7802_attributes,
};

static int nau7802_set_gain(struct nau7802_state *st, int gain)
{
	int ret;

	mutex_lock(&st->lock);
	st->conversion_count = 0;

	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
	if (ret < 0)
		goto nau7802_sysfs_set_gain_out;
	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
					(ret & (~NAU7802_CTRL1_GAINS_BITS)) |
					gain);

nau7802_sysfs_set_gain_out:
	mutex_unlock(&st->lock);

	return ret;
}

static int nau7802_read_conversion(struct nau7802_state *st)
{
	int data;

	mutex_lock(&st->data_lock);
	data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2);
	if (data < 0)
		goto nau7802_read_conversion_out;
	st->last_value = data << 16;

	data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1);
	if (data < 0)
		goto nau7802_read_conversion_out;
	st->last_value |= data << 8;

	data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0);
	if (data < 0)
		goto nau7802_read_conversion_out;
	st->last_value |= data;

	st->last_value = sign_extend32(st->last_value, 23);

nau7802_read_conversion_out:
	mutex_unlock(&st->data_lock);

	return data;
}

/*
 * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
 */
static int nau7802_sync(struct nau7802_state *st)
{
	int ret;

	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
	if (ret < 0)
		return ret;
	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
				ret | NAU7802_PUCTRL_CS_BIT);

	return ret;
}

static irqreturn_t nau7802_eoc_trigger(int irq, void *private)
{
	struct iio_dev *indio_dev = private;
	struct nau7802_state *st = iio_priv(indio_dev);
	int status;

	status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
	if (status < 0)
		return IRQ_HANDLED;

	if (!(status & NAU7802_PUCTRL_CR_BIT))
		return IRQ_NONE;

	if (nau7802_read_conversion(st) < 0)
		return IRQ_HANDLED;

	/*
	 * Because there is actually only one ADC for both channels, we have to
	 * wait for enough conversions to happen before getting a significant
	 * value when changing channels and the values are far apart.
	 */
	if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
		st->conversion_count++;
	if (st->conversion_count >= NAU7802_MIN_CONVERSIONS)
		complete(&st->value_ok);

	return IRQ_HANDLED;
}

static int nau7802_read_irq(struct iio_dev *indio_dev,
			struct iio_chan_spec const *chan,
			int *val)
{
	struct nau7802_state *st = iio_priv(indio_dev);
	int ret;

	reinit_completion(&st->value_ok);
	enable_irq(st->client->irq);

	nau7802_sync(st);

	/* read registers to ensure we flush everything */
	ret = nau7802_read_conversion(st);
	if (ret < 0)
		goto read_chan_info_failure;

	/* Wait for a conversion to finish */
	ret = wait_for_completion_interruptible_timeout(&st->value_ok,
			msecs_to_jiffies(1000));
	if (ret == 0)
		ret = -ETIMEDOUT;

	if (ret < 0)
		goto read_chan_info_failure;

	disable_irq(st->client->irq);

	*val = st->last_value;

	return IIO_VAL_INT;

read_chan_info_failure:
	disable_irq(st->client->irq);

	return ret;
}

static int nau7802_read_poll(struct iio_dev *indio_dev,
			struct iio_chan_spec const *chan,
			int *val)
{
	struct nau7802_state *st = iio_priv(indio_dev);
	int ret;

	nau7802_sync(st);

	/* read registers to ensure we flush everything */
	ret = nau7802_read_conversion(st);
	if (ret < 0)
		return ret;

	/*
	 * Because there is actually only one ADC for both channels, we have to
	 * wait for enough conversions to happen before getting a significant
	 * value when changing channels and the values are far appart.
	 */
	do {
		ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
		if (ret < 0)
			return ret;

		while (!(ret & NAU7802_PUCTRL_CR_BIT)) {
			if (st->sample_rate != NAU7802_SAMP_FREQ_320)
				msleep(20);
			else
				mdelay(4);
			ret = i2c_smbus_read_byte_data(st->client,
							NAU7802_REG_PUCTRL);
			if (ret < 0)
				return ret;
		}

		ret = nau7802_read_conversion(st);
		if (ret < 0)
			return ret;
		if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
			st->conversion_count++;
	} while (st->conversion_count < NAU7802_MIN_CONVERSIONS);

	*val = st->last_value;

	return IIO_VAL_INT;
}

static int nau7802_read_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan,
			    int *val, int *val2, long mask)
{
	struct nau7802_state *st = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		mutex_lock(&st->lock);
		/*
		 * Select the channel to use
		 *   - Channel 1 is value 0 in the CHS register
		 *   - Channel 2 is value 1 in the CHS register
		 */
		ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2);
		if (ret < 0) {
			mutex_unlock(&st->lock);
			return ret;
		}

		if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) ||
				(!(ret & NAU7802_CTRL2_CHS_BIT) &&
				 chan->channel)) {
			st->conversion_count = 0;
			ret = i2c_smbus_write_byte_data(st->client,
					NAU7802_REG_CTRL2,
					NAU7802_CTRL2_CHS(chan->channel) |
					NAU7802_CTRL2_CRS(st->sample_rate));

			if (ret < 0) {
				mutex_unlock(&st->lock);
				return ret;
			}
		}

		if (st->client->irq)
			ret = nau7802_read_irq(indio_dev, chan, val);
		else
			ret = nau7802_read_poll(indio_dev, chan, val);

		mutex_unlock(&st->lock);
		return ret;

	case IIO_CHAN_INFO_SCALE:
		ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
		if (ret < 0)
			return ret;

		/*
		 * We have 24 bits of signed data, that means 23 bits of data
		 * plus the sign bit
		 */
		*val = st->vref_mv;
		*val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS);

		return IIO_VAL_FRACTIONAL_LOG2;

	case IIO_CHAN_INFO_SAMP_FREQ:
		*val =  nau7802_sample_freq_avail[st->sample_rate];
		*val2 = 0;
		return IIO_VAL_INT;

	default:
		break;
	}

	return -EINVAL;
}

static int nau7802_write_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan,
			     int val, int val2, long mask)
{
	struct nau7802_state *st = iio_priv(indio_dev);
	int i, ret;

	switch (mask) {
	case IIO_CHAN_INFO_SCALE:
		for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
			if (val2 == st->scale_avail[i])
				return nau7802_set_gain(st, i);

		break;

	case IIO_CHAN_INFO_SAMP_FREQ:
		for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++)
			if (val == nau7802_sample_freq_avail[i]) {
				mutex_lock(&st->lock);
				st->sample_rate = i;
				st->conversion_count = 0;
				ret = i2c_smbus_write_byte_data(st->client,
					NAU7802_REG_CTRL2,
					NAU7802_CTRL2_CRS(st->sample_rate));
				mutex_unlock(&st->lock);
				return ret;
			}

		break;

	default:
		break;
	}

	return -EINVAL;
}

static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
				     struct iio_chan_spec const *chan,
				     long mask)
{
	return IIO_VAL_INT_PLUS_NANO;
}

static const struct iio_info nau7802_info = {
	.driver_module = THIS_MODULE,
	.read_raw = &nau7802_read_raw,
	.write_raw = &nau7802_write_raw,
	.write_raw_get_fmt = nau7802_write_raw_get_fmt,
	.attrs = &nau7802_attribute_group,
};

static int nau7802_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	struct iio_dev *indio_dev;
	struct nau7802_state *st;
	struct device_node *np = client->dev.of_node;
	int i, ret;
	u8 data;
	u32 tmp = 0;

	if (!client->dev.of_node) {
		dev_err(&client->dev, "No device tree node available.\n");
		return -EINVAL;
	}

	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
	if (indio_dev == NULL)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	i2c_set_clientdata(client, indio_dev);

	indio_dev->dev.parent = &client->dev;
	indio_dev->dev.of_node = client->dev.of_node;
	indio_dev->name = dev_name(&client->dev);
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->info = &nau7802_info;

	st->client = client;

	/* Reset the device */
	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
				  NAU7802_PUCTRL_RR_BIT);
	if (ret < 0)
		return ret;

	/* Enter normal operation mode */
	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
				  NAU7802_PUCTRL_PUD_BIT);
	if (ret < 0)
		return ret;

	/*
	 * After about 200 usecs, the device should be ready and then
	 * the Power Up bit will be set to 1. If not, wait for it.
	 */
	udelay(210);
	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
	if (ret < 0)
		return ret;
	if (!(ret & NAU7802_PUCTRL_PUR_BIT))
		return ret;

	of_property_read_u32(np, "nuvoton,vldo", &tmp);
	st->vref_mv = tmp;

	data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT |
		NAU7802_PUCTRL_CS_BIT;
	if (tmp >= 2400)
		data |= NAU7802_PUCTRL_AVDDS_BIT;

	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data);
	if (ret < 0)
		return ret;
	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30);
	if (ret < 0)
		return ret;

	if (tmp >= 2400) {
		data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
		ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
						data);
		if (ret < 0)
			return ret;
	}

	/* Populate available ADC input ranges */
	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
		st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL)
					   >> (23 + i);

	init_completion(&st->value_ok);

	/*
	 * The ADC fires continuously and we can't do anything about
	 * it. So we need to have the IRQ disabled by default, and we
	 * will enable them back when we will need them..
	 */
	if (client->irq) {
		ret = request_threaded_irq(client->irq,
				NULL,
				nau7802_eoc_trigger,
				IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
				client->dev.driver->name,
				indio_dev);
		if (ret) {
			/*
			 * What may happen here is that our IRQ controller is
			 * not able to get level interrupt but this is required
			 * by this ADC as when going over 40 sample per second,
			 * the interrupt line may stay high between conversions.
			 * So, we continue no matter what but we switch to
			 * polling mode.
			 */
			dev_info(&client->dev,
				"Failed to allocate IRQ, using polling mode\n");
			client->irq = 0;
		} else
			disable_irq(client->irq);
	}

	if (!client->irq) {
		/*
		 * We are polling, use the fastest sample rate by
		 * default
		 */
		st->sample_rate = NAU7802_SAMP_FREQ_320;
		ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2,
					  NAU7802_CTRL2_CRS(st->sample_rate));
		if (ret)
			goto error_free_irq;
	}

	/* Setup the ADC channels available on the board */
	indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array);
	indio_dev->channels = nau7802_chan_array;

	mutex_init(&st->lock);
	mutex_init(&st->data_lock);

	ret = iio_device_register(indio_dev);
	if (ret < 0) {
		dev_err(&client->dev, "Couldn't register the device.\n");
		goto error_device_register;
	}

	return 0;

error_device_register:
	mutex_destroy(&st->lock);
	mutex_destroy(&st->data_lock);
error_free_irq:
	if (client->irq)
		free_irq(client->irq, indio_dev);

	return ret;
}

static int nau7802_remove(struct i2c_client *client)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	struct nau7802_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	mutex_destroy(&st->lock);
	mutex_destroy(&st->data_lock);
	if (client->irq)
		free_irq(client->irq, indio_dev);

	return 0;
}

static const struct i2c_device_id nau7802_i2c_id[] = {
	{ "nau7802", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id);

static const struct of_device_id nau7802_dt_ids[] = {
	{ .compatible = "nuvoton,nau7802" },
	{},
};
MODULE_DEVICE_TABLE(of, nau7802_dt_ids);

static struct i2c_driver nau7802_driver = {
	.probe = nau7802_probe,
	.remove = nau7802_remove,
	.id_table = nau7802_i2c_id,
	.driver = {
		   .name = "nau7802",
		   .of_match_table = nau7802_dt_ids,
	},
};

module_i2c_driver(nau7802_driver);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver");
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
Commit	Line	Data
8b20be87 AB	1	/*
	2	* Driver for the Nuvoton NAU7802 ADC
	3	*
	4	* Copyright 2013 Free Electrons
	5	*
	6	* Licensed under the GPLv2 or later.
	7	*/
	8
	9	#include <linux/delay.h>
	10	#include <linux/i2c.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/module.h>
	13	#include <linux/wait.h>
	14	#include <linux/log2.h>
62ba493e	15	#include <linux/of.h>
8b20be87 AB	16
	17	#include <linux/iio/iio.h>
	18	#include <linux/iio/sysfs.h>
	19
	20	#define NAU7802_REG_PUCTRL 0x00
	21	#define NAU7802_PUCTRL_RR(x) (x << 0)
	22	#define NAU7802_PUCTRL_RR_BIT NAU7802_PUCTRL_RR(1)
	23	#define NAU7802_PUCTRL_PUD(x) (x << 1)
	24	#define NAU7802_PUCTRL_PUD_BIT NAU7802_PUCTRL_PUD(1)
	25	#define NAU7802_PUCTRL_PUA(x) (x << 2)
	26	#define NAU7802_PUCTRL_PUA_BIT NAU7802_PUCTRL_PUA(1)
	27	#define NAU7802_PUCTRL_PUR(x) (x << 3)
	28	#define NAU7802_PUCTRL_PUR_BIT NAU7802_PUCTRL_PUR(1)
	29	#define NAU7802_PUCTRL_CS(x) (x << 4)
	30	#define NAU7802_PUCTRL_CS_BIT NAU7802_PUCTRL_CS(1)
	31	#define NAU7802_PUCTRL_CR(x) (x << 5)
	32	#define NAU7802_PUCTRL_CR_BIT NAU7802_PUCTRL_CR(1)
	33	#define NAU7802_PUCTRL_AVDDS(x) (x << 7)
	34	#define NAU7802_PUCTRL_AVDDS_BIT NAU7802_PUCTRL_AVDDS(1)
	35	#define NAU7802_REG_CTRL1 0x01
	36	#define NAU7802_CTRL1_VLDO(x) (x << 3)
	37	#define NAU7802_CTRL1_GAINS(x) (x)
	38	#define NAU7802_CTRL1_GAINS_BITS 0x07
	39	#define NAU7802_REG_CTRL2 0x02
	40	#define NAU7802_CTRL2_CHS(x) (x << 7)
	41	#define NAU7802_CTRL2_CRS(x) (x << 4)
	42	#define NAU7802_SAMP_FREQ_320 0x07
	43	#define NAU7802_CTRL2_CHS_BIT NAU7802_CTRL2_CHS(1)
	44	#define NAU7802_REG_ADC_B2 0x12
	45	#define NAU7802_REG_ADC_B1 0x13
	46	#define NAU7802_REG_ADC_B0 0x14
	47	#define NAU7802_REG_ADC_CTRL 0x15
	48
	49	#define NAU7802_MIN_CONVERSIONS 6
	50
	51	struct nau7802_state {
	52	struct i2c_client *client;
	53	s32 last_value;
	54	struct mutex lock;
	55	struct mutex data_lock;
	56	u32 vref_mv;
	57	u32 conversion_count;
	58	u32 min_conversions;
	59	u8 sample_rate;
	60	u32 scale_avail[8];
	61	struct completion value_ok;
	62	};
	63
	64	#define NAU7802_CHANNEL(chan) { \
	65	.type = IIO_VOLTAGE, \
	66	.indexed = 1, \
	67	.channel = (chan), \
	68	.scan_index = (chan), \
	69	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
	70	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \| \
	71	BIT(IIO_CHAN_INFO_SAMP_FREQ) \
	72	}
	73
	74	static const struct iio_chan_spec nau7802_chan_array[] = {
	75	NAU7802_CHANNEL(0),
	76	NAU7802_CHANNEL(1),
	77	};
	78
	79	static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80,
80	10, 10, 10, 320};
81
44072b2c QS	82	static ssize_t nau7802_show_scales(struct device *dev,
	83	struct device_attribute attr, char buf)
	84	{
	85	struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev));
	86	int i, len = 0;
	87
	88	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
	89	len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09d ",
	90	st->scale_avail[i]);
	91
	92	buf[len-1] = '\n';
	93
	94	return len;
	95	}
	96
8b20be87 AB	97	static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320");
8b20be87 AB	98
44072b2c QS	99	static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, nau7802_show_scales,
	100	NULL, 0);
	101
8b20be87 AB	102	static struct attribute *nau7802_attributes[] = {
8b20be87 AB	103	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
44072b2c	104	&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
8b20be87 AB	105	NULL
	106	};
	107
	108	static const struct attribute_group nau7802_attribute_group = {
	109	.attrs = nau7802_attributes,
	110	};
	111
	112	static int nau7802_set_gain(struct nau7802_state *st, int gain)
	113	{
	114	int ret;
	115
	116	mutex_lock(&st->lock);
	117	st->conversion_count = 0;
	118
	119	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
	120	if (ret < 0)
	121	goto nau7802_sysfs_set_gain_out;
	122	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
	123	(ret & (~NAU7802_CTRL1_GAINS_BITS)) \|
	124	gain);
	125
	126	nau7802_sysfs_set_gain_out:
	127	mutex_unlock(&st->lock);
	128
	129	return ret;
	130	}
	131
	132	static int nau7802_read_conversion(struct nau7802_state *st)
	133	{
	134	int data;
	135
	136	mutex_lock(&st->data_lock);
	137	data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2);
	138	if (data < 0)
	139	goto nau7802_read_conversion_out;
	140	st->last_value = data << 16;
	141
	142	data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1);
	143	if (data < 0)
	144	goto nau7802_read_conversion_out;
	145	st->last_value \|= data << 8;
	146
	147	data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0);
	148	if (data < 0)
	149	goto nau7802_read_conversion_out;
	150	st->last_value \|= data;
	151
	152	st->last_value = sign_extend32(st->last_value, 23);
	153
	154	nau7802_read_conversion_out:
	155	mutex_unlock(&st->data_lock);
	156
	157	return data;
	158	}
	159
	160	/*
	161	* Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
	162	*/
	163	static int nau7802_sync(struct nau7802_state *st)
	164	{
	165	int ret;
	166
	167	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
	168	if (ret < 0)
169	return ret;
170	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
171	ret \| NAU7802_PUCTRL_CS_BIT);
172
173	return ret;
174	}
175
176	static irqreturn_t nau7802_eoc_trigger(int irq, void *private)
177	{
178	struct iio_dev *indio_dev = private;
179	struct nau7802_state *st = iio_priv(indio_dev);
180	int status;
181
182	status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
183	if (status < 0)
184	return IRQ_HANDLED;
185
186	if (!(status & NAU7802_PUCTRL_CR_BIT))
187	return IRQ_NONE;
188
189	if (nau7802_read_conversion(st) < 0)
190	return IRQ_HANDLED;
191
192	/*
193	* Because there is actually only one ADC for both channels, we have to
194	* wait for enough conversions to happen before getting a significant
195	* value when changing channels and the values are far apart.
196	*/
197	if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
198	st->conversion_count++;
199	if (st->conversion_count >= NAU7802_MIN_CONVERSIONS)
cba4985e	200	complete(&st->value_ok);
8b20be87 AB	201
	202	return IRQ_HANDLED;
	203	}
	204
	205	static int nau7802_read_irq(struct iio_dev *indio_dev,
	206	struct iio_chan_spec const *chan,
	207	int *val)
	208	{
	209	struct nau7802_state *st = iio_priv(indio_dev);
	210	int ret;
	211
16735d02	212	reinit_completion(&st->value_ok);
8b20be87 AB	213	enable_irq(st->client->irq);
	214
	215	nau7802_sync(st);
	216
	217	/* read registers to ensure we flush everything */
	218	ret = nau7802_read_conversion(st);
	219	if (ret < 0)
	220	goto read_chan_info_failure;
	221
	222	/* Wait for a conversion to finish */
	223	ret = wait_for_completion_interruptible_timeout(&st->value_ok,
	224	msecs_to_jiffies(1000));
	225	if (ret == 0)
	226	ret = -ETIMEDOUT;
	227
	228	if (ret < 0)
	229	goto read_chan_info_failure;
	230
	231	disable_irq(st->client->irq);
	232
	233	*val = st->last_value;
	234
	235	return IIO_VAL_INT;
	236
	237	read_chan_info_failure:
	238	disable_irq(st->client->irq);
	239
	240	return ret;
	241	}
	242
	243	static int nau7802_read_poll(struct iio_dev *indio_dev,
	244	struct iio_chan_spec const *chan,
	245	int *val)
	246	{
	247	struct nau7802_state *st = iio_priv(indio_dev);
	248	int ret;
	249
	250	nau7802_sync(st);
	251
	252	/* read registers to ensure we flush everything */
	253	ret = nau7802_read_conversion(st);
	254	if (ret < 0)
	255	return ret;
	256
	257	/*
	258	* Because there is actually only one ADC for both channels, we have to
	259	* wait for enough conversions to happen before getting a significant
	260	* value when changing channels and the values are far appart.
	261	*/
	262	do {
	263	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
	264	if (ret < 0)
	265	return ret;
	266
	267	while (!(ret & NAU7802_PUCTRL_CR_BIT)) {
	268	if (st->sample_rate != NAU7802_SAMP_FREQ_320)
	269	msleep(20);
	270	else
	271	mdelay(4);
	272	ret = i2c_smbus_read_byte_data(st->client,
	273	NAU7802_REG_PUCTRL);
	274	if (ret < 0)
	275	return ret;
	276	}
277
278	ret = nau7802_read_conversion(st);
279	if (ret < 0)
280	return ret;
281	if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
282	st->conversion_count++;
283	} while (st->conversion_count < NAU7802_MIN_CONVERSIONS);
284
285	*val = st->last_value;
286
287	return IIO_VAL_INT;
288	}
289
290	static int nau7802_read_raw(struct iio_dev *indio_dev,
291	struct iio_chan_spec const *chan,
292	int val, int val2, long mask)
293	{
294	struct nau7802_state *st = iio_priv(indio_dev);
295	int ret;
296
297	switch (mask) {
298	case IIO_CHAN_INFO_RAW:
299	mutex_lock(&st->lock);
300	/*
301	* Select the channel to use
302	* - Channel 1 is value 0 in the CHS register
303	* - Channel 2 is value 1 in the CHS register
304	*/
305	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2);
306	if (ret < 0) {
307	mutex_unlock(&st->lock);
308	return ret;
309	}
310
311	if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) \|\|
312	(!(ret & NAU7802_CTRL2_CHS_BIT) &&
313	chan->channel)) {
314	st->conversion_count = 0;
315	ret = i2c_smbus_write_byte_data(st->client,
316	NAU7802_REG_CTRL2,
317	NAU7802_CTRL2_CHS(chan->channel) \|
318	NAU7802_CTRL2_CRS(st->sample_rate));
319
320	if (ret < 0) {
321	mutex_unlock(&st->lock);
322	return ret;
323	}
324	}
325
326	if (st->client->irq)
327	ret = nau7802_read_irq(indio_dev, chan, val);
328	else
329	ret = nau7802_read_poll(indio_dev, chan, val);
330
331	mutex_unlock(&st->lock);
332	return ret;
333
334	case IIO_CHAN_INFO_SCALE:
335	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
336	if (ret < 0)
337	return ret;
338
339	/*
340	* We have 24 bits of signed data, that means 23 bits of data
341	* plus the sign bit
342	*/
343	*val = st->vref_mv;
344	*val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS);
345
346	return IIO_VAL_FRACTIONAL_LOG2;
347
348	case IIO_CHAN_INFO_SAMP_FREQ:
349	*val = nau7802_sample_freq_avail[st->sample_rate];
350	*val2 = 0;
351	return IIO_VAL_INT;
352
353	default:
354	break;
355	}
356
357	return -EINVAL;
358	}
359
360	static int nau7802_write_raw(struct iio_dev *indio_dev,
361	struct iio_chan_spec const *chan,
362	int val, int val2, long mask)
363	{
364	struct nau7802_state *st = iio_priv(indio_dev);
365	int i, ret;
366
367	switch (mask) {
368	case IIO_CHAN_INFO_SCALE:
369	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
370	if (val2 == st->scale_avail[i])
371	return nau7802_set_gain(st, i);
372
373	break;
374
375	case IIO_CHAN_INFO_SAMP_FREQ:
376	for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++)
377	if (val == nau7802_sample_freq_avail[i]) {
378	mutex_lock(&st->lock);
379	st->sample_rate = i;
380	st->conversion_count = 0;
381	ret = i2c_smbus_write_byte_data(st->client,
382	NAU7802_REG_CTRL2,
383	NAU7802_CTRL2_CRS(st->sample_rate));
384	mutex_unlock(&st->lock);
385	return ret;
386	}
387
388	break;
389
390	default:
391	break;
392	}
393
394	return -EINVAL;
395	}
396
397	static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
398	struct iio_chan_spec const *chan,
399	long mask)
400	{
401	return IIO_VAL_INT_PLUS_NANO;
402	}
403
404	static const struct iio_info nau7802_info = {
405	.driver_module = THIS_MODULE,
406	.read_raw = &nau7802_read_raw,
407	.write_raw = &nau7802_write_raw,
408	.write_raw_get_fmt = nau7802_write_raw_get_fmt,
409	.attrs = &nau7802_attribute_group,
410	};
411
412	static int nau7802_probe(struct i2c_client *client,
413	const struct i2c_device_id *id)
414	{
415	struct iio_dev *indio_dev;
416	struct nau7802_state *st;
417	struct device_node *np = client->dev.of_node;
418	int i, ret;
419	u8 data;
420	u32 tmp = 0;
421
422	if (!client->dev.of_node) {
423	dev_err(&client->dev, "No device tree node available.\n");
424	return -EINVAL;
425	}
426
ed6886c1	427	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
8b20be87 AB	428	if (indio_dev == NULL)
	429	return -ENOMEM;
	430
	431	st = iio_priv(indio_dev);
	432
	433	i2c_set_clientdata(client, indio_dev);
	434
	435	indio_dev->dev.parent = &client->dev;
b541eaff	436	indio_dev->dev.of_node = client->dev.of_node;
8b20be87 AB	437	indio_dev->name = dev_name(&client->dev);
	438	indio_dev->modes = INDIO_DIRECT_MODE;
	439	indio_dev->info = &nau7802_info;
	440
	441	st->client = client;
	442
	443	/* Reset the device */
	444	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
	445	NAU7802_PUCTRL_RR_BIT);
	446	if (ret < 0)
ed6886c1	447	return ret;
8b20be87 AB	448
	449	/* Enter normal operation mode */
	450	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
	451	NAU7802_PUCTRL_PUD_BIT);
	452	if (ret < 0)
ed6886c1	453	return ret;
8b20be87 AB	454
	455	/*
	456	* After about 200 usecs, the device should be ready and then
	457	* the Power Up bit will be set to 1. If not, wait for it.
	458	*/
	459	udelay(210);
	460	ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
	461	if (ret < 0)
ed6886c1	462	return ret;
8b20be87	463	if (!(ret & NAU7802_PUCTRL_PUR_BIT))
ed6886c1	464	return ret;
8b20be87 AB	465
	466	of_property_read_u32(np, "nuvoton,vldo", &tmp);
	467	st->vref_mv = tmp;
	468
	469	data = NAU7802_PUCTRL_PUD_BIT \| NAU7802_PUCTRL_PUA_BIT \|
	470	NAU7802_PUCTRL_CS_BIT;
	471	if (tmp >= 2400)
	472	data \|= NAU7802_PUCTRL_AVDDS_BIT;
	473
	474	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data);
	475	if (ret < 0)
ed6886c1	476	return ret;
8b20be87 AB	477	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30);
8b20be87 AB	478	if (ret < 0)
ed6886c1	479	return ret;
8b20be87 AB	480
	481	if (tmp >= 2400) {
	482	data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
	483	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
	484	data);
	485	if (ret < 0)
ed6886c1	486	return ret;
8b20be87 AB	487	}
	488
	489	/* Populate available ADC input ranges */
	490	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
	491	st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL)
	492	>> (23 + i);
	493
	494	init_completion(&st->value_ok);
	495
	496	/*
	497	* The ADC fires continuously and we can't do anything about
	498	* it. So we need to have the IRQ disabled by default, and we
	499	* will enable them back when we will need them..
	500	*/
	501	if (client->irq) {
	502	ret = request_threaded_irq(client->irq,
	503	NULL,
	504	nau7802_eoc_trigger,
	505	IRQF_TRIGGER_HIGH \| IRQF_ONESHOT,
	506	client->dev.driver->name,
	507	indio_dev);
	508	if (ret) {
	509	/*
	510	* What may happen here is that our IRQ controller is
	511	* not able to get level interrupt but this is required
	512	* by this ADC as when going over 40 sample per second,
	513	* the interrupt line may stay high between conversions.
	514	* So, we continue no matter what but we switch to
	515	* polling mode.
	516	*/
	517	dev_info(&client->dev,
	518	"Failed to allocate IRQ, using polling mode\n");
	519	client->irq = 0;
	520	} else
	521	disable_irq(client->irq);
	522	}
	523
	524	if (!client->irq) {
	525	/*
	526	* We are polling, use the fastest sample rate by
	527	* default
	528	*/
	529	st->sample_rate = NAU7802_SAMP_FREQ_320;
	530	ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2,
	531	NAU7802_CTRL2_CRS(st->sample_rate));
	532	if (ret)
	533	goto error_free_irq;
	534	}
	535
	536	/* Setup the ADC channels available on the board */
	537	indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array);
	538	indio_dev->channels = nau7802_chan_array;
	539
	540	mutex_init(&st->lock);
	541	mutex_init(&st->data_lock);
	542
	543	ret = iio_device_register(indio_dev);
	544	if (ret < 0) {
	545	dev_err(&client->dev, "Couldn't register the device.\n");
	546	goto error_device_register;
	547	}
	548
	549	return 0;
	550
551	error_device_register:
552	mutex_destroy(&st->lock);
553	mutex_destroy(&st->data_lock);
554	error_free_irq:
555	if (client->irq)
556	free_irq(client->irq, indio_dev);
8b20be87 AB	557
	558	return ret;
	559	}
	560
	561	static int nau7802_remove(struct i2c_client *client)
	562	{
	563	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	564	struct nau7802_state *st = iio_priv(indio_dev);
	565
	566	iio_device_unregister(indio_dev);
	567	mutex_destroy(&st->lock);
	568	mutex_destroy(&st->data_lock);
	569	if (client->irq)
	570	free_irq(client->irq, indio_dev);
8b20be87 AB	571
	572	return 0;
	573	}
	574
	575	static const struct i2c_device_id nau7802_i2c_id[] = {
	576	{ "nau7802", 0 },
	577	{ }
	578	};
	579	MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id);
	580
	581	static const struct of_device_id nau7802_dt_ids[] = {
	582	{ .compatible = "nuvoton,nau7802" },
	583	{},
	584	};
	585	MODULE_DEVICE_TABLE(of, nau7802_dt_ids);
	586
	587	static struct i2c_driver nau7802_driver = {
	588	.probe = nau7802_probe,
	589	.remove = nau7802_remove,
	590	.id_table = nau7802_i2c_id,
	591	.driver = {
	592	.name = "nau7802",
d453a4ab	593	.of_match_table = nau7802_dt_ids,
8b20be87 AB	594	},
	595	};
	596
	597	module_i2c_driver(nau7802_driver);
	598
	599	MODULE_LICENSE("GPL");
	600	MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver");
	601	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
	602	MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");