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8b20be87 AB |
1 | /* |
2 | * Driver for the Nuvoton NAU7802 ADC | |
3 | * | |
4 | * Copyright 2013 Free Electrons | |
5 | * | |
6 | * Licensed under the GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/delay.h> | |
10 | #include <linux/i2c.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/wait.h> | |
14 | #include <linux/log2.h> | |
15 | ||
16 | #include <linux/iio/iio.h> | |
17 | #include <linux/iio/sysfs.h> | |
18 | ||
19 | #define NAU7802_REG_PUCTRL 0x00 | |
20 | #define NAU7802_PUCTRL_RR(x) (x << 0) | |
21 | #define NAU7802_PUCTRL_RR_BIT NAU7802_PUCTRL_RR(1) | |
22 | #define NAU7802_PUCTRL_PUD(x) (x << 1) | |
23 | #define NAU7802_PUCTRL_PUD_BIT NAU7802_PUCTRL_PUD(1) | |
24 | #define NAU7802_PUCTRL_PUA(x) (x << 2) | |
25 | #define NAU7802_PUCTRL_PUA_BIT NAU7802_PUCTRL_PUA(1) | |
26 | #define NAU7802_PUCTRL_PUR(x) (x << 3) | |
27 | #define NAU7802_PUCTRL_PUR_BIT NAU7802_PUCTRL_PUR(1) | |
28 | #define NAU7802_PUCTRL_CS(x) (x << 4) | |
29 | #define NAU7802_PUCTRL_CS_BIT NAU7802_PUCTRL_CS(1) | |
30 | #define NAU7802_PUCTRL_CR(x) (x << 5) | |
31 | #define NAU7802_PUCTRL_CR_BIT NAU7802_PUCTRL_CR(1) | |
32 | #define NAU7802_PUCTRL_AVDDS(x) (x << 7) | |
33 | #define NAU7802_PUCTRL_AVDDS_BIT NAU7802_PUCTRL_AVDDS(1) | |
34 | #define NAU7802_REG_CTRL1 0x01 | |
35 | #define NAU7802_CTRL1_VLDO(x) (x << 3) | |
36 | #define NAU7802_CTRL1_GAINS(x) (x) | |
37 | #define NAU7802_CTRL1_GAINS_BITS 0x07 | |
38 | #define NAU7802_REG_CTRL2 0x02 | |
39 | #define NAU7802_CTRL2_CHS(x) (x << 7) | |
40 | #define NAU7802_CTRL2_CRS(x) (x << 4) | |
41 | #define NAU7802_SAMP_FREQ_320 0x07 | |
42 | #define NAU7802_CTRL2_CHS_BIT NAU7802_CTRL2_CHS(1) | |
43 | #define NAU7802_REG_ADC_B2 0x12 | |
44 | #define NAU7802_REG_ADC_B1 0x13 | |
45 | #define NAU7802_REG_ADC_B0 0x14 | |
46 | #define NAU7802_REG_ADC_CTRL 0x15 | |
47 | ||
48 | #define NAU7802_MIN_CONVERSIONS 6 | |
49 | ||
50 | struct nau7802_state { | |
51 | struct i2c_client *client; | |
52 | s32 last_value; | |
53 | struct mutex lock; | |
54 | struct mutex data_lock; | |
55 | u32 vref_mv; | |
56 | u32 conversion_count; | |
57 | u32 min_conversions; | |
58 | u8 sample_rate; | |
59 | u32 scale_avail[8]; | |
60 | struct completion value_ok; | |
61 | }; | |
62 | ||
63 | #define NAU7802_CHANNEL(chan) { \ | |
64 | .type = IIO_VOLTAGE, \ | |
65 | .indexed = 1, \ | |
66 | .channel = (chan), \ | |
67 | .scan_index = (chan), \ | |
68 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
69 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ | |
70 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \ | |
71 | } | |
72 | ||
73 | static const struct iio_chan_spec nau7802_chan_array[] = { | |
74 | NAU7802_CHANNEL(0), | |
75 | NAU7802_CHANNEL(1), | |
76 | }; | |
77 | ||
78 | static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80, | |
79 | 10, 10, 10, 320}; | |
80 | ||
81 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320"); | |
82 | ||
83 | static struct attribute *nau7802_attributes[] = { | |
84 | &iio_const_attr_sampling_frequency_available.dev_attr.attr, | |
85 | NULL | |
86 | }; | |
87 | ||
88 | static const struct attribute_group nau7802_attribute_group = { | |
89 | .attrs = nau7802_attributes, | |
90 | }; | |
91 | ||
92 | static int nau7802_set_gain(struct nau7802_state *st, int gain) | |
93 | { | |
94 | int ret; | |
95 | ||
96 | mutex_lock(&st->lock); | |
97 | st->conversion_count = 0; | |
98 | ||
99 | ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1); | |
100 | if (ret < 0) | |
101 | goto nau7802_sysfs_set_gain_out; | |
102 | ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1, | |
103 | (ret & (~NAU7802_CTRL1_GAINS_BITS)) | | |
104 | gain); | |
105 | ||
106 | nau7802_sysfs_set_gain_out: | |
107 | mutex_unlock(&st->lock); | |
108 | ||
109 | return ret; | |
110 | } | |
111 | ||
112 | static int nau7802_read_conversion(struct nau7802_state *st) | |
113 | { | |
114 | int data; | |
115 | ||
116 | mutex_lock(&st->data_lock); | |
117 | data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2); | |
118 | if (data < 0) | |
119 | goto nau7802_read_conversion_out; | |
120 | st->last_value = data << 16; | |
121 | ||
122 | data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1); | |
123 | if (data < 0) | |
124 | goto nau7802_read_conversion_out; | |
125 | st->last_value |= data << 8; | |
126 | ||
127 | data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0); | |
128 | if (data < 0) | |
129 | goto nau7802_read_conversion_out; | |
130 | st->last_value |= data; | |
131 | ||
132 | st->last_value = sign_extend32(st->last_value, 23); | |
133 | ||
134 | nau7802_read_conversion_out: | |
135 | mutex_unlock(&st->data_lock); | |
136 | ||
137 | return data; | |
138 | } | |
139 | ||
140 | /* | |
141 | * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT | |
142 | */ | |
143 | static int nau7802_sync(struct nau7802_state *st) | |
144 | { | |
145 | int ret; | |
146 | ||
147 | ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL); | |
148 | if (ret < 0) | |
149 | return ret; | |
150 | ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, | |
151 | ret | NAU7802_PUCTRL_CS_BIT); | |
152 | ||
153 | return ret; | |
154 | } | |
155 | ||
156 | static irqreturn_t nau7802_eoc_trigger(int irq, void *private) | |
157 | { | |
158 | struct iio_dev *indio_dev = private; | |
159 | struct nau7802_state *st = iio_priv(indio_dev); | |
160 | int status; | |
161 | ||
162 | status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL); | |
163 | if (status < 0) | |
164 | return IRQ_HANDLED; | |
165 | ||
166 | if (!(status & NAU7802_PUCTRL_CR_BIT)) | |
167 | return IRQ_NONE; | |
168 | ||
169 | if (nau7802_read_conversion(st) < 0) | |
170 | return IRQ_HANDLED; | |
171 | ||
172 | /* | |
173 | * Because there is actually only one ADC for both channels, we have to | |
174 | * wait for enough conversions to happen before getting a significant | |
175 | * value when changing channels and the values are far apart. | |
176 | */ | |
177 | if (st->conversion_count < NAU7802_MIN_CONVERSIONS) | |
178 | st->conversion_count++; | |
179 | if (st->conversion_count >= NAU7802_MIN_CONVERSIONS) | |
180 | complete_all(&st->value_ok); | |
181 | ||
182 | return IRQ_HANDLED; | |
183 | } | |
184 | ||
185 | static int nau7802_read_irq(struct iio_dev *indio_dev, | |
186 | struct iio_chan_spec const *chan, | |
187 | int *val) | |
188 | { | |
189 | struct nau7802_state *st = iio_priv(indio_dev); | |
190 | int ret; | |
191 | ||
192 | INIT_COMPLETION(st->value_ok); | |
193 | enable_irq(st->client->irq); | |
194 | ||
195 | nau7802_sync(st); | |
196 | ||
197 | /* read registers to ensure we flush everything */ | |
198 | ret = nau7802_read_conversion(st); | |
199 | if (ret < 0) | |
200 | goto read_chan_info_failure; | |
201 | ||
202 | /* Wait for a conversion to finish */ | |
203 | ret = wait_for_completion_interruptible_timeout(&st->value_ok, | |
204 | msecs_to_jiffies(1000)); | |
205 | if (ret == 0) | |
206 | ret = -ETIMEDOUT; | |
207 | ||
208 | if (ret < 0) | |
209 | goto read_chan_info_failure; | |
210 | ||
211 | disable_irq(st->client->irq); | |
212 | ||
213 | *val = st->last_value; | |
214 | ||
215 | return IIO_VAL_INT; | |
216 | ||
217 | read_chan_info_failure: | |
218 | disable_irq(st->client->irq); | |
219 | ||
220 | return ret; | |
221 | } | |
222 | ||
223 | static int nau7802_read_poll(struct iio_dev *indio_dev, | |
224 | struct iio_chan_spec const *chan, | |
225 | int *val) | |
226 | { | |
227 | struct nau7802_state *st = iio_priv(indio_dev); | |
228 | int ret; | |
229 | ||
230 | nau7802_sync(st); | |
231 | ||
232 | /* read registers to ensure we flush everything */ | |
233 | ret = nau7802_read_conversion(st); | |
234 | if (ret < 0) | |
235 | return ret; | |
236 | ||
237 | /* | |
238 | * Because there is actually only one ADC for both channels, we have to | |
239 | * wait for enough conversions to happen before getting a significant | |
240 | * value when changing channels and the values are far appart. | |
241 | */ | |
242 | do { | |
243 | ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL); | |
244 | if (ret < 0) | |
245 | return ret; | |
246 | ||
247 | while (!(ret & NAU7802_PUCTRL_CR_BIT)) { | |
248 | if (st->sample_rate != NAU7802_SAMP_FREQ_320) | |
249 | msleep(20); | |
250 | else | |
251 | mdelay(4); | |
252 | ret = i2c_smbus_read_byte_data(st->client, | |
253 | NAU7802_REG_PUCTRL); | |
254 | if (ret < 0) | |
255 | return ret; | |
256 | } | |
257 | ||
258 | ret = nau7802_read_conversion(st); | |
259 | if (ret < 0) | |
260 | return ret; | |
261 | if (st->conversion_count < NAU7802_MIN_CONVERSIONS) | |
262 | st->conversion_count++; | |
263 | } while (st->conversion_count < NAU7802_MIN_CONVERSIONS); | |
264 | ||
265 | *val = st->last_value; | |
266 | ||
267 | return IIO_VAL_INT; | |
268 | } | |
269 | ||
270 | static int nau7802_read_raw(struct iio_dev *indio_dev, | |
271 | struct iio_chan_spec const *chan, | |
272 | int *val, int *val2, long mask) | |
273 | { | |
274 | struct nau7802_state *st = iio_priv(indio_dev); | |
275 | int ret; | |
276 | ||
277 | switch (mask) { | |
278 | case IIO_CHAN_INFO_RAW: | |
279 | mutex_lock(&st->lock); | |
280 | /* | |
281 | * Select the channel to use | |
282 | * - Channel 1 is value 0 in the CHS register | |
283 | * - Channel 2 is value 1 in the CHS register | |
284 | */ | |
285 | ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2); | |
286 | if (ret < 0) { | |
287 | mutex_unlock(&st->lock); | |
288 | return ret; | |
289 | } | |
290 | ||
291 | if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) || | |
292 | (!(ret & NAU7802_CTRL2_CHS_BIT) && | |
293 | chan->channel)) { | |
294 | st->conversion_count = 0; | |
295 | ret = i2c_smbus_write_byte_data(st->client, | |
296 | NAU7802_REG_CTRL2, | |
297 | NAU7802_CTRL2_CHS(chan->channel) | | |
298 | NAU7802_CTRL2_CRS(st->sample_rate)); | |
299 | ||
300 | if (ret < 0) { | |
301 | mutex_unlock(&st->lock); | |
302 | return ret; | |
303 | } | |
304 | } | |
305 | ||
306 | if (st->client->irq) | |
307 | ret = nau7802_read_irq(indio_dev, chan, val); | |
308 | else | |
309 | ret = nau7802_read_poll(indio_dev, chan, val); | |
310 | ||
311 | mutex_unlock(&st->lock); | |
312 | return ret; | |
313 | ||
314 | case IIO_CHAN_INFO_SCALE: | |
315 | ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1); | |
316 | if (ret < 0) | |
317 | return ret; | |
318 | ||
319 | /* | |
320 | * We have 24 bits of signed data, that means 23 bits of data | |
321 | * plus the sign bit | |
322 | */ | |
323 | *val = st->vref_mv; | |
324 | *val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS); | |
325 | ||
326 | return IIO_VAL_FRACTIONAL_LOG2; | |
327 | ||
328 | case IIO_CHAN_INFO_SAMP_FREQ: | |
329 | *val = nau7802_sample_freq_avail[st->sample_rate]; | |
330 | *val2 = 0; | |
331 | return IIO_VAL_INT; | |
332 | ||
333 | default: | |
334 | break; | |
335 | } | |
336 | ||
337 | return -EINVAL; | |
338 | } | |
339 | ||
340 | static int nau7802_write_raw(struct iio_dev *indio_dev, | |
341 | struct iio_chan_spec const *chan, | |
342 | int val, int val2, long mask) | |
343 | { | |
344 | struct nau7802_state *st = iio_priv(indio_dev); | |
345 | int i, ret; | |
346 | ||
347 | switch (mask) { | |
348 | case IIO_CHAN_INFO_SCALE: | |
349 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) | |
350 | if (val2 == st->scale_avail[i]) | |
351 | return nau7802_set_gain(st, i); | |
352 | ||
353 | break; | |
354 | ||
355 | case IIO_CHAN_INFO_SAMP_FREQ: | |
356 | for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++) | |
357 | if (val == nau7802_sample_freq_avail[i]) { | |
358 | mutex_lock(&st->lock); | |
359 | st->sample_rate = i; | |
360 | st->conversion_count = 0; | |
361 | ret = i2c_smbus_write_byte_data(st->client, | |
362 | NAU7802_REG_CTRL2, | |
363 | NAU7802_CTRL2_CRS(st->sample_rate)); | |
364 | mutex_unlock(&st->lock); | |
365 | return ret; | |
366 | } | |
367 | ||
368 | break; | |
369 | ||
370 | default: | |
371 | break; | |
372 | } | |
373 | ||
374 | return -EINVAL; | |
375 | } | |
376 | ||
377 | static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev, | |
378 | struct iio_chan_spec const *chan, | |
379 | long mask) | |
380 | { | |
381 | return IIO_VAL_INT_PLUS_NANO; | |
382 | } | |
383 | ||
384 | static const struct iio_info nau7802_info = { | |
385 | .driver_module = THIS_MODULE, | |
386 | .read_raw = &nau7802_read_raw, | |
387 | .write_raw = &nau7802_write_raw, | |
388 | .write_raw_get_fmt = nau7802_write_raw_get_fmt, | |
389 | .attrs = &nau7802_attribute_group, | |
390 | }; | |
391 | ||
392 | static int nau7802_probe(struct i2c_client *client, | |
393 | const struct i2c_device_id *id) | |
394 | { | |
395 | struct iio_dev *indio_dev; | |
396 | struct nau7802_state *st; | |
397 | struct device_node *np = client->dev.of_node; | |
398 | int i, ret; | |
399 | u8 data; | |
400 | u32 tmp = 0; | |
401 | ||
402 | if (!client->dev.of_node) { | |
403 | dev_err(&client->dev, "No device tree node available.\n"); | |
404 | return -EINVAL; | |
405 | } | |
406 | ||
407 | indio_dev = iio_device_alloc(sizeof(*st)); | |
408 | if (indio_dev == NULL) | |
409 | return -ENOMEM; | |
410 | ||
411 | st = iio_priv(indio_dev); | |
412 | ||
413 | i2c_set_clientdata(client, indio_dev); | |
414 | ||
415 | indio_dev->dev.parent = &client->dev; | |
416 | indio_dev->name = dev_name(&client->dev); | |
417 | indio_dev->modes = INDIO_DIRECT_MODE; | |
418 | indio_dev->info = &nau7802_info; | |
419 | ||
420 | st->client = client; | |
421 | ||
422 | /* Reset the device */ | |
423 | ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, | |
424 | NAU7802_PUCTRL_RR_BIT); | |
425 | if (ret < 0) | |
426 | goto error_free_indio; | |
427 | ||
428 | /* Enter normal operation mode */ | |
429 | ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, | |
430 | NAU7802_PUCTRL_PUD_BIT); | |
431 | if (ret < 0) | |
432 | goto error_free_indio; | |
433 | ||
434 | /* | |
435 | * After about 200 usecs, the device should be ready and then | |
436 | * the Power Up bit will be set to 1. If not, wait for it. | |
437 | */ | |
438 | udelay(210); | |
439 | ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL); | |
440 | if (ret < 0) | |
441 | goto error_free_indio; | |
442 | if (!(ret & NAU7802_PUCTRL_PUR_BIT)) | |
443 | goto error_free_indio; | |
444 | ||
445 | of_property_read_u32(np, "nuvoton,vldo", &tmp); | |
446 | st->vref_mv = tmp; | |
447 | ||
448 | data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT | | |
449 | NAU7802_PUCTRL_CS_BIT; | |
450 | if (tmp >= 2400) | |
451 | data |= NAU7802_PUCTRL_AVDDS_BIT; | |
452 | ||
453 | ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data); | |
454 | if (ret < 0) | |
455 | goto error_free_indio; | |
456 | ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30); | |
457 | if (ret < 0) | |
458 | goto error_free_indio; | |
459 | ||
460 | if (tmp >= 2400) { | |
461 | data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300); | |
462 | ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1, | |
463 | data); | |
464 | if (ret < 0) | |
465 | goto error_free_indio; | |
466 | } | |
467 | ||
468 | /* Populate available ADC input ranges */ | |
469 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) | |
470 | st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL) | |
471 | >> (23 + i); | |
472 | ||
473 | init_completion(&st->value_ok); | |
474 | ||
475 | /* | |
476 | * The ADC fires continuously and we can't do anything about | |
477 | * it. So we need to have the IRQ disabled by default, and we | |
478 | * will enable them back when we will need them.. | |
479 | */ | |
480 | if (client->irq) { | |
481 | ret = request_threaded_irq(client->irq, | |
482 | NULL, | |
483 | nau7802_eoc_trigger, | |
484 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, | |
485 | client->dev.driver->name, | |
486 | indio_dev); | |
487 | if (ret) { | |
488 | /* | |
489 | * What may happen here is that our IRQ controller is | |
490 | * not able to get level interrupt but this is required | |
491 | * by this ADC as when going over 40 sample per second, | |
492 | * the interrupt line may stay high between conversions. | |
493 | * So, we continue no matter what but we switch to | |
494 | * polling mode. | |
495 | */ | |
496 | dev_info(&client->dev, | |
497 | "Failed to allocate IRQ, using polling mode\n"); | |
498 | client->irq = 0; | |
499 | } else | |
500 | disable_irq(client->irq); | |
501 | } | |
502 | ||
503 | if (!client->irq) { | |
504 | /* | |
505 | * We are polling, use the fastest sample rate by | |
506 | * default | |
507 | */ | |
508 | st->sample_rate = NAU7802_SAMP_FREQ_320; | |
509 | ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2, | |
510 | NAU7802_CTRL2_CRS(st->sample_rate)); | |
511 | if (ret) | |
512 | goto error_free_irq; | |
513 | } | |
514 | ||
515 | /* Setup the ADC channels available on the board */ | |
516 | indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array); | |
517 | indio_dev->channels = nau7802_chan_array; | |
518 | ||
519 | mutex_init(&st->lock); | |
520 | mutex_init(&st->data_lock); | |
521 | ||
522 | ret = iio_device_register(indio_dev); | |
523 | if (ret < 0) { | |
524 | dev_err(&client->dev, "Couldn't register the device.\n"); | |
525 | goto error_device_register; | |
526 | } | |
527 | ||
528 | return 0; | |
529 | ||
530 | error_device_register: | |
531 | mutex_destroy(&st->lock); | |
532 | mutex_destroy(&st->data_lock); | |
533 | error_free_irq: | |
534 | if (client->irq) | |
535 | free_irq(client->irq, indio_dev); | |
536 | error_free_indio: | |
537 | iio_device_free(indio_dev); | |
538 | ||
539 | return ret; | |
540 | } | |
541 | ||
542 | static int nau7802_remove(struct i2c_client *client) | |
543 | { | |
544 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | |
545 | struct nau7802_state *st = iio_priv(indio_dev); | |
546 | ||
547 | iio_device_unregister(indio_dev); | |
548 | mutex_destroy(&st->lock); | |
549 | mutex_destroy(&st->data_lock); | |
550 | if (client->irq) | |
551 | free_irq(client->irq, indio_dev); | |
552 | iio_device_free(indio_dev); | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static const struct i2c_device_id nau7802_i2c_id[] = { | |
558 | { "nau7802", 0 }, | |
559 | { } | |
560 | }; | |
561 | MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id); | |
562 | ||
563 | static const struct of_device_id nau7802_dt_ids[] = { | |
564 | { .compatible = "nuvoton,nau7802" }, | |
565 | {}, | |
566 | }; | |
567 | MODULE_DEVICE_TABLE(of, nau7802_dt_ids); | |
568 | ||
569 | static struct i2c_driver nau7802_driver = { | |
570 | .probe = nau7802_probe, | |
571 | .remove = nau7802_remove, | |
572 | .id_table = nau7802_i2c_id, | |
573 | .driver = { | |
574 | .name = "nau7802", | |
575 | .of_match_table = of_match_ptr(nau7802_dt_ids), | |
576 | }, | |
577 | }; | |
578 | ||
579 | module_i2c_driver(nau7802_driver); | |
580 | ||
581 | MODULE_LICENSE("GPL"); | |
582 | MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver"); | |
583 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
584 | MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>"); |