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d1caa990 QS |
1 | /* ADC driver for sunxi platforms' (A10, A13 and A31) GPADC |
2 | * | |
3 | * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it under | |
6 | * the terms of the GNU General Public License version 2 as published by the | |
7 | * Free Software Foundation. | |
8 | * | |
9 | * The Allwinner SoCs all have an ADC that can also act as a touchscreen | |
10 | * controller and a thermal sensor. | |
11 | * The thermal sensor works only when the ADC acts as a touchscreen controller | |
12 | * and is configured to throw an interrupt every fixed periods of time (let say | |
13 | * every X seconds). | |
14 | * One would be tempted to disable the IP on the hardware side rather than | |
15 | * disabling interrupts to save some power but that resets the internal clock of | |
16 | * the IP, resulting in having to wait X seconds every time we want to read the | |
17 | * value of the thermal sensor. | |
18 | * This is also the reason of using autosuspend in pm_runtime. If there was no | |
19 | * autosuspend, the thermal sensor would need X seconds after every | |
20 | * pm_runtime_get_sync to get a value from the ADC. The autosuspend allows the | |
21 | * thermal sensor to be requested again in a certain time span before it gets | |
22 | * shutdown for not being used. | |
23 | */ | |
24 | ||
25 | #include <linux/completion.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/of.h> | |
30 | #include <linux/of_device.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/pm_runtime.h> | |
33 | #include <linux/regmap.h> | |
34 | #include <linux/thermal.h> | |
35 | #include <linux/delay.h> | |
36 | ||
37 | #include <linux/iio/iio.h> | |
38 | #include <linux/iio/driver.h> | |
39 | #include <linux/iio/machine.h> | |
40 | #include <linux/mfd/sun4i-gpadc.h> | |
41 | ||
42 | static unsigned int sun4i_gpadc_chan_select(unsigned int chan) | |
43 | { | |
44 | return SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(chan); | |
45 | } | |
46 | ||
47 | static unsigned int sun6i_gpadc_chan_select(unsigned int chan) | |
48 | { | |
49 | return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan); | |
50 | } | |
51 | ||
52 | struct gpadc_data { | |
53 | int temp_offset; | |
54 | int temp_scale; | |
55 | unsigned int tp_mode_en; | |
56 | unsigned int tp_adc_select; | |
57 | unsigned int (*adc_chan_select)(unsigned int chan); | |
58 | unsigned int adc_chan_mask; | |
59 | }; | |
60 | ||
61 | static const struct gpadc_data sun4i_gpadc_data = { | |
62 | .temp_offset = -1932, | |
63 | .temp_scale = 133, | |
64 | .tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN, | |
65 | .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT, | |
66 | .adc_chan_select = &sun4i_gpadc_chan_select, | |
67 | .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK, | |
68 | }; | |
69 | ||
70 | static const struct gpadc_data sun5i_gpadc_data = { | |
71 | .temp_offset = -1447, | |
72 | .temp_scale = 100, | |
73 | .tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN, | |
74 | .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT, | |
75 | .adc_chan_select = &sun4i_gpadc_chan_select, | |
76 | .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK, | |
77 | }; | |
78 | ||
79 | static const struct gpadc_data sun6i_gpadc_data = { | |
80 | .temp_offset = -1623, | |
81 | .temp_scale = 167, | |
82 | .tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN, | |
83 | .tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT, | |
84 | .adc_chan_select = &sun6i_gpadc_chan_select, | |
85 | .adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK, | |
86 | }; | |
87 | ||
88 | struct sun4i_gpadc_iio { | |
89 | struct iio_dev *indio_dev; | |
90 | struct completion completion; | |
91 | int temp_data; | |
92 | u32 adc_data; | |
93 | struct regmap *regmap; | |
94 | unsigned int fifo_data_irq; | |
95 | atomic_t ignore_fifo_data_irq; | |
96 | unsigned int temp_data_irq; | |
97 | atomic_t ignore_temp_data_irq; | |
98 | const struct gpadc_data *data; | |
99 | /* prevents concurrent reads of temperature and ADC */ | |
100 | struct mutex mutex; | |
101 | }; | |
102 | ||
103 | #define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \ | |
104 | .type = IIO_VOLTAGE, \ | |
105 | .indexed = 1, \ | |
106 | .channel = _channel, \ | |
107 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
108 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ | |
109 | .datasheet_name = _name, \ | |
110 | } | |
111 | ||
112 | static struct iio_map sun4i_gpadc_hwmon_maps[] = { | |
113 | { | |
114 | .adc_channel_label = "temp_adc", | |
115 | .consumer_dev_name = "iio_hwmon.0", | |
116 | }, | |
117 | { /* sentinel */ }, | |
118 | }; | |
119 | ||
120 | static const struct iio_chan_spec sun4i_gpadc_channels[] = { | |
121 | SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"), | |
122 | SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"), | |
123 | SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"), | |
124 | SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"), | |
125 | { | |
126 | .type = IIO_TEMP, | |
127 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | | |
128 | BIT(IIO_CHAN_INFO_SCALE) | | |
129 | BIT(IIO_CHAN_INFO_OFFSET), | |
130 | .datasheet_name = "temp_adc", | |
131 | }, | |
132 | }; | |
133 | ||
134 | static const struct iio_chan_spec sun4i_gpadc_channels_no_temp[] = { | |
135 | SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"), | |
136 | SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"), | |
137 | SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"), | |
138 | SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"), | |
139 | }; | |
140 | ||
141 | static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, int channel, | |
142 | unsigned int irq) | |
143 | { | |
144 | struct sun4i_gpadc_iio *info = iio_priv(indio_dev); | |
145 | int ret; | |
146 | u32 reg; | |
147 | ||
148 | pm_runtime_get_sync(indio_dev->dev.parent); | |
149 | ||
150 | reinit_completion(&info->completion); | |
151 | ||
152 | ret = regmap_write(info->regmap, SUN4I_GPADC_INT_FIFOC, | |
153 | SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(1) | | |
154 | SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH); | |
155 | if (ret) | |
156 | return ret; | |
157 | ||
158 | ret = regmap_read(info->regmap, SUN4I_GPADC_CTRL1, ®); | |
159 | if (ret) | |
160 | return ret; | |
161 | ||
162 | if (irq == info->fifo_data_irq) { | |
163 | ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1, | |
164 | info->data->tp_mode_en | | |
165 | info->data->tp_adc_select | | |
166 | info->data->adc_chan_select(channel)); | |
167 | /* | |
168 | * When the IP changes channel, it needs a bit of time to get | |
169 | * correct values. | |
170 | */ | |
171 | if ((reg & info->data->adc_chan_mask) != | |
172 | info->data->adc_chan_select(channel)) | |
173 | mdelay(10); | |
174 | ||
175 | } else { | |
176 | /* | |
177 | * The temperature sensor returns valid data only when the ADC | |
178 | * operates in touchscreen mode. | |
179 | */ | |
180 | ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1, | |
181 | info->data->tp_mode_en); | |
182 | } | |
183 | ||
184 | if (ret) | |
185 | return ret; | |
186 | ||
187 | /* | |
188 | * When the IP changes mode between ADC or touchscreen, it | |
189 | * needs a bit of time to get correct values. | |
190 | */ | |
191 | if ((reg & info->data->tp_adc_select) != info->data->tp_adc_select) | |
192 | mdelay(100); | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | static int sun4i_gpadc_read(struct iio_dev *indio_dev, int channel, int *val, | |
198 | unsigned int irq) | |
199 | { | |
200 | struct sun4i_gpadc_iio *info = iio_priv(indio_dev); | |
201 | int ret; | |
202 | ||
203 | mutex_lock(&info->mutex); | |
204 | ||
205 | ret = sun4i_prepare_for_irq(indio_dev, channel, irq); | |
206 | if (ret) | |
207 | goto err; | |
208 | ||
209 | enable_irq(irq); | |
210 | ||
211 | /* | |
212 | * The temperature sensor throws an interruption periodically (currently | |
213 | * set at periods of ~0.6s in sun4i_gpadc_runtime_resume). A 1s delay | |
214 | * makes sure an interruption occurs in normal conditions. If it doesn't | |
215 | * occur, then there is a timeout. | |
216 | */ | |
217 | if (!wait_for_completion_timeout(&info->completion, | |
218 | msecs_to_jiffies(1000))) { | |
219 | ret = -ETIMEDOUT; | |
220 | goto err; | |
221 | } | |
222 | ||
223 | if (irq == info->fifo_data_irq) | |
224 | *val = info->adc_data; | |
225 | else | |
226 | *val = info->temp_data; | |
227 | ||
228 | ret = 0; | |
229 | pm_runtime_mark_last_busy(indio_dev->dev.parent); | |
230 | ||
231 | err: | |
232 | pm_runtime_put_autosuspend(indio_dev->dev.parent); | |
233 | mutex_unlock(&info->mutex); | |
234 | ||
235 | return ret; | |
236 | } | |
237 | ||
238 | static int sun4i_gpadc_adc_read(struct iio_dev *indio_dev, int channel, | |
239 | int *val) | |
240 | { | |
241 | struct sun4i_gpadc_iio *info = iio_priv(indio_dev); | |
242 | ||
243 | return sun4i_gpadc_read(indio_dev, channel, val, info->fifo_data_irq); | |
244 | } | |
245 | ||
246 | static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val) | |
247 | { | |
248 | struct sun4i_gpadc_iio *info = iio_priv(indio_dev); | |
249 | ||
250 | return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq); | |
251 | } | |
252 | ||
253 | static int sun4i_gpadc_temp_offset(struct iio_dev *indio_dev, int *val) | |
254 | { | |
255 | struct sun4i_gpadc_iio *info = iio_priv(indio_dev); | |
256 | ||
257 | *val = info->data->temp_offset; | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | static int sun4i_gpadc_temp_scale(struct iio_dev *indio_dev, int *val) | |
263 | { | |
264 | struct sun4i_gpadc_iio *info = iio_priv(indio_dev); | |
265 | ||
266 | *val = info->data->temp_scale; | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev, | |
272 | struct iio_chan_spec const *chan, int *val, | |
273 | int *val2, long mask) | |
274 | { | |
275 | int ret; | |
276 | ||
277 | switch (mask) { | |
278 | case IIO_CHAN_INFO_OFFSET: | |
279 | ret = sun4i_gpadc_temp_offset(indio_dev, val); | |
280 | if (ret) | |
281 | return ret; | |
282 | ||
283 | return IIO_VAL_INT; | |
284 | case IIO_CHAN_INFO_RAW: | |
285 | if (chan->type == IIO_VOLTAGE) | |
286 | ret = sun4i_gpadc_adc_read(indio_dev, chan->channel, | |
287 | val); | |
288 | else | |
289 | ret = sun4i_gpadc_temp_read(indio_dev, val); | |
290 | ||
291 | if (ret) | |
292 | return ret; | |
293 | ||
294 | return IIO_VAL_INT; | |
295 | case IIO_CHAN_INFO_SCALE: | |
296 | if (chan->type == IIO_VOLTAGE) { | |
297 | /* 3000mV / 4096 * raw */ | |
298 | *val = 0; | |
299 | *val2 = 732421875; | |
300 | return IIO_VAL_INT_PLUS_NANO; | |
301 | } | |
302 | ||
303 | ret = sun4i_gpadc_temp_scale(indio_dev, val); | |
304 | if (ret) | |
305 | return ret; | |
306 | ||
307 | return IIO_VAL_INT; | |
308 | default: | |
309 | return -EINVAL; | |
310 | } | |
311 | ||
312 | return -EINVAL; | |
313 | } | |
314 | ||
315 | static const struct iio_info sun4i_gpadc_iio_info = { | |
316 | .read_raw = sun4i_gpadc_read_raw, | |
317 | .driver_module = THIS_MODULE, | |
318 | }; | |
319 | ||
320 | static irqreturn_t sun4i_gpadc_temp_data_irq_handler(int irq, void *dev_id) | |
321 | { | |
322 | struct sun4i_gpadc_iio *info = dev_id; | |
323 | ||
324 | if (atomic_read(&info->ignore_temp_data_irq)) | |
325 | goto out; | |
326 | ||
327 | if (!regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, &info->temp_data)) | |
328 | complete(&info->completion); | |
329 | ||
330 | out: | |
331 | disable_irq_nosync(info->temp_data_irq); | |
332 | return IRQ_HANDLED; | |
333 | } | |
334 | ||
335 | static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id) | |
336 | { | |
337 | struct sun4i_gpadc_iio *info = dev_id; | |
338 | ||
339 | if (atomic_read(&info->ignore_fifo_data_irq)) | |
340 | goto out; | |
341 | ||
342 | if (!regmap_read(info->regmap, SUN4I_GPADC_DATA, &info->adc_data)) | |
343 | complete(&info->completion); | |
344 | ||
345 | out: | |
346 | disable_irq_nosync(info->fifo_data_irq); | |
347 | return IRQ_HANDLED; | |
348 | } | |
349 | ||
350 | static int sun4i_gpadc_runtime_suspend(struct device *dev) | |
351 | { | |
352 | struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev)); | |
353 | ||
354 | /* Disable the ADC on IP */ | |
355 | regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0); | |
356 | /* Disable temperature sensor on IP */ | |
357 | regmap_write(info->regmap, SUN4I_GPADC_TPR, 0); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static int sun4i_gpadc_runtime_resume(struct device *dev) | |
363 | { | |
364 | struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev)); | |
365 | ||
366 | /* clkin = 6MHz */ | |
367 | regmap_write(info->regmap, SUN4I_GPADC_CTRL0, | |
368 | SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) | | |
369 | SUN4I_GPADC_CTRL0_FS_DIV(7) | | |
370 | SUN4I_GPADC_CTRL0_T_ACQ(63)); | |
371 | regmap_write(info->regmap, SUN4I_GPADC_CTRL1, info->data->tp_mode_en); | |
372 | regmap_write(info->regmap, SUN4I_GPADC_CTRL3, | |
373 | SUN4I_GPADC_CTRL3_FILTER_EN | | |
374 | SUN4I_GPADC_CTRL3_FILTER_TYPE(1)); | |
375 | /* period = SUN4I_GPADC_TPR_TEMP_PERIOD * 256 * 16 / clkin; ~0.6s */ | |
376 | regmap_write(info->regmap, SUN4I_GPADC_TPR, | |
377 | SUN4I_GPADC_TPR_TEMP_ENABLE | | |
378 | SUN4I_GPADC_TPR_TEMP_PERIOD(800)); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static int sun4i_gpadc_get_temp(void *data, int *temp) | |
384 | { | |
385 | struct sun4i_gpadc_iio *info = (struct sun4i_gpadc_iio *)data; | |
386 | int val, scale, offset; | |
387 | ||
388 | if (sun4i_gpadc_temp_read(info->indio_dev, &val)) | |
389 | return -ETIMEDOUT; | |
390 | ||
391 | sun4i_gpadc_temp_scale(info->indio_dev, &scale); | |
392 | sun4i_gpadc_temp_offset(info->indio_dev, &offset); | |
393 | ||
394 | *temp = (val + offset) * scale; | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | static const struct thermal_zone_of_device_ops sun4i_ts_tz_ops = { | |
400 | .get_temp = &sun4i_gpadc_get_temp, | |
401 | }; | |
402 | ||
403 | static const struct dev_pm_ops sun4i_gpadc_pm_ops = { | |
404 | .runtime_suspend = &sun4i_gpadc_runtime_suspend, | |
405 | .runtime_resume = &sun4i_gpadc_runtime_resume, | |
406 | }; | |
407 | ||
408 | static int sun4i_irq_init(struct platform_device *pdev, const char *name, | |
409 | irq_handler_t handler, const char *devname, | |
410 | unsigned int *irq, atomic_t *atomic) | |
411 | { | |
412 | int ret; | |
413 | struct sun4i_gpadc_dev *mfd_dev = dev_get_drvdata(pdev->dev.parent); | |
414 | struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(&pdev->dev)); | |
415 | ||
416 | /* | |
417 | * Once the interrupt is activated, the IP continuously performs | |
418 | * conversions thus throws interrupts. The interrupt is activated right | |
419 | * after being requested but we want to control when these interrupts | |
420 | * occur thus we disable it right after being requested. However, an | |
421 | * interrupt might occur between these two instructions and we have to | |
422 | * make sure that does not happen, by using atomic flags. We set the | |
423 | * flag before requesting the interrupt and unset it right after | |
424 | * disabling the interrupt. When an interrupt occurs between these two | |
425 | * instructions, reading the atomic flag will tell us to ignore the | |
426 | * interrupt. | |
427 | */ | |
428 | atomic_set(atomic, 1); | |
429 | ||
430 | ret = platform_get_irq_byname(pdev, name); | |
431 | if (ret < 0) { | |
432 | dev_err(&pdev->dev, "no %s interrupt registered\n", name); | |
433 | return ret; | |
434 | } | |
435 | ||
436 | ret = regmap_irq_get_virq(mfd_dev->regmap_irqc, ret); | |
437 | if (ret < 0) { | |
438 | dev_err(&pdev->dev, "failed to get virq for irq %s\n", name); | |
439 | return ret; | |
440 | } | |
441 | ||
442 | *irq = ret; | |
443 | ret = devm_request_any_context_irq(&pdev->dev, *irq, handler, 0, | |
444 | devname, info); | |
445 | if (ret < 0) { | |
446 | dev_err(&pdev->dev, "could not request %s interrupt: %d\n", | |
447 | name, ret); | |
448 | return ret; | |
449 | } | |
450 | ||
451 | disable_irq(*irq); | |
452 | atomic_set(atomic, 0); | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static int sun4i_gpadc_probe(struct platform_device *pdev) | |
458 | { | |
459 | struct sun4i_gpadc_iio *info; | |
460 | struct iio_dev *indio_dev; | |
461 | int ret; | |
462 | struct sun4i_gpadc_dev *sun4i_gpadc_dev; | |
463 | ||
464 | sun4i_gpadc_dev = dev_get_drvdata(pdev->dev.parent); | |
465 | ||
466 | indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); | |
467 | if (!indio_dev) | |
468 | return -ENOMEM; | |
469 | ||
470 | info = iio_priv(indio_dev); | |
471 | platform_set_drvdata(pdev, indio_dev); | |
472 | ||
473 | mutex_init(&info->mutex); | |
474 | info->regmap = sun4i_gpadc_dev->regmap; | |
475 | info->indio_dev = indio_dev; | |
476 | init_completion(&info->completion); | |
477 | indio_dev->name = dev_name(&pdev->dev); | |
478 | indio_dev->dev.parent = &pdev->dev; | |
479 | indio_dev->dev.of_node = pdev->dev.of_node; | |
480 | indio_dev->info = &sun4i_gpadc_iio_info; | |
481 | indio_dev->modes = INDIO_DIRECT_MODE; | |
482 | indio_dev->num_channels = ARRAY_SIZE(sun4i_gpadc_channels); | |
483 | indio_dev->channels = sun4i_gpadc_channels; | |
484 | ||
485 | info->data = (struct gpadc_data *)platform_get_device_id(pdev)->driver_data; | |
486 | ||
487 | /* | |
488 | * Since the controller needs to be in touchscreen mode for its thermal | |
489 | * sensor to operate properly, and that switching between the two modes | |
490 | * needs a delay, always registering in the thermal framework will | |
491 | * significantly slow down the conversion rate of the ADCs. | |
492 | * | |
493 | * Therefore, instead of depending on THERMAL_OF in Kconfig, we only | |
494 | * register the sensor if that option is enabled, eventually leaving | |
495 | * that choice to the user. | |
496 | */ | |
497 | ||
498 | if (IS_ENABLED(CONFIG_THERMAL_OF)) { | |
499 | /* | |
500 | * This driver is a child of an MFD which has a node in the DT | |
501 | * but not its children, because of DT backward compatibility | |
502 | * for A10, A13 and A31 SoCs. Therefore, the resulting devices | |
503 | * of this driver do not have an of_node variable. | |
504 | * However, its parent (the MFD driver) has an of_node variable | |
505 | * and since devm_thermal_zone_of_sensor_register uses its first | |
506 | * argument to match the phandle defined in the node of the | |
507 | * thermal driver with the of_node of the device passed as first | |
508 | * argument and the third argument to call ops from | |
509 | * thermal_zone_of_device_ops, the solution is to use the parent | |
510 | * device as first argument to match the phandle with its | |
511 | * of_node, and the device from this driver as third argument to | |
512 | * return the temperature. | |
513 | */ | |
514 | struct thermal_zone_device *tzd; | |
515 | tzd = devm_thermal_zone_of_sensor_register(pdev->dev.parent, 0, | |
516 | info, | |
517 | &sun4i_ts_tz_ops); | |
518 | if (IS_ERR(tzd)) { | |
519 | dev_err(&pdev->dev, | |
520 | "could not register thermal sensor: %ld\n", | |
521 | PTR_ERR(tzd)); | |
522 | ret = PTR_ERR(tzd); | |
523 | goto err; | |
524 | } | |
525 | } else { | |
526 | indio_dev->num_channels = | |
527 | ARRAY_SIZE(sun4i_gpadc_channels_no_temp); | |
528 | indio_dev->channels = sun4i_gpadc_channels_no_temp; | |
529 | } | |
530 | ||
531 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
532 | SUN4I_GPADC_AUTOSUSPEND_DELAY); | |
533 | pm_runtime_use_autosuspend(&pdev->dev); | |
534 | pm_runtime_set_suspended(&pdev->dev); | |
535 | pm_runtime_enable(&pdev->dev); | |
536 | ||
537 | if (IS_ENABLED(CONFIG_THERMAL_OF)) { | |
538 | ret = sun4i_irq_init(pdev, "TEMP_DATA_PENDING", | |
539 | sun4i_gpadc_temp_data_irq_handler, | |
540 | "temp_data", &info->temp_data_irq, | |
541 | &info->ignore_temp_data_irq); | |
542 | if (ret < 0) | |
543 | goto err; | |
544 | } | |
545 | ||
546 | ret = sun4i_irq_init(pdev, "FIFO_DATA_PENDING", | |
547 | sun4i_gpadc_fifo_data_irq_handler, "fifo_data", | |
548 | &info->fifo_data_irq, &info->ignore_fifo_data_irq); | |
549 | if (ret < 0) | |
550 | goto err; | |
551 | ||
552 | if (IS_ENABLED(CONFIG_THERMAL_OF)) { | |
553 | ret = iio_map_array_register(indio_dev, sun4i_gpadc_hwmon_maps); | |
554 | if (ret < 0) { | |
555 | dev_err(&pdev->dev, | |
556 | "failed to register iio map array\n"); | |
557 | goto err; | |
558 | } | |
559 | } | |
560 | ||
561 | ret = devm_iio_device_register(&pdev->dev, indio_dev); | |
562 | if (ret < 0) { | |
563 | dev_err(&pdev->dev, "could not register the device\n"); | |
564 | goto err_map; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | ||
569 | err_map: | |
570 | if (IS_ENABLED(CONFIG_THERMAL_OF)) | |
571 | iio_map_array_unregister(indio_dev); | |
572 | ||
573 | err: | |
574 | pm_runtime_put(&pdev->dev); | |
575 | pm_runtime_disable(&pdev->dev); | |
576 | ||
577 | return ret; | |
578 | } | |
579 | ||
580 | static int sun4i_gpadc_remove(struct platform_device *pdev) | |
581 | { | |
582 | struct iio_dev *indio_dev = platform_get_drvdata(pdev); | |
583 | ||
584 | pm_runtime_put(&pdev->dev); | |
585 | pm_runtime_disable(&pdev->dev); | |
586 | if (IS_ENABLED(CONFIG_THERMAL_OF)) | |
587 | iio_map_array_unregister(indio_dev); | |
588 | ||
589 | return 0; | |
590 | } | |
591 | ||
592 | static const struct platform_device_id sun4i_gpadc_id[] = { | |
593 | { "sun4i-a10-gpadc-iio", (kernel_ulong_t)&sun4i_gpadc_data }, | |
594 | { "sun5i-a13-gpadc-iio", (kernel_ulong_t)&sun5i_gpadc_data }, | |
595 | { "sun6i-a31-gpadc-iio", (kernel_ulong_t)&sun6i_gpadc_data }, | |
596 | { /* sentinel */ }, | |
597 | }; | |
598 | ||
599 | static struct platform_driver sun4i_gpadc_driver = { | |
600 | .driver = { | |
601 | .name = "sun4i-gpadc-iio", | |
602 | .pm = &sun4i_gpadc_pm_ops, | |
603 | }, | |
604 | .id_table = sun4i_gpadc_id, | |
605 | .probe = sun4i_gpadc_probe, | |
606 | .remove = sun4i_gpadc_remove, | |
607 | }; | |
608 | ||
609 | module_platform_driver(sun4i_gpadc_driver); | |
610 | ||
611 | MODULE_DESCRIPTION("ADC driver for sunxi platforms"); | |
612 | MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>"); | |
613 | MODULE_LICENSE("GPL v2"); |