[mirror_ubuntu-artful-kernel.git] / drivers / iio / adc / ti-ads1015.c

/*
 * ADS1015 - Texas Instruments Analog-to-Digital Converter
 *
 * Copyright (c) 2016, Intel Corporation.
 *
 * This file is subject to the terms and conditions of version 2 of
 * the GNU General Public License.  See the file COPYING in the main
 * directory of this archive for more details.
 *
 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
 *	* 0x48 - ADDR connected to Ground
 *	* 0x49 - ADDR connected to Vdd
 *	* 0x4A - ADDR connected to SDA
 *	* 0x4B - ADDR connected to SCL
 */

#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
#include <linux/mutex.h>
#include <linux/delay.h>

#include <linux/platform_data/ads1015.h>

#include <linux/iio/iio.h>
#include <linux/iio/types.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>

#define ADS1015_DRV_NAME "ads1015"

#define ADS1015_CONV_REG	0x00
#define ADS1015_CFG_REG		0x01

#define ADS1015_CFG_DR_SHIFT	5
#define ADS1015_CFG_MOD_SHIFT	8
#define ADS1015_CFG_PGA_SHIFT	9
#define ADS1015_CFG_MUX_SHIFT	12

#define ADS1015_CFG_DR_MASK	GENMASK(7, 5)
#define ADS1015_CFG_MOD_MASK	BIT(8)
#define ADS1015_CFG_PGA_MASK	GENMASK(11, 9)
#define ADS1015_CFG_MUX_MASK	GENMASK(14, 12)

/* device operating modes */
#define ADS1015_CONTINUOUS	0
#define ADS1015_SINGLESHOT	1

#define ADS1015_SLEEP_DELAY_MS		2000
#define ADS1015_DEFAULT_PGA		2
#define ADS1015_DEFAULT_DATA_RATE	4
#define ADS1015_DEFAULT_CHAN		0

enum chip_ids {
	ADS1015,
	ADS1115,
};

enum ads1015_channels {
	ADS1015_AIN0_AIN1 = 0,
	ADS1015_AIN0_AIN3,
	ADS1015_AIN1_AIN3,
	ADS1015_AIN2_AIN3,
	ADS1015_AIN0,
	ADS1015_AIN1,
	ADS1015_AIN2,
	ADS1015_AIN3,
	ADS1015_TIMESTAMP,
};

static const unsigned int ads1015_data_rate[] = {
	128, 250, 490, 920, 1600, 2400, 3300, 3300
};

static const unsigned int ads1115_data_rate[] = {
	8, 16, 32, 64, 128, 250, 475, 860
};

/*
 * Translation from PGA bits to full-scale positive and negative input voltage
 * range in mV
 */
static int ads1015_fullscale_range[] = {
	6144, 4096, 2048, 1024, 512, 256, 256, 256
};

#define ADS1015_V_CHAN(_chan, _addr) {				\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.address = _addr,					\
	.channel = _chan,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
				BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = _addr,					\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 12,					\
		.storagebits = 16,				\
		.shift = 4,					\
		.endianness = IIO_CPU,				\
	},							\
	.datasheet_name = "AIN"#_chan,				\
}

#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) {		\
	.type = IIO_VOLTAGE,					\
	.differential = 1,					\
	.indexed = 1,						\
	.address = _addr,					\
	.channel = _chan,					\
	.channel2 = _chan2,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
				BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = _addr,					\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 12,					\
		.storagebits = 16,				\
		.shift = 4,					\
		.endianness = IIO_CPU,				\
	},							\
	.datasheet_name = "AIN"#_chan"-AIN"#_chan2,		\
}

#define ADS1115_V_CHAN(_chan, _addr) {				\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.address = _addr,					\
	.channel = _chan,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
				BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = _addr,					\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 16,					\
		.storagebits = 16,				\
		.endianness = IIO_CPU,				\
	},							\
	.datasheet_name = "AIN"#_chan,				\
}

#define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) {		\
	.type = IIO_VOLTAGE,					\
	.differential = 1,					\
	.indexed = 1,						\
	.address = _addr,					\
	.channel = _chan,					\
	.channel2 = _chan2,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
				BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = _addr,					\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 16,					\
		.storagebits = 16,				\
		.endianness = IIO_CPU,				\
	},							\
	.datasheet_name = "AIN"#_chan"-AIN"#_chan2,		\
}

struct ads1015_data {
	struct regmap *regmap;
	/*
	 * Protects ADC ops, e.g: concurrent sysfs/buffered
	 * data reads, configuration updates
	 */
	struct mutex lock;
	struct ads1015_channel_data channel_data[ADS1015_CHANNELS];

	unsigned int *data_rate;
};

static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
{
	return (reg == ADS1015_CFG_REG);
}

static const struct regmap_config ads1015_regmap_config = {
	.reg_bits = 8,
	.val_bits = 16,
	.max_register = ADS1015_CFG_REG,
	.writeable_reg = ads1015_is_writeable_reg,
};

static const struct iio_chan_spec ads1015_channels[] = {
	ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
	ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
	ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
	ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
	ADS1015_V_CHAN(0, ADS1015_AIN0),
	ADS1015_V_CHAN(1, ADS1015_AIN1),
	ADS1015_V_CHAN(2, ADS1015_AIN2),
	ADS1015_V_CHAN(3, ADS1015_AIN3),
	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
};

static const struct iio_chan_spec ads1115_channels[] = {
	ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
	ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
	ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
	ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
	ADS1115_V_CHAN(0, ADS1015_AIN0),
	ADS1115_V_CHAN(1, ADS1015_AIN1),
	ADS1115_V_CHAN(2, ADS1015_AIN2),
	ADS1115_V_CHAN(3, ADS1015_AIN3),
	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
};

static int ads1015_set_power_state(struct ads1015_data *data, bool on)
{
	int ret;
	struct device *dev = regmap_get_device(data->regmap);

	if (on) {
		ret = pm_runtime_get_sync(dev);
		if (ret < 0)
			pm_runtime_put_noidle(dev);
	} else {
		pm_runtime_mark_last_busy(dev);
		ret = pm_runtime_put_autosuspend(dev);
	}

	return ret;
}

static
int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
{
	int ret, pga, dr, conv_time;
	bool change;

	if (chan < 0 || chan >= ADS1015_CHANNELS)
		return -EINVAL;

	pga = data->channel_data[chan].pga;
	dr = data->channel_data[chan].data_rate;

	ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
				       ADS1015_CFG_MUX_MASK |
				       ADS1015_CFG_PGA_MASK |
				       ADS1015_CFG_DR_MASK,
				       chan << ADS1015_CFG_MUX_SHIFT |
				       pga << ADS1015_CFG_PGA_SHIFT |
				       dr << ADS1015_CFG_DR_SHIFT,
				       &change);
	if (ret < 0)
		return ret;

	if (change) {
		conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
		usleep_range(conv_time, conv_time + 1);
	}

	return regmap_read(data->regmap, ADS1015_CONV_REG, val);
}

static irqreturn_t ads1015_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ads1015_data *data = iio_priv(indio_dev);
	s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding +  4x s16 timestamp */
	int chan, ret, res;

	memset(buf, 0, sizeof(buf));

	mutex_lock(&data->lock);
	chan = find_first_bit(indio_dev->active_scan_mask,
			      indio_dev->masklength);
	ret = ads1015_get_adc_result(data, chan, &res);
	if (ret < 0) {
		mutex_unlock(&data->lock);
		goto err;
	}

	buf[0] = res;
	mutex_unlock(&data->lock);

	iio_push_to_buffers_with_timestamp(indio_dev, buf,
					   iio_get_time_ns(indio_dev));

err:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static int ads1015_set_scale(struct ads1015_data *data,
			     struct iio_chan_spec const *chan,
			     int scale, int uscale)
{
	int i, ret, rindex = -1;
	int fullscale = div_s64((scale * 1000000LL + uscale) <<
				(chan->scan_type.realbits - 1), 1000000);

	for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
		if (ads1015_fullscale_range[i] == fullscale) {
			rindex = i;
			break;
		}
	}
	if (rindex < 0)
		return -EINVAL;

	ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				 ADS1015_CFG_PGA_MASK,
				 rindex << ADS1015_CFG_PGA_SHIFT);
	if (ret < 0)
		return ret;

	data->channel_data[chan->address].pga = rindex;

	return 0;
}

static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
		if (data->data_rate[i] == rate) {
			data->channel_data[chan].data_rate = i;
			return 0;
		}
	}

	return -EINVAL;
}

static int ads1015_read_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan, int *val,
			    int *val2, long mask)
{
	int ret, idx;
	struct ads1015_data *data = iio_priv(indio_dev);

	mutex_lock(&indio_dev->mlock);
	mutex_lock(&data->lock);
	switch (mask) {
	case IIO_CHAN_INFO_RAW: {
		int shift = chan->scan_type.shift;

		if (iio_buffer_enabled(indio_dev)) {
			ret = -EBUSY;
			break;
		}

		ret = ads1015_set_power_state(data, true);
		if (ret < 0)
			break;

		ret = ads1015_get_adc_result(data, chan->address, val);
		if (ret < 0) {
			ads1015_set_power_state(data, false);
			break;
		}

		*val = sign_extend32(*val >> shift, 15 - shift);

		ret = ads1015_set_power_state(data, false);
		if (ret < 0)
			break;

		ret = IIO_VAL_INT;
		break;
	}
	case IIO_CHAN_INFO_SCALE:
		idx = data->channel_data[chan->address].pga;
		*val = ads1015_fullscale_range[idx];
		*val2 = chan->scan_type.realbits - 1;
		ret = IIO_VAL_FRACTIONAL_LOG2;
		break;
	case IIO_CHAN_INFO_SAMP_FREQ:
		idx = data->channel_data[chan->address].data_rate;
		*val = data->data_rate[idx];
		ret = IIO_VAL_INT;
		break;
	default:
		ret = -EINVAL;
		break;
	}
	mutex_unlock(&data->lock);
	mutex_unlock(&indio_dev->mlock);

	return ret;
}

static int ads1015_write_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan, int val,
			     int val2, long mask)
{
	struct ads1015_data *data = iio_priv(indio_dev);
	int ret;

	mutex_lock(&data->lock);
	switch (mask) {
	case IIO_CHAN_INFO_SCALE:
		ret = ads1015_set_scale(data, chan, val, val2);
		break;
	case IIO_CHAN_INFO_SAMP_FREQ:
		ret = ads1015_set_data_rate(data, chan->address, val);
		break;
	default:
		ret = -EINVAL;
		break;
	}
	mutex_unlock(&data->lock);

	return ret;
}

static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
{
	return ads1015_set_power_state(iio_priv(indio_dev), true);
}

static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
{
	return ads1015_set_power_state(iio_priv(indio_dev), false);
}

static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
	.preenable	= ads1015_buffer_preenable,
	.postenable	= iio_triggered_buffer_postenable,
	.predisable	= iio_triggered_buffer_predisable,
	.postdisable	= ads1015_buffer_postdisable,
	.validate_scan_mask = &iio_validate_scan_mask_onehot,
};

static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
	"3 2 1 0.5 0.25 0.125");
static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
	"0.1875 0.125 0.0625 0.03125 0.015625 0.007813");

static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
	sampling_frequency_available, "128 250 490 920 1600 2400 3300");
static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
	sampling_frequency_available, "8 16 32 64 128 250 475 860");

static struct attribute *ads1015_attributes[] = {
	&iio_const_attr_ads1015_scale_available.dev_attr.attr,
	&iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
	NULL,
};

static const struct attribute_group ads1015_attribute_group = {
	.attrs = ads1015_attributes,
};

static struct attribute *ads1115_attributes[] = {
	&iio_const_attr_ads1115_scale_available.dev_attr.attr,
	&iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
	NULL,
};

static const struct attribute_group ads1115_attribute_group = {
	.attrs = ads1115_attributes,
};

static const struct iio_info ads1015_info = {
	.driver_module	= THIS_MODULE,
	.read_raw	= ads1015_read_raw,
	.write_raw	= ads1015_write_raw,
	.attrs          = &ads1015_attribute_group,
};

static const struct iio_info ads1115_info = {
	.driver_module	= THIS_MODULE,
	.read_raw	= ads1015_read_raw,
	.write_raw	= ads1015_write_raw,
	.attrs          = &ads1115_attribute_group,
};

#ifdef CONFIG_OF
static int ads1015_get_channels_config_of(struct i2c_client *client)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	struct ads1015_data *data = iio_priv(indio_dev);
	struct device_node *node;

	if (!client->dev.of_node ||
	    !of_get_next_child(client->dev.of_node, NULL))
		return -EINVAL;

	for_each_child_of_node(client->dev.of_node, node) {
		u32 pval;
		unsigned int channel;
		unsigned int pga = ADS1015_DEFAULT_PGA;
		unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;

		if (of_property_read_u32(node, "reg", &pval)) {
			dev_err(&client->dev, "invalid reg on %s\n",
				node->full_name);
			continue;
		}

		channel = pval;
		if (channel >= ADS1015_CHANNELS) {
			dev_err(&client->dev,
				"invalid channel index %d on %s\n",
				channel, node->full_name);
			continue;
		}

		if (!of_property_read_u32(node, "ti,gain", &pval)) {
			pga = pval;
			if (pga > 6) {
				dev_err(&client->dev, "invalid gain on %s\n",
					node->full_name);
				of_node_put(node);
				return -EINVAL;
			}
		}

		if (!of_property_read_u32(node, "ti,datarate", &pval)) {
			data_rate = pval;
			if (data_rate > 7) {
				dev_err(&client->dev,
					"invalid data_rate on %s\n",
					node->full_name);
				of_node_put(node);
				return -EINVAL;
			}
		}

		data->channel_data[channel].pga = pga;
		data->channel_data[channel].data_rate = data_rate;
	}

	return 0;
}
#endif

static void ads1015_get_channels_config(struct i2c_client *client)
{
	unsigned int k;

	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	struct ads1015_data *data = iio_priv(indio_dev);
	struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);

	/* prefer platform data */
	if (pdata) {
		memcpy(data->channel_data, pdata->channel_data,
		       sizeof(data->channel_data));
		return;
	}

#ifdef CONFIG_OF
	if (!ads1015_get_channels_config_of(client))
		return;
#endif
	/* fallback on default configuration */
	for (k = 0; k < ADS1015_CHANNELS; ++k) {
		data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
		data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
	}
}

static int ads1015_probe(struct i2c_client *client,
			 const struct i2c_device_id *id)
{
	struct iio_dev *indio_dev;
	struct ads1015_data *data;
	int ret;
	enum chip_ids chip;

	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
	if (!indio_dev)
		return -ENOMEM;

	data = iio_priv(indio_dev);
	i2c_set_clientdata(client, indio_dev);

	mutex_init(&data->lock);

	indio_dev->dev.parent = &client->dev;
	indio_dev->dev.of_node = client->dev.of_node;
	indio_dev->name = ADS1015_DRV_NAME;
	indio_dev->modes = INDIO_DIRECT_MODE;

	if (client->dev.of_node)
		chip = (enum chip_ids)of_device_get_match_data(&client->dev);
	else
		chip = id->driver_data;
	switch (chip) {
	case ADS1015:
		indio_dev->channels = ads1015_channels;
		indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
		indio_dev->info = &ads1015_info;
		data->data_rate = (unsigned int *) &ads1015_data_rate;
		break;
	case ADS1115:
		indio_dev->channels = ads1115_channels;
		indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
		indio_dev->info = &ads1115_info;
		data->data_rate = (unsigned int *) &ads1115_data_rate;
		break;
	}

	/* we need to keep this ABI the same as used by hwmon ADS1015 driver */
	ads1015_get_channels_config(client);

	data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
	if (IS_ERR(data->regmap)) {
		dev_err(&client->dev, "Failed to allocate register map\n");
		return PTR_ERR(data->regmap);
	}

	ret = iio_triggered_buffer_setup(indio_dev, NULL,
					 ads1015_trigger_handler,
					 &ads1015_buffer_setup_ops);
	if (ret < 0) {
		dev_err(&client->dev, "iio triggered buffer setup failed\n");
		return ret;
	}
	ret = pm_runtime_set_active(&client->dev);
	if (ret)
		goto err_buffer_cleanup;
	pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
	pm_runtime_use_autosuspend(&client->dev);
	pm_runtime_enable(&client->dev);

	ret = iio_device_register(indio_dev);
	if (ret < 0) {
		dev_err(&client->dev, "Failed to register IIO device\n");
		goto err_buffer_cleanup;
	}

	return 0;

err_buffer_cleanup:
	iio_triggered_buffer_cleanup(indio_dev);

	return ret;
}

static int ads1015_remove(struct i2c_client *client)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	struct ads1015_data *data = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);

	pm_runtime_disable(&client->dev);
	pm_runtime_set_suspended(&client->dev);
	pm_runtime_put_noidle(&client->dev);

	iio_triggered_buffer_cleanup(indio_dev);

	/* power down single shot mode */
	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				  ADS1015_CFG_MOD_MASK,
				  ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
}

#ifdef CONFIG_PM
static int ads1015_runtime_suspend(struct device *dev)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
	struct ads1015_data *data = iio_priv(indio_dev);

	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				  ADS1015_CFG_MOD_MASK,
				  ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
}

static int ads1015_runtime_resume(struct device *dev)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
	struct ads1015_data *data = iio_priv(indio_dev);

	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				  ADS1015_CFG_MOD_MASK,
				  ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
}
#endif

static const struct dev_pm_ops ads1015_pm_ops = {
	SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
			   ads1015_runtime_resume, NULL)
};

static const struct i2c_device_id ads1015_id[] = {
	{"ads1015", ADS1015},
	{"ads1115", ADS1115},
	{}
};
MODULE_DEVICE_TABLE(i2c, ads1015_id);

static const struct of_device_id ads1015_of_match[] = {
	{
		.compatible = "ti,ads1015",
		.data = (void *)ADS1015
	},
	{
		.compatible = "ti,ads1115",
		.data = (void *)ADS1115
	},
	{}
};
MODULE_DEVICE_TABLE(of, ads1015_of_match);

static struct i2c_driver ads1015_driver = {
	.driver = {
		.name = ADS1015_DRV_NAME,
		.of_match_table = ads1015_of_match,
		.pm = &ads1015_pm_ops,
	},
	.probe		= ads1015_probe,
	.remove		= ads1015_remove,
	.id_table	= ads1015_id,
};

module_i2c_driver(ads1015_driver);

MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ecc24e72 DB	1	/*
	2	* ADS1015 - Texas Instruments Analog-to-Digital Converter
	3	*
	4	* Copyright (c) 2016, Intel Corporation.
	5	*
	6	* This file is subject to the terms and conditions of version 2 of
	7	* the GNU General Public License. See the file COPYING in the main
	8	* directory of this archive for more details.
	9	*
	10	* IIO driver for ADS1015 ADC 7-bit I2C slave address:
	11	* * 0x48 - ADDR connected to Ground
	12	* * 0x49 - ADDR connected to Vdd
	13	* * 0x4A - ADDR connected to SDA
	14	* * 0x4B - ADDR connected to SCL
	15	*/
	16
	17	#include <linux/module.h>
c172d22d	18	#include <linux/of_device.h>
ecc24e72 DB	19	#include <linux/init.h>
	20	#include <linux/i2c.h>
	21	#include <linux/regmap.h>
	22	#include <linux/pm_runtime.h>
	23	#include <linux/mutex.h>
	24	#include <linux/delay.h>
	25
9010624c	26	#include <linux/platform_data/ads1015.h>
ecc24e72 DB	27
	28	#include <linux/iio/iio.h>
	29	#include <linux/iio/types.h>
	30	#include <linux/iio/sysfs.h>
	31	#include <linux/iio/buffer.h>
	32	#include <linux/iio/triggered_buffer.h>
	33	#include <linux/iio/trigger_consumer.h>
	34
	35	#define ADS1015_DRV_NAME "ads1015"
	36
	37	#define ADS1015_CONV_REG 0x00
	38	#define ADS1015_CFG_REG 0x01
	39
	40	#define ADS1015_CFG_DR_SHIFT 5
	41	#define ADS1015_CFG_MOD_SHIFT 8
	42	#define ADS1015_CFG_PGA_SHIFT 9
	43	#define ADS1015_CFG_MUX_SHIFT 12
	44
	45	#define ADS1015_CFG_DR_MASK GENMASK(7, 5)
	46	#define ADS1015_CFG_MOD_MASK BIT(8)
	47	#define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
	48	#define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
	49
	50	/* device operating modes */
	51	#define ADS1015_CONTINUOUS 0
	52	#define ADS1015_SINGLESHOT 1
	53
	54	#define ADS1015_SLEEP_DELAY_MS 2000
	55	#define ADS1015_DEFAULT_PGA 2
	56	#define ADS1015_DEFAULT_DATA_RATE 4
	57	#define ADS1015_DEFAULT_CHAN 0
	58
c172d22d	59	enum chip_ids {
ba35f111 MR	60	ADS1015,
	61	ADS1115,
	62	};
	63
ecc24e72 DB	64	enum ads1015_channels {
	65	ADS1015_AIN0_AIN1 = 0,
	66	ADS1015_AIN0_AIN3,
	67	ADS1015_AIN1_AIN3,
	68	ADS1015_AIN2_AIN3,
	69	ADS1015_AIN0,
	70	ADS1015_AIN1,
	71	ADS1015_AIN2,
	72	ADS1015_AIN3,
	73	ADS1015_TIMESTAMP,
	74	};
	75
	76	static const unsigned int ads1015_data_rate[] = {
	77	128, 250, 490, 920, 1600, 2400, 3300, 3300
	78	};
	79
ba35f111 MR	80	static const unsigned int ads1115_data_rate[] = {
	81	8, 16, 32, 64, 128, 250, 475, 860
	82	};
	83
e99c6901 AM	84	/*
	85	* Translation from PGA bits to full-scale positive and negative input voltage
	86	* range in mV
	87	*/
	88	static int ads1015_fullscale_range[] = {
	89	6144, 4096, 2048, 1024, 512, 256, 256, 256
ecc24e72 DB	90	};
	91
	92	#define ADS1015_V_CHAN(_chan, _addr) { \
	93	.type = IIO_VOLTAGE, \
	94	.indexed = 1, \
	95	.address = _addr, \
	96	.channel = _chan, \
	97	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	98	BIT(IIO_CHAN_INFO_SCALE) \| \
	99	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	100	.scan_index = _addr, \
	101	.scan_type = { \
	102	.sign = 's', \
	103	.realbits = 12, \
	104	.storagebits = 16, \
	105	.shift = 4, \
	106	.endianness = IIO_CPU, \
	107	}, \
8ac8aa61	108	.datasheet_name = "AIN"#_chan, \
ecc24e72 DB	109	}
	110
	111	#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
	112	.type = IIO_VOLTAGE, \
	113	.differential = 1, \
	114	.indexed = 1, \
	115	.address = _addr, \
	116	.channel = _chan, \
	117	.channel2 = _chan2, \
	118	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	119	BIT(IIO_CHAN_INFO_SCALE) \| \
	120	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	121	.scan_index = _addr, \
	122	.scan_type = { \
	123	.sign = 's', \
	124	.realbits = 12, \
	125	.storagebits = 16, \
	126	.shift = 4, \
	127	.endianness = IIO_CPU, \
	128	}, \
8ac8aa61	129	.datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
ecc24e72 DB	130	}
ecc24e72 DB	131
ba35f111 MR	132	#define ADS1115_V_CHAN(_chan, _addr) { \
	133	.type = IIO_VOLTAGE, \
	134	.indexed = 1, \
	135	.address = _addr, \
	136	.channel = _chan, \
	137	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	138	BIT(IIO_CHAN_INFO_SCALE) \| \
	139	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	140	.scan_index = _addr, \
	141	.scan_type = { \
	142	.sign = 's', \
	143	.realbits = 16, \
	144	.storagebits = 16, \
	145	.endianness = IIO_CPU, \
	146	}, \
8ac8aa61	147	.datasheet_name = "AIN"#_chan, \
ba35f111 MR	148	}
	149
	150	#define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
	151	.type = IIO_VOLTAGE, \
	152	.differential = 1, \
	153	.indexed = 1, \
	154	.address = _addr, \
	155	.channel = _chan, \
	156	.channel2 = _chan2, \
	157	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	158	BIT(IIO_CHAN_INFO_SCALE) \| \
	159	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	160	.scan_index = _addr, \
	161	.scan_type = { \
	162	.sign = 's', \
	163	.realbits = 16, \
	164	.storagebits = 16, \
	165	.endianness = IIO_CPU, \
	166	}, \
8ac8aa61	167	.datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
ba35f111 MR	168	}
ba35f111 MR	169
ecc24e72 DB	170	struct ads1015_data {
	171	struct regmap *regmap;
	172	/*
	173	* Protects ADC ops, e.g: concurrent sysfs/buffered
	174	* data reads, configuration updates
	175	*/
	176	struct mutex lock;
	177	struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
ba35f111 MR	178
ba35f111 MR	179	unsigned int *data_rate;
ecc24e72 DB	180	};
	181
	182	static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
	183	{
	184	return (reg == ADS1015_CFG_REG);
	185	}
	186
	187	static const struct regmap_config ads1015_regmap_config = {
	188	.reg_bits = 8,
	189	.val_bits = 16,
	190	.max_register = ADS1015_CFG_REG,
	191	.writeable_reg = ads1015_is_writeable_reg,
	192	};
	193
	194	static const struct iio_chan_spec ads1015_channels[] = {
	195	ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
	196	ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
	197	ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
	198	ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
	199	ADS1015_V_CHAN(0, ADS1015_AIN0),
	200	ADS1015_V_CHAN(1, ADS1015_AIN1),
	201	ADS1015_V_CHAN(2, ADS1015_AIN2),
	202	ADS1015_V_CHAN(3, ADS1015_AIN3),
	203	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
	204	};
	205
ba35f111 MR	206	static const struct iio_chan_spec ads1115_channels[] = {
	207	ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
	208	ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
	209	ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
	210	ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
	211	ADS1115_V_CHAN(0, ADS1015_AIN0),
	212	ADS1115_V_CHAN(1, ADS1015_AIN1),
	213	ADS1115_V_CHAN(2, ADS1015_AIN2),
	214	ADS1115_V_CHAN(3, ADS1015_AIN3),
	215	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
	216	};
	217
ecc24e72 DB	218	static int ads1015_set_power_state(struct ads1015_data *data, bool on)
	219	{
	220	int ret;
	221	struct device *dev = regmap_get_device(data->regmap);
	222
	223	if (on) {
	224	ret = pm_runtime_get_sync(dev);
	225	if (ret < 0)
	226	pm_runtime_put_noidle(dev);
	227	} else {
	228	pm_runtime_mark_last_busy(dev);
	229	ret = pm_runtime_put_autosuspend(dev);
	230	}
	231
	232	return ret;
	233	}
	234
	235	static
	236	int ads1015_get_adc_result(struct ads1015_data data, int chan, int val)
	237	{
	238	int ret, pga, dr, conv_time;
	239	bool change;
	240
	241	if (chan < 0 \|\| chan >= ADS1015_CHANNELS)
	242	return -EINVAL;
	243
	244	pga = data->channel_data[chan].pga;
	245	dr = data->channel_data[chan].data_rate;
	246
	247	ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
	248	ADS1015_CFG_MUX_MASK \|
a8da3223 AM	249	ADS1015_CFG_PGA_MASK \|
a8da3223 AM	250	ADS1015_CFG_DR_MASK,
ecc24e72	251	chan << ADS1015_CFG_MUX_SHIFT \|
a8da3223 AM	252	pga << ADS1015_CFG_PGA_SHIFT \|
a8da3223 AM	253	dr << ADS1015_CFG_DR_SHIFT,
ecc24e72 DB	254	&change);
	255	if (ret < 0)
	256	return ret;
	257
	258	if (change) {
ba35f111	259	conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
ecc24e72 DB	260	usleep_range(conv_time, conv_time + 1);
	261	}
	262
	263	return regmap_read(data->regmap, ADS1015_CONV_REG, val);
	264	}
	265
	266	static irqreturn_t ads1015_trigger_handler(int irq, void *p)
	267	{
	268	struct iio_poll_func *pf = p;
	269	struct iio_dev *indio_dev = pf->indio_dev;
	270	struct ads1015_data *data = iio_priv(indio_dev);
	271	s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
	272	int chan, ret, res;
	273
	274	memset(buf, 0, sizeof(buf));
	275
	276	mutex_lock(&data->lock);
	277	chan = find_first_bit(indio_dev->active_scan_mask,
	278	indio_dev->masklength);
	279	ret = ads1015_get_adc_result(data, chan, &res);
	280	if (ret < 0) {
	281	mutex_unlock(&data->lock);
	282	goto err;
	283	}
	284
	285	buf[0] = res;
	286	mutex_unlock(&data->lock);
	287
bc2b7dab GB	288	iio_push_to_buffers_with_timestamp(indio_dev, buf,
bc2b7dab GB	289	iio_get_time_ns(indio_dev));
ecc24e72 DB	290
	291	err:
	292	iio_trigger_notify_done(indio_dev->trig);
	293
	294	return IRQ_HANDLED;
	295	}
	296
e99c6901 AM	297	static int ads1015_set_scale(struct ads1015_data *data,
e99c6901 AM	298	struct iio_chan_spec const *chan,
ecc24e72 DB	299	int scale, int uscale)
	300	{
	301	int i, ret, rindex = -1;
e99c6901 AM	302	int fullscale = div_s64((scale * 1000000LL + uscale) <<
e99c6901 AM	303	(chan->scan_type.realbits - 1), 1000000);
ecc24e72	304
e99c6901 AM	305	for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
e99c6901 AM	306	if (ads1015_fullscale_range[i] == fullscale) {
ecc24e72 DB	307	rindex = i;
	308	break;
	309	}
e99c6901	310	}
ecc24e72 DB	311	if (rindex < 0)
	312	return -EINVAL;
	313
	314	ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
	315	ADS1015_CFG_PGA_MASK,
	316	rindex << ADS1015_CFG_PGA_SHIFT);
	317	if (ret < 0)
	318	return ret;
	319
e99c6901	320	data->channel_data[chan->address].pga = rindex;
ecc24e72 DB	321
	322	return 0;
	323	}
	324
	325	static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
	326	{
a8da3223	327	int i;
ecc24e72	328
a8da3223	329	for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
ba35f111	330	if (data->data_rate[i] == rate) {
a8da3223 AM	331	data->channel_data[chan].data_rate = i;
a8da3223 AM	332	return 0;
ecc24e72	333	}
a8da3223	334	}
ecc24e72	335
a8da3223	336	return -EINVAL;
ecc24e72 DB	337	}
	338
	339	static int ads1015_read_raw(struct iio_dev *indio_dev,
	340	struct iio_chan_spec const chan, int val,
	341	int *val2, long mask)
	342	{
	343	int ret, idx;
	344	struct ads1015_data *data = iio_priv(indio_dev);
	345
	346	mutex_lock(&indio_dev->mlock);
	347	mutex_lock(&data->lock);
	348	switch (mask) {
ba35f111 MR	349	case IIO_CHAN_INFO_RAW: {
	350	int shift = chan->scan_type.shift;
	351
ecc24e72 DB	352	if (iio_buffer_enabled(indio_dev)) {
	353	ret = -EBUSY;
	354	break;
	355	}
	356
	357	ret = ads1015_set_power_state(data, true);
	358	if (ret < 0)
	359	break;
	360
	361	ret = ads1015_get_adc_result(data, chan->address, val);
	362	if (ret < 0) {
	363	ads1015_set_power_state(data, false);
	364	break;
	365	}
	366
ba35f111	367	val = sign_extend32(val >> shift, 15 - shift);
ecc24e72 DB	368
	369	ret = ads1015_set_power_state(data, false);
	370	if (ret < 0)
	371	break;
	372
	373	ret = IIO_VAL_INT;
	374	break;
ba35f111	375	}
ecc24e72 DB	376	case IIO_CHAN_INFO_SCALE:
ecc24e72 DB	377	idx = data->channel_data[chan->address].pga;
e99c6901 AM	378	*val = ads1015_fullscale_range[idx];
	379	*val2 = chan->scan_type.realbits - 1;
	380	ret = IIO_VAL_FRACTIONAL_LOG2;
ecc24e72 DB	381	break;
	382	case IIO_CHAN_INFO_SAMP_FREQ:
	383	idx = data->channel_data[chan->address].data_rate;
ba35f111	384	*val = data->data_rate[idx];
ecc24e72 DB	385	ret = IIO_VAL_INT;
	386	break;
	387	default:
	388	ret = -EINVAL;
	389	break;
	390	}
	391	mutex_unlock(&data->lock);
	392	mutex_unlock(&indio_dev->mlock);
	393
	394	return ret;
	395	}
	396
	397	static int ads1015_write_raw(struct iio_dev *indio_dev,
	398	struct iio_chan_spec const *chan, int val,
	399	int val2, long mask)
	400	{
	401	struct ads1015_data *data = iio_priv(indio_dev);
	402	int ret;
	403
	404	mutex_lock(&data->lock);
	405	switch (mask) {
	406	case IIO_CHAN_INFO_SCALE:
e99c6901	407	ret = ads1015_set_scale(data, chan, val, val2);
ecc24e72 DB	408	break;
	409	case IIO_CHAN_INFO_SAMP_FREQ:
	410	ret = ads1015_set_data_rate(data, chan->address, val);
	411	break;
	412	default:
	413	ret = -EINVAL;
	414	break;
	415	}
	416	mutex_unlock(&data->lock);
	417
	418	return ret;
	419	}
	420
	421	static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
	422	{
	423	return ads1015_set_power_state(iio_priv(indio_dev), true);
	424	}
	425
	426	static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
	427	{
	428	return ads1015_set_power_state(iio_priv(indio_dev), false);
	429	}
	430
	431	static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
	432	.preenable = ads1015_buffer_preenable,
	433	.postenable = iio_triggered_buffer_postenable,
	434	.predisable = iio_triggered_buffer_predisable,
	435	.postdisable = ads1015_buffer_postdisable,
	436	.validate_scan_mask = &iio_validate_scan_mask_onehot,
	437	};
	438
e99c6901 AM	439	static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
	440	"3 2 1 0.5 0.25 0.125");
	441	static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
	442	"0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
ba35f111 MR	443
	444	static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
	445	sampling_frequency_available, "128 250 490 920 1600 2400 3300");
	446	static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
	447	sampling_frequency_available, "8 16 32 64 128 250 475 860");
ecc24e72 DB	448
ecc24e72 DB	449	static struct attribute *ads1015_attributes[] = {
e99c6901	450	&iio_const_attr_ads1015_scale_available.dev_attr.attr,
ba35f111	451	&iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
ecc24e72 DB	452	NULL,
	453	};
	454
	455	static const struct attribute_group ads1015_attribute_group = {
	456	.attrs = ads1015_attributes,
	457	};
	458
ba35f111	459	static struct attribute *ads1115_attributes[] = {
e99c6901	460	&iio_const_attr_ads1115_scale_available.dev_attr.attr,
ba35f111 MR	461	&iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
	462	NULL,
	463	};
	464
	465	static const struct attribute_group ads1115_attribute_group = {
	466	.attrs = ads1115_attributes,
	467	};
	468
99a22f06	469	static const struct iio_info ads1015_info = {
ba35f111 MR	470	.driver_module = THIS_MODULE,
	471	.read_raw = ads1015_read_raw,
	472	.write_raw = ads1015_write_raw,
	473	.attrs = &ads1015_attribute_group,
	474	};
	475
99a22f06	476	static const struct iio_info ads1115_info = {
ecc24e72 DB	477	.driver_module = THIS_MODULE,
	478	.read_raw = ads1015_read_raw,
	479	.write_raw = ads1015_write_raw,
ba35f111	480	.attrs = &ads1115_attribute_group,
ecc24e72 DB	481	};
	482
	483	#ifdef CONFIG_OF
	484	static int ads1015_get_channels_config_of(struct i2c_client *client)
	485	{
522caebb GDM	486	struct iio_dev *indio_dev = i2c_get_clientdata(client);
522caebb GDM	487	struct ads1015_data *data = iio_priv(indio_dev);
ecc24e72 DB	488	struct device_node *node;
	489
	490	if (!client->dev.of_node \|\|
	491	!of_get_next_child(client->dev.of_node, NULL))
	492	return -EINVAL;
	493
	494	for_each_child_of_node(client->dev.of_node, node) {
	495	u32 pval;
	496	unsigned int channel;
	497	unsigned int pga = ADS1015_DEFAULT_PGA;
	498	unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
	499
	500	if (of_property_read_u32(node, "reg", &pval)) {
	501	dev_err(&client->dev, "invalid reg on %s\n",
	502	node->full_name);
	503	continue;
	504	}
	505
	506	channel = pval;
	507	if (channel >= ADS1015_CHANNELS) {
	508	dev_err(&client->dev,
	509	"invalid channel index %d on %s\n",
	510	channel, node->full_name);
	511	continue;
	512	}
	513
	514	if (!of_property_read_u32(node, "ti,gain", &pval)) {
	515	pga = pval;
	516	if (pga > 6) {
	517	dev_err(&client->dev, "invalid gain on %s\n",
	518	node->full_name);
943bbe74	519	of_node_put(node);
ecc24e72 DB	520	return -EINVAL;
	521	}
	522	}
	523
	524	if (!of_property_read_u32(node, "ti,datarate", &pval)) {
	525	data_rate = pval;
	526	if (data_rate > 7) {
	527	dev_err(&client->dev,
	528	"invalid data_rate on %s\n",
	529	node->full_name);
943bbe74	530	of_node_put(node);
ecc24e72 DB	531	return -EINVAL;
	532	}
	533	}
	534
	535	data->channel_data[channel].pga = pga;
	536	data->channel_data[channel].data_rate = data_rate;
	537	}
	538
	539	return 0;
	540	}
	541	#endif
	542
	543	static void ads1015_get_channels_config(struct i2c_client *client)
	544	{
	545	unsigned int k;
	546
	547	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	548	struct ads1015_data *data = iio_priv(indio_dev);
	549	struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
	550
	551	/* prefer platform data */
	552	if (pdata) {
	553	memcpy(data->channel_data, pdata->channel_data,
	554	sizeof(data->channel_data));
	555	return;
	556	}
	557
	558	#ifdef CONFIG_OF
	559	if (!ads1015_get_channels_config_of(client))
	560	return;
	561	#endif
	562	/* fallback on default configuration */
	563	for (k = 0; k < ADS1015_CHANNELS; ++k) {
	564	data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
	565	data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
	566	}
	567	}
	568
	569	static int ads1015_probe(struct i2c_client *client,
	570	const struct i2c_device_id *id)
	571	{
	572	struct iio_dev *indio_dev;
	573	struct ads1015_data *data;
	574	int ret;
c172d22d	575	enum chip_ids chip;
ecc24e72 DB	576
	577	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
	578	if (!indio_dev)
	579	return -ENOMEM;
	580
	581	data = iio_priv(indio_dev);
	582	i2c_set_clientdata(client, indio_dev);
	583
	584	mutex_init(&data->lock);
	585
	586	indio_dev->dev.parent = &client->dev;
f5241dbd	587	indio_dev->dev.of_node = client->dev.of_node;
ecc24e72	588	indio_dev->name = ADS1015_DRV_NAME;
ecc24e72 DB	589	indio_dev->modes = INDIO_DIRECT_MODE;
ecc24e72 DB	590
c172d22d JMC	591	if (client->dev.of_node)
	592	chip = (enum chip_ids)of_device_get_match_data(&client->dev);
	593	else
	594	chip = id->driver_data;
	595	switch (chip) {
ba35f111 MR	596	case ADS1015:
	597	indio_dev->channels = ads1015_channels;
	598	indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
	599	indio_dev->info = &ads1015_info;
	600	data->data_rate = (unsigned int *) &ads1015_data_rate;
	601	break;
	602	case ADS1115:
	603	indio_dev->channels = ads1115_channels;
	604	indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
	605	indio_dev->info = &ads1115_info;
	606	data->data_rate = (unsigned int *) &ads1115_data_rate;
	607	break;
	608	}
	609
ecc24e72 DB	610	/* we need to keep this ABI the same as used by hwmon ADS1015 driver */
	611	ads1015_get_channels_config(client);
	612
	613	data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
	614	if (IS_ERR(data->regmap)) {
	615	dev_err(&client->dev, "Failed to allocate register map\n");
	616	return PTR_ERR(data->regmap);
	617	}
	618
	619	ret = iio_triggered_buffer_setup(indio_dev, NULL,
	620	ads1015_trigger_handler,
	621	&ads1015_buffer_setup_ops);
	622	if (ret < 0) {
	623	dev_err(&client->dev, "iio triggered buffer setup failed\n");
	624	return ret;
	625	}
	626	ret = pm_runtime_set_active(&client->dev);
	627	if (ret)
	628	goto err_buffer_cleanup;
	629	pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
	630	pm_runtime_use_autosuspend(&client->dev);
	631	pm_runtime_enable(&client->dev);
	632
	633	ret = iio_device_register(indio_dev);
	634	if (ret < 0) {
	635	dev_err(&client->dev, "Failed to register IIO device\n");
	636	goto err_buffer_cleanup;
	637	}
	638
	639	return 0;
	640
	641	err_buffer_cleanup:
	642	iio_triggered_buffer_cleanup(indio_dev);
	643
	644	return ret;
	645	}
	646
	647	static int ads1015_remove(struct i2c_client *client)
	648	{
	649	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	650	struct ads1015_data *data = iio_priv(indio_dev);
	651
	652	iio_device_unregister(indio_dev);
	653
	654	pm_runtime_disable(&client->dev);
	655	pm_runtime_set_suspended(&client->dev);
	656	pm_runtime_put_noidle(&client->dev);
	657
	658	iio_triggered_buffer_cleanup(indio_dev);
	659
	660	/* power down single shot mode */
	661	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
	662	ADS1015_CFG_MOD_MASK,
	663	ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
	664	}
	665
	666	#ifdef CONFIG_PM
	667	static int ads1015_runtime_suspend(struct device *dev)
	668	{
	669	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
	670	struct ads1015_data *data = iio_priv(indio_dev);
	671
	672	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
	673	ADS1015_CFG_MOD_MASK,
674	ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
675	}
676
677	static int ads1015_runtime_resume(struct device *dev)
678	{
679	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
680	struct ads1015_data *data = iio_priv(indio_dev);
681
682	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
683	ADS1015_CFG_MOD_MASK,
684	ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
685	}
686	#endif
687
688	static const struct dev_pm_ops ads1015_pm_ops = {
689	SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
690	ads1015_runtime_resume, NULL)
691	};
692
693	static const struct i2c_device_id ads1015_id[] = {
ba35f111 MR	694	{"ads1015", ADS1015},
ba35f111 MR	695	{"ads1115", ADS1115},
ecc24e72 DB	696	{}
	697	};
	698	MODULE_DEVICE_TABLE(i2c, ads1015_id);
	699
c172d22d JMC	700	static const struct of_device_id ads1015_of_match[] = {
	701	{
	702	.compatible = "ti,ads1015",
	703	.data = (void *)ADS1015
	704	},
	705	{
	706	.compatible = "ti,ads1115",
	707	.data = (void *)ADS1115
	708	},
	709	{}
	710	};
	711	MODULE_DEVICE_TABLE(of, ads1015_of_match);
	712
ecc24e72 DB	713	static struct i2c_driver ads1015_driver = {
	714	.driver = {
	715	.name = ADS1015_DRV_NAME,
c172d22d	716	.of_match_table = ads1015_of_match,
ecc24e72 DB	717	.pm = &ads1015_pm_ops,
	718	},
	719	.probe = ads1015_probe,
	720	.remove = ads1015_remove,
	721	.id_table = ads1015_id,
	722	};
	723
	724	module_i2c_driver(ads1015_driver);
	725
	726	MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
	727	MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
	728	MODULE_LICENSE("GPL v2");