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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
3e87e783 SN |
2 | /* |
3 | * Copyright (C) 2015 Prevas A/S | |
3e87e783 SN |
4 | */ |
5 | ||
6 | #include <linux/device.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/slab.h> | |
9 | #include <linux/sysfs.h> | |
10 | #include <linux/spi/spi.h> | |
11 | #include <linux/regulator/consumer.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/of.h> | |
15 | ||
16 | #include <linux/iio/iio.h> | |
2a864877 SN |
17 | #include <linux/iio/buffer.h> |
18 | #include <linux/iio/trigger_consumer.h> | |
19 | #include <linux/iio/triggered_buffer.h> | |
3e87e783 SN |
20 | #include <linux/iio/sysfs.h> |
21 | ||
22 | #define ADS8688_CMD_REG(x) (x << 8) | |
23 | #define ADS8688_CMD_REG_NOOP 0x00 | |
24 | #define ADS8688_CMD_REG_RST 0x85 | |
25 | #define ADS8688_CMD_REG_MAN_CH(chan) (0xC0 | (4 * chan)) | |
26 | #define ADS8688_CMD_DONT_CARE_BITS 16 | |
27 | ||
28 | #define ADS8688_PROG_REG(x) (x << 9) | |
29 | #define ADS8688_PROG_REG_RANGE_CH(chan) (0x05 + chan) | |
30 | #define ADS8688_PROG_WR_BIT BIT(8) | |
31 | #define ADS8688_PROG_DONT_CARE_BITS 8 | |
32 | ||
33 | #define ADS8688_REG_PLUSMINUS25VREF 0 | |
34 | #define ADS8688_REG_PLUSMINUS125VREF 1 | |
35 | #define ADS8688_REG_PLUSMINUS0625VREF 2 | |
36 | #define ADS8688_REG_PLUS25VREF 5 | |
37 | #define ADS8688_REG_PLUS125VREF 6 | |
38 | ||
39 | #define ADS8688_VREF_MV 4096 | |
40 | #define ADS8688_REALBITS 16 | |
f214ff52 | 41 | #define ADS8688_MAX_CHANNELS 8 |
3e87e783 SN |
42 | |
43 | /* | |
44 | * enum ads8688_range - ADS8688 reference voltage range | |
45 | * @ADS8688_PLUSMINUS25VREF: Device is configured for input range ±2.5 * VREF | |
46 | * @ADS8688_PLUSMINUS125VREF: Device is configured for input range ±1.25 * VREF | |
47 | * @ADS8688_PLUSMINUS0625VREF: Device is configured for input range ±0.625 * VREF | |
48 | * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF | |
49 | * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF | |
50 | */ | |
51 | enum ads8688_range { | |
52 | ADS8688_PLUSMINUS25VREF, | |
53 | ADS8688_PLUSMINUS125VREF, | |
54 | ADS8688_PLUSMINUS0625VREF, | |
55 | ADS8688_PLUS25VREF, | |
56 | ADS8688_PLUS125VREF, | |
57 | }; | |
58 | ||
59 | struct ads8688_chip_info { | |
60 | const struct iio_chan_spec *channels; | |
61 | unsigned int num_channels; | |
62 | }; | |
63 | ||
64 | struct ads8688_state { | |
65 | struct mutex lock; | |
66 | const struct ads8688_chip_info *chip_info; | |
67 | struct spi_device *spi; | |
68 | struct regulator *reg; | |
69 | unsigned int vref_mv; | |
70 | enum ads8688_range range[8]; | |
71 | union { | |
72 | __be32 d32; | |
73 | u8 d8[4]; | |
74 | } data[2] ____cacheline_aligned; | |
75 | }; | |
76 | ||
77 | enum ads8688_id { | |
78 | ID_ADS8684, | |
79 | ID_ADS8688, | |
80 | }; | |
81 | ||
82 | struct ads8688_ranges { | |
83 | enum ads8688_range range; | |
84 | unsigned int scale; | |
85 | int offset; | |
86 | u8 reg; | |
87 | }; | |
88 | ||
89 | static const struct ads8688_ranges ads8688_range_def[5] = { | |
90 | { | |
91 | .range = ADS8688_PLUSMINUS25VREF, | |
92 | .scale = 76295, | |
93 | .offset = -(1 << (ADS8688_REALBITS - 1)), | |
94 | .reg = ADS8688_REG_PLUSMINUS25VREF, | |
95 | }, { | |
96 | .range = ADS8688_PLUSMINUS125VREF, | |
97 | .scale = 38148, | |
98 | .offset = -(1 << (ADS8688_REALBITS - 1)), | |
99 | .reg = ADS8688_REG_PLUSMINUS125VREF, | |
100 | }, { | |
101 | .range = ADS8688_PLUSMINUS0625VREF, | |
102 | .scale = 19074, | |
103 | .offset = -(1 << (ADS8688_REALBITS - 1)), | |
104 | .reg = ADS8688_REG_PLUSMINUS0625VREF, | |
105 | }, { | |
106 | .range = ADS8688_PLUS25VREF, | |
107 | .scale = 38148, | |
108 | .offset = 0, | |
109 | .reg = ADS8688_REG_PLUS25VREF, | |
110 | }, { | |
111 | .range = ADS8688_PLUS125VREF, | |
112 | .scale = 19074, | |
113 | .offset = 0, | |
114 | .reg = ADS8688_REG_PLUS125VREF, | |
115 | } | |
116 | }; | |
117 | ||
118 | static ssize_t ads8688_show_scales(struct device *dev, | |
119 | struct device_attribute *attr, char *buf) | |
120 | { | |
121 | struct ads8688_state *st = iio_priv(dev_to_iio_dev(dev)); | |
122 | ||
123 | return sprintf(buf, "0.%09u 0.%09u 0.%09u\n", | |
124 | ads8688_range_def[0].scale * st->vref_mv, | |
125 | ads8688_range_def[1].scale * st->vref_mv, | |
126 | ads8688_range_def[2].scale * st->vref_mv); | |
127 | } | |
128 | ||
129 | static ssize_t ads8688_show_offsets(struct device *dev, | |
130 | struct device_attribute *attr, char *buf) | |
131 | { | |
132 | return sprintf(buf, "%d %d\n", ads8688_range_def[0].offset, | |
133 | ads8688_range_def[3].offset); | |
134 | } | |
135 | ||
136 | static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, | |
137 | ads8688_show_scales, NULL, 0); | |
138 | static IIO_DEVICE_ATTR(in_voltage_offset_available, S_IRUGO, | |
139 | ads8688_show_offsets, NULL, 0); | |
140 | ||
141 | static struct attribute *ads8688_attributes[] = { | |
142 | &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, | |
143 | &iio_dev_attr_in_voltage_offset_available.dev_attr.attr, | |
144 | NULL, | |
145 | }; | |
146 | ||
147 | static const struct attribute_group ads8688_attribute_group = { | |
148 | .attrs = ads8688_attributes, | |
149 | }; | |
150 | ||
151 | #define ADS8688_CHAN(index) \ | |
152 | { \ | |
153 | .type = IIO_VOLTAGE, \ | |
154 | .indexed = 1, \ | |
155 | .channel = index, \ | |
156 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ | |
157 | | BIT(IIO_CHAN_INFO_SCALE) \ | |
158 | | BIT(IIO_CHAN_INFO_OFFSET), \ | |
2a864877 SN |
159 | .scan_index = index, \ |
160 | .scan_type = { \ | |
161 | .sign = 'u', \ | |
162 | .realbits = 16, \ | |
163 | .storagebits = 16, \ | |
164 | .endianness = IIO_BE, \ | |
165 | }, \ | |
3e87e783 SN |
166 | } |
167 | ||
168 | static const struct iio_chan_spec ads8684_channels[] = { | |
169 | ADS8688_CHAN(0), | |
170 | ADS8688_CHAN(1), | |
171 | ADS8688_CHAN(2), | |
172 | ADS8688_CHAN(3), | |
173 | }; | |
174 | ||
175 | static const struct iio_chan_spec ads8688_channels[] = { | |
176 | ADS8688_CHAN(0), | |
177 | ADS8688_CHAN(1), | |
178 | ADS8688_CHAN(2), | |
179 | ADS8688_CHAN(3), | |
180 | ADS8688_CHAN(4), | |
181 | ADS8688_CHAN(5), | |
182 | ADS8688_CHAN(6), | |
183 | ADS8688_CHAN(7), | |
184 | }; | |
185 | ||
186 | static int ads8688_prog_write(struct iio_dev *indio_dev, unsigned int addr, | |
187 | unsigned int val) | |
188 | { | |
189 | struct ads8688_state *st = iio_priv(indio_dev); | |
190 | u32 tmp; | |
191 | ||
192 | tmp = ADS8688_PROG_REG(addr) | ADS8688_PROG_WR_BIT | val; | |
193 | tmp <<= ADS8688_PROG_DONT_CARE_BITS; | |
194 | st->data[0].d32 = cpu_to_be32(tmp); | |
195 | ||
196 | return spi_write(st->spi, &st->data[0].d8[1], 3); | |
197 | } | |
198 | ||
199 | static int ads8688_reset(struct iio_dev *indio_dev) | |
200 | { | |
201 | struct ads8688_state *st = iio_priv(indio_dev); | |
202 | u32 tmp; | |
203 | ||
204 | tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_RST); | |
205 | tmp <<= ADS8688_CMD_DONT_CARE_BITS; | |
206 | st->data[0].d32 = cpu_to_be32(tmp); | |
207 | ||
208 | return spi_write(st->spi, &st->data[0].d8[0], 4); | |
209 | } | |
210 | ||
211 | static int ads8688_read(struct iio_dev *indio_dev, unsigned int chan) | |
212 | { | |
213 | struct ads8688_state *st = iio_priv(indio_dev); | |
214 | int ret; | |
215 | u32 tmp; | |
216 | struct spi_transfer t[] = { | |
217 | { | |
218 | .tx_buf = &st->data[0].d8[0], | |
219 | .len = 4, | |
220 | .cs_change = 1, | |
221 | }, { | |
222 | .tx_buf = &st->data[1].d8[0], | |
223 | .rx_buf = &st->data[1].d8[0], | |
224 | .len = 4, | |
225 | }, | |
226 | }; | |
227 | ||
228 | tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_MAN_CH(chan)); | |
229 | tmp <<= ADS8688_CMD_DONT_CARE_BITS; | |
230 | st->data[0].d32 = cpu_to_be32(tmp); | |
231 | ||
232 | tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_NOOP); | |
233 | tmp <<= ADS8688_CMD_DONT_CARE_BITS; | |
234 | st->data[1].d32 = cpu_to_be32(tmp); | |
235 | ||
236 | ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); | |
237 | if (ret < 0) | |
238 | return ret; | |
239 | ||
240 | return be32_to_cpu(st->data[1].d32) & 0xffff; | |
241 | } | |
242 | ||
243 | static int ads8688_read_raw(struct iio_dev *indio_dev, | |
244 | struct iio_chan_spec const *chan, | |
245 | int *val, int *val2, long m) | |
246 | { | |
247 | int ret, offset; | |
248 | unsigned long scale_mv; | |
249 | ||
250 | struct ads8688_state *st = iio_priv(indio_dev); | |
251 | ||
252 | mutex_lock(&st->lock); | |
253 | switch (m) { | |
254 | case IIO_CHAN_INFO_RAW: | |
255 | ret = ads8688_read(indio_dev, chan->channel); | |
256 | mutex_unlock(&st->lock); | |
257 | if (ret < 0) | |
258 | return ret; | |
259 | *val = ret; | |
260 | return IIO_VAL_INT; | |
261 | case IIO_CHAN_INFO_SCALE: | |
262 | scale_mv = st->vref_mv; | |
263 | scale_mv *= ads8688_range_def[st->range[chan->channel]].scale; | |
264 | *val = 0; | |
265 | *val2 = scale_mv; | |
266 | mutex_unlock(&st->lock); | |
267 | return IIO_VAL_INT_PLUS_NANO; | |
268 | case IIO_CHAN_INFO_OFFSET: | |
269 | offset = ads8688_range_def[st->range[chan->channel]].offset; | |
270 | *val = offset; | |
271 | mutex_unlock(&st->lock); | |
272 | return IIO_VAL_INT; | |
273 | } | |
274 | mutex_unlock(&st->lock); | |
275 | ||
276 | return -EINVAL; | |
277 | } | |
278 | ||
279 | static int ads8688_write_reg_range(struct iio_dev *indio_dev, | |
280 | struct iio_chan_spec const *chan, | |
281 | enum ads8688_range range) | |
282 | { | |
283 | unsigned int tmp; | |
284 | int ret; | |
285 | ||
286 | tmp = ADS8688_PROG_REG_RANGE_CH(chan->channel); | |
287 | ret = ads8688_prog_write(indio_dev, tmp, range); | |
288 | ||
289 | return ret; | |
290 | } | |
291 | ||
292 | static int ads8688_write_raw(struct iio_dev *indio_dev, | |
293 | struct iio_chan_spec const *chan, | |
294 | int val, int val2, long mask) | |
295 | { | |
296 | struct ads8688_state *st = iio_priv(indio_dev); | |
297 | unsigned int scale = 0; | |
298 | int ret = -EINVAL, i, offset = 0; | |
299 | ||
300 | mutex_lock(&st->lock); | |
301 | switch (mask) { | |
302 | case IIO_CHAN_INFO_SCALE: | |
303 | /* If the offset is 0 the ±2.5 * VREF mode is not available */ | |
304 | offset = ads8688_range_def[st->range[chan->channel]].offset; | |
305 | if (offset == 0 && val2 == ads8688_range_def[0].scale * st->vref_mv) { | |
306 | mutex_unlock(&st->lock); | |
307 | return -EINVAL; | |
308 | } | |
309 | ||
310 | /* Lookup new mode */ | |
311 | for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++) | |
312 | if (val2 == ads8688_range_def[i].scale * st->vref_mv && | |
313 | offset == ads8688_range_def[i].offset) { | |
314 | ret = ads8688_write_reg_range(indio_dev, chan, | |
315 | ads8688_range_def[i].reg); | |
316 | break; | |
317 | } | |
318 | break; | |
319 | case IIO_CHAN_INFO_OFFSET: | |
320 | /* | |
321 | * There are only two available offsets: | |
322 | * 0 and -(1 << (ADS8688_REALBITS - 1)) | |
323 | */ | |
324 | if (!(ads8688_range_def[0].offset == val || | |
325 | ads8688_range_def[3].offset == val)) { | |
326 | mutex_unlock(&st->lock); | |
327 | return -EINVAL; | |
328 | } | |
329 | ||
330 | /* | |
331 | * If the device are in ±2.5 * VREF mode, it's not allowed to | |
332 | * switch to a mode where the offset is 0 | |
333 | */ | |
334 | if (val == 0 && | |
335 | st->range[chan->channel] == ADS8688_PLUSMINUS25VREF) { | |
336 | mutex_unlock(&st->lock); | |
337 | return -EINVAL; | |
338 | } | |
339 | ||
340 | scale = ads8688_range_def[st->range[chan->channel]].scale; | |
341 | ||
342 | /* Lookup new mode */ | |
343 | for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++) | |
344 | if (val == ads8688_range_def[i].offset && | |
345 | scale == ads8688_range_def[i].scale) { | |
346 | ret = ads8688_write_reg_range(indio_dev, chan, | |
347 | ads8688_range_def[i].reg); | |
348 | break; | |
349 | } | |
350 | break; | |
351 | } | |
352 | ||
353 | if (!ret) | |
354 | st->range[chan->channel] = ads8688_range_def[i].range; | |
355 | ||
356 | mutex_unlock(&st->lock); | |
357 | ||
358 | return ret; | |
359 | } | |
360 | ||
361 | static int ads8688_write_raw_get_fmt(struct iio_dev *indio_dev, | |
362 | struct iio_chan_spec const *chan, | |
363 | long mask) | |
364 | { | |
365 | switch (mask) { | |
366 | case IIO_CHAN_INFO_SCALE: | |
367 | return IIO_VAL_INT_PLUS_NANO; | |
368 | case IIO_CHAN_INFO_OFFSET: | |
369 | return IIO_VAL_INT; | |
370 | } | |
371 | ||
372 | return -EINVAL; | |
373 | } | |
374 | ||
375 | static const struct iio_info ads8688_info = { | |
376 | .read_raw = &ads8688_read_raw, | |
377 | .write_raw = &ads8688_write_raw, | |
378 | .write_raw_get_fmt = &ads8688_write_raw_get_fmt, | |
379 | .attrs = &ads8688_attribute_group, | |
3e87e783 SN |
380 | }; |
381 | ||
2a864877 SN |
382 | static irqreturn_t ads8688_trigger_handler(int irq, void *p) |
383 | { | |
384 | struct iio_poll_func *pf = p; | |
385 | struct iio_dev *indio_dev = pf->indio_dev; | |
f214ff52 | 386 | u16 buffer[ADS8688_MAX_CHANNELS + sizeof(s64)/sizeof(u16)]; |
2a864877 SN |
387 | int i, j = 0; |
388 | ||
389 | for (i = 0; i < indio_dev->masklength; i++) { | |
390 | if (!test_bit(i, indio_dev->active_scan_mask)) | |
391 | continue; | |
392 | buffer[j] = ads8688_read(indio_dev, i); | |
393 | j++; | |
394 | } | |
395 | ||
396 | iio_push_to_buffers_with_timestamp(indio_dev, buffer, | |
e6d12298 | 397 | iio_get_time_ns(indio_dev)); |
2a864877 SN |
398 | |
399 | iio_trigger_notify_done(indio_dev->trig); | |
400 | ||
401 | return IRQ_HANDLED; | |
402 | } | |
403 | ||
3e87e783 SN |
404 | static const struct ads8688_chip_info ads8688_chip_info_tbl[] = { |
405 | [ID_ADS8684] = { | |
406 | .channels = ads8684_channels, | |
407 | .num_channels = ARRAY_SIZE(ads8684_channels), | |
408 | }, | |
409 | [ID_ADS8688] = { | |
410 | .channels = ads8688_channels, | |
411 | .num_channels = ARRAY_SIZE(ads8688_channels), | |
412 | }, | |
413 | }; | |
414 | ||
415 | static int ads8688_probe(struct spi_device *spi) | |
416 | { | |
417 | struct ads8688_state *st; | |
418 | struct iio_dev *indio_dev; | |
419 | int ret; | |
420 | ||
421 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); | |
422 | if (indio_dev == NULL) | |
423 | return -ENOMEM; | |
424 | ||
425 | st = iio_priv(indio_dev); | |
426 | ||
427 | st->reg = devm_regulator_get_optional(&spi->dev, "vref"); | |
428 | if (!IS_ERR(st->reg)) { | |
429 | ret = regulator_enable(st->reg); | |
430 | if (ret) | |
431 | return ret; | |
432 | ||
433 | ret = regulator_get_voltage(st->reg); | |
434 | if (ret < 0) | |
2a864877 | 435 | goto err_regulator_disable; |
3e87e783 SN |
436 | |
437 | st->vref_mv = ret / 1000; | |
438 | } else { | |
439 | /* Use internal reference */ | |
440 | st->vref_mv = ADS8688_VREF_MV; | |
441 | } | |
442 | ||
443 | st->chip_info = &ads8688_chip_info_tbl[spi_get_device_id(spi)->driver_data]; | |
444 | ||
445 | spi->mode = SPI_MODE_1; | |
446 | ||
447 | spi_set_drvdata(spi, indio_dev); | |
448 | ||
449 | st->spi = spi; | |
450 | ||
451 | indio_dev->name = spi_get_device_id(spi)->name; | |
452 | indio_dev->dev.parent = &spi->dev; | |
b541eaff | 453 | indio_dev->dev.of_node = spi->dev.of_node; |
3e87e783 SN |
454 | indio_dev->modes = INDIO_DIRECT_MODE; |
455 | indio_dev->channels = st->chip_info->channels; | |
456 | indio_dev->num_channels = st->chip_info->num_channels; | |
457 | indio_dev->info = &ads8688_info; | |
458 | ||
459 | ads8688_reset(indio_dev); | |
460 | ||
461 | mutex_init(&st->lock); | |
462 | ||
2a864877 SN |
463 | ret = iio_triggered_buffer_setup(indio_dev, NULL, ads8688_trigger_handler, NULL); |
464 | if (ret < 0) { | |
465 | dev_err(&spi->dev, "iio triggered buffer setup failed\n"); | |
466 | goto err_regulator_disable; | |
467 | } | |
468 | ||
3e87e783 SN |
469 | ret = iio_device_register(indio_dev); |
470 | if (ret) | |
2a864877 | 471 | goto err_buffer_cleanup; |
3e87e783 SN |
472 | |
473 | return 0; | |
474 | ||
2a864877 SN |
475 | err_buffer_cleanup: |
476 | iio_triggered_buffer_cleanup(indio_dev); | |
477 | ||
478 | err_regulator_disable: | |
fbe84bd4 | 479 | if (!IS_ERR(st->reg)) |
3e87e783 SN |
480 | regulator_disable(st->reg); |
481 | ||
482 | return ret; | |
483 | } | |
484 | ||
485 | static int ads8688_remove(struct spi_device *spi) | |
486 | { | |
487 | struct iio_dev *indio_dev = spi_get_drvdata(spi); | |
488 | struct ads8688_state *st = iio_priv(indio_dev); | |
489 | ||
490 | iio_device_unregister(indio_dev); | |
2a864877 | 491 | iio_triggered_buffer_cleanup(indio_dev); |
3e87e783 | 492 | |
fbe84bd4 | 493 | if (!IS_ERR(st->reg)) |
3e87e783 SN |
494 | regulator_disable(st->reg); |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static const struct spi_device_id ads8688_id[] = { | |
500 | {"ads8684", ID_ADS8684}, | |
501 | {"ads8688", ID_ADS8688}, | |
502 | {} | |
503 | }; | |
504 | MODULE_DEVICE_TABLE(spi, ads8688_id); | |
505 | ||
506 | static const struct of_device_id ads8688_of_match[] = { | |
507 | { .compatible = "ti,ads8684" }, | |
508 | { .compatible = "ti,ads8688" }, | |
509 | { } | |
510 | }; | |
511 | MODULE_DEVICE_TABLE(of, ads8688_of_match); | |
512 | ||
513 | static struct spi_driver ads8688_driver = { | |
514 | .driver = { | |
515 | .name = "ads8688", | |
3e87e783 SN |
516 | }, |
517 | .probe = ads8688_probe, | |
518 | .remove = ads8688_remove, | |
519 | .id_table = ads8688_id, | |
520 | }; | |
521 | module_spi_driver(ads8688_driver); | |
522 | ||
bcccd7ab | 523 | MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.dk>"); |
3e87e783 SN |
524 | MODULE_DESCRIPTION("Texas Instruments ADS8688 driver"); |
525 | MODULE_LICENSE("GPL v2"); |