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Commit | Line | Data |
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5e53a69b PR |
1 | /* |
2 | * TI ADC MFD driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
5e53a69b PR |
16 | #include <linux/kernel.h> |
17 | #include <linux/err.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/iio/iio.h> | |
6f39ac4e PR |
24 | #include <linux/of.h> |
25 | #include <linux/of_device.h> | |
c80df483 PA |
26 | #include <linux/iio/machine.h> |
27 | #include <linux/iio/driver.h> | |
5e53a69b PR |
28 | |
29 | #include <linux/mfd/ti_am335x_tscadc.h> | |
ca9a5638 ZL |
30 | #include <linux/iio/buffer.h> |
31 | #include <linux/iio/kfifo_buf.h> | |
5e53a69b | 32 | |
f438b9da M |
33 | #include <linux/dmaengine.h> |
34 | #include <linux/dma-mapping.h> | |
35 | ||
36 | #define DMA_BUFFER_SIZE SZ_2K | |
37 | ||
38 | struct tiadc_dma { | |
39 | struct dma_slave_config conf; | |
40 | struct dma_chan *chan; | |
41 | dma_addr_t addr; | |
42 | dma_cookie_t cookie; | |
43 | u8 *buf; | |
44 | int current_period; | |
45 | int period_size; | |
46 | u8 fifo_thresh; | |
47 | }; | |
48 | ||
5e53a69b PR |
49 | struct tiadc_device { |
50 | struct ti_tscadc_dev *mfd_tscadc; | |
f438b9da | 51 | struct tiadc_dma dma; |
90c43ec6 | 52 | struct mutex fifo1_lock; /* to protect fifo access */ |
5e53a69b | 53 | int channels; |
f438b9da | 54 | int total_ch_enabled; |
18926ede SAS |
55 | u8 channel_line[8]; |
56 | u8 channel_step[8]; | |
ca9a5638 | 57 | int buffer_en_ch_steps; |
ca9a5638 | 58 | u16 data[8]; |
5dc11e81 | 59 | u32 open_delay[8], sample_delay[8], step_avg[8]; |
5e53a69b PR |
60 | }; |
61 | ||
62 | static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) | |
63 | { | |
64 | return readl(adc->mfd_tscadc->tscadc_base + reg); | |
65 | } | |
66 | ||
67 | static void tiadc_writel(struct tiadc_device *adc, unsigned int reg, | |
68 | unsigned int val) | |
69 | { | |
70 | writel(val, adc->mfd_tscadc->tscadc_base + reg); | |
71 | } | |
72 | ||
abeccee4 PR |
73 | static u32 get_adc_step_mask(struct tiadc_device *adc_dev) |
74 | { | |
75 | u32 step_en; | |
76 | ||
77 | step_en = ((1 << adc_dev->channels) - 1); | |
78 | step_en <<= TOTAL_STEPS - adc_dev->channels + 1; | |
79 | return step_en; | |
80 | } | |
81 | ||
7ca6740c SAS |
82 | static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev, |
83 | struct iio_chan_spec const *chan) | |
84 | { | |
85 | int i; | |
86 | ||
87 | for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { | |
88 | if (chan->channel == adc_dev->channel_line[i]) { | |
89 | u32 step; | |
90 | ||
91 | step = adc_dev->channel_step[i]; | |
92 | /* +1 for the charger */ | |
93 | return 1 << (step + 1); | |
94 | } | |
95 | } | |
96 | WARN_ON(1); | |
97 | return 0; | |
98 | } | |
99 | ||
ca9a5638 | 100 | static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan) |
5e53a69b | 101 | { |
ca9a5638 ZL |
102 | return 1 << adc_dev->channel_step[chan]; |
103 | } | |
104 | ||
105 | static void tiadc_step_config(struct iio_dev *indio_dev) | |
106 | { | |
107 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
5dc11e81 | 108 | struct device *dev = adc_dev->mfd_tscadc->dev; |
5e53a69b | 109 | unsigned int stepconfig; |
3a59684c | 110 | int i, steps = 0; |
5e53a69b PR |
111 | |
112 | /* | |
113 | * There are 16 configurable steps and 8 analog input | |
114 | * lines available which are shared between Touchscreen and ADC. | |
115 | * | |
3a59684c | 116 | * Steps forwards i.e. from 0 towards 16 are used by ADC |
5e53a69b PR |
117 | * depending on number of input lines needed. |
118 | * Channel would represent which analog input | |
119 | * needs to be given to ADC to digitalize data. | |
120 | */ | |
121 | ||
5e53a69b | 122 | |
18926ede SAS |
123 | for (i = 0; i < adc_dev->channels; i++) { |
124 | int chan; | |
125 | ||
126 | chan = adc_dev->channel_line[i]; | |
5dc11e81 V |
127 | |
128 | if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { | |
129 | dev_warn(dev, "chan %d step_avg truncating to %d\n", | |
130 | chan, STEPCONFIG_AVG_16); | |
131 | adc_dev->step_avg[i] = STEPCONFIG_AVG_16; | |
132 | } | |
133 | ||
134 | if (adc_dev->step_avg[i]) | |
135 | stepconfig = | |
136 | STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | | |
137 | STEPCONFIG_FIFO1; | |
138 | else | |
139 | stepconfig = STEPCONFIG_FIFO1; | |
140 | ||
141 | if (iio_buffer_enabled(indio_dev)) | |
142 | stepconfig |= STEPCONFIG_MODE_SWCNT; | |
143 | ||
18926ede SAS |
144 | tiadc_writel(adc_dev, REG_STEPCONFIG(steps), |
145 | stepconfig | STEPCONFIG_INP(chan)); | |
5dc11e81 V |
146 | |
147 | if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) { | |
148 | dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n", | |
149 | chan); | |
150 | adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK; | |
151 | } | |
152 | ||
153 | if (adc_dev->sample_delay[i] > 0xFF) { | |
154 | dev_warn(dev, "chan %d sample delay truncating to 0xFF\n", | |
155 | chan); | |
156 | adc_dev->sample_delay[i] = 0xFF; | |
157 | } | |
158 | ||
18926ede | 159 | tiadc_writel(adc_dev, REG_STEPDELAY(steps), |
5dc11e81 V |
160 | STEPDELAY_OPEN(adc_dev->open_delay[i]) | |
161 | STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); | |
162 | ||
18926ede SAS |
163 | adc_dev->channel_step[i] = steps; |
164 | steps++; | |
5e53a69b | 165 | } |
ca9a5638 ZL |
166 | } |
167 | ||
168 | static irqreturn_t tiadc_irq_h(int irq, void *private) | |
169 | { | |
170 | struct iio_dev *indio_dev = private; | |
171 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
e83bb3e6 ME |
172 | unsigned int status, config, adc_fsm; |
173 | unsigned short count = 0; | |
174 | ||
ca9a5638 ZL |
175 | status = tiadc_readl(adc_dev, REG_IRQSTATUS); |
176 | ||
177 | /* | |
178 | * ADC and touchscreen share the IRQ line. | |
179 | * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only | |
180 | */ | |
181 | if (status & IRQENB_FIFO1OVRRUN) { | |
182 | /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */ | |
183 | config = tiadc_readl(adc_dev, REG_CTRL); | |
184 | config &= ~(CNTRLREG_TSCSSENB); | |
185 | tiadc_writel(adc_dev, REG_CTRL, config); | |
186 | tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN | |
187 | | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES); | |
e83bb3e6 ME |
188 | |
189 | /* wait for idle state. | |
190 | * ADC needs to finish the current conversion | |
191 | * before disabling the module | |
192 | */ | |
193 | do { | |
194 | adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM); | |
195 | } while (adc_fsm != 0x10 && count++ < 100); | |
196 | ||
ca9a5638 ZL |
197 | tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB)); |
198 | return IRQ_HANDLED; | |
199 | } else if (status & IRQENB_FIFO1THRES) { | |
200 | /* Disable irq and wake worker thread */ | |
201 | tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES); | |
202 | return IRQ_WAKE_THREAD; | |
203 | } | |
204 | ||
205 | return IRQ_NONE; | |
206 | } | |
207 | ||
208 | static irqreturn_t tiadc_worker_h(int irq, void *private) | |
209 | { | |
210 | struct iio_dev *indio_dev = private; | |
211 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
212 | int i, k, fifo1count, read; | |
213 | u16 *data = adc_dev->data; | |
214 | ||
215 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); | |
216 | for (k = 0; k < fifo1count; k = k + i) { | |
217 | for (i = 0; i < (indio_dev->scan_bytes)/2; i++) { | |
218 | read = tiadc_readl(adc_dev, REG_FIFO1); | |
219 | data[i] = read & FIFOREAD_DATA_MASK; | |
220 | } | |
221 | iio_push_to_buffers(indio_dev, (u8 *) data); | |
222 | } | |
223 | ||
224 | tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES); | |
225 | tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES); | |
226 | ||
227 | return IRQ_HANDLED; | |
228 | } | |
229 | ||
f438b9da M |
230 | static void tiadc_dma_rx_complete(void *param) |
231 | { | |
232 | struct iio_dev *indio_dev = param; | |
233 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
234 | struct tiadc_dma *dma = &adc_dev->dma; | |
235 | u8 *data; | |
236 | int i; | |
237 | ||
238 | data = dma->buf + dma->current_period * dma->period_size; | |
239 | dma->current_period = 1 - dma->current_period; /* swap the buffer ID */ | |
240 | ||
241 | for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) { | |
242 | iio_push_to_buffers(indio_dev, data); | |
243 | data += indio_dev->scan_bytes; | |
244 | } | |
245 | } | |
246 | ||
247 | static int tiadc_start_dma(struct iio_dev *indio_dev) | |
248 | { | |
249 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
250 | struct tiadc_dma *dma = &adc_dev->dma; | |
251 | struct dma_async_tx_descriptor *desc; | |
252 | ||
253 | dma->current_period = 0; /* We start to fill period 0 */ | |
254 | /* | |
255 | * Make the fifo thresh as the multiple of total number of | |
256 | * channels enabled, so make sure that cyclic DMA period | |
257 | * length is also a multiple of total number of channels | |
258 | * enabled. This ensures that no invalid data is reported | |
259 | * to the stack via iio_push_to_buffers(). | |
260 | */ | |
261 | dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1, | |
262 | adc_dev->total_ch_enabled) - 1; | |
263 | /* Make sure that period length is multiple of fifo thresh level */ | |
264 | dma->period_size = rounddown(DMA_BUFFER_SIZE / 2, | |
265 | (dma->fifo_thresh + 1) * sizeof(u16)); | |
266 | ||
267 | dma->conf.src_maxburst = dma->fifo_thresh + 1; | |
268 | dmaengine_slave_config(dma->chan, &dma->conf); | |
269 | ||
270 | desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr, | |
271 | dma->period_size * 2, | |
272 | dma->period_size, DMA_DEV_TO_MEM, | |
273 | DMA_PREP_INTERRUPT); | |
274 | if (!desc) | |
275 | return -EBUSY; | |
276 | ||
277 | desc->callback = tiadc_dma_rx_complete; | |
278 | desc->callback_param = indio_dev; | |
279 | ||
280 | dma->cookie = dmaengine_submit(desc); | |
281 | ||
282 | dma_async_issue_pending(dma->chan); | |
283 | ||
284 | tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh); | |
285 | tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh); | |
286 | tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
ca9a5638 ZL |
291 | static int tiadc_buffer_preenable(struct iio_dev *indio_dev) |
292 | { | |
293 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
294 | int i, fifo1count, read; | |
295 | ||
296 | tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | | |
297 | IRQENB_FIFO1OVRRUN | | |
298 | IRQENB_FIFO1UNDRFLW)); | |
299 | ||
300 | /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */ | |
301 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); | |
302 | for (i = 0; i < fifo1count; i++) | |
303 | read = tiadc_readl(adc_dev, REG_FIFO1); | |
304 | ||
24adaf79 | 305 | return 0; |
ca9a5638 ZL |
306 | } |
307 | ||
308 | static int tiadc_buffer_postenable(struct iio_dev *indio_dev) | |
309 | { | |
310 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
f438b9da M |
311 | struct tiadc_dma *dma = &adc_dev->dma; |
312 | unsigned int irq_enable; | |
ca9a5638 ZL |
313 | unsigned int enb = 0; |
314 | u8 bit; | |
315 | ||
316 | tiadc_step_config(indio_dev); | |
f438b9da | 317 | for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) { |
ca9a5638 | 318 | enb |= (get_adc_step_bit(adc_dev, bit) << 1); |
f438b9da M |
319 | adc_dev->total_ch_enabled++; |
320 | } | |
ca9a5638 ZL |
321 | adc_dev->buffer_en_ch_steps = enb; |
322 | ||
f438b9da M |
323 | if (dma->chan) |
324 | tiadc_start_dma(indio_dev); | |
325 | ||
7e170c6e | 326 | am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb); |
ca9a5638 ZL |
327 | |
328 | tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES | |
329 | | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW); | |
f438b9da M |
330 | |
331 | irq_enable = IRQENB_FIFO1OVRRUN; | |
332 | if (!dma->chan) | |
333 | irq_enable |= IRQENB_FIFO1THRES; | |
334 | tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable); | |
ca9a5638 ZL |
335 | |
336 | return 0; | |
337 | } | |
338 | ||
339 | static int tiadc_buffer_predisable(struct iio_dev *indio_dev) | |
340 | { | |
341 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
f438b9da | 342 | struct tiadc_dma *dma = &adc_dev->dma; |
ca9a5638 ZL |
343 | int fifo1count, i, read; |
344 | ||
345 | tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | | |
346 | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW)); | |
347 | am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps); | |
3954b7bf | 348 | adc_dev->buffer_en_ch_steps = 0; |
f438b9da M |
349 | adc_dev->total_ch_enabled = 0; |
350 | if (dma->chan) { | |
351 | tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2); | |
352 | dmaengine_terminate_async(dma->chan); | |
353 | } | |
b1451e54 | 354 | |
ca9a5638 ZL |
355 | /* Flush FIFO of leftover data in the time it takes to disable adc */ |
356 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); | |
357 | for (i = 0; i < fifo1count; i++) | |
358 | read = tiadc_readl(adc_dev, REG_FIFO1); | |
359 | ||
360 | return 0; | |
5e53a69b PR |
361 | } |
362 | ||
ca9a5638 ZL |
363 | static int tiadc_buffer_postdisable(struct iio_dev *indio_dev) |
364 | { | |
365 | tiadc_step_config(indio_dev); | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = { | |
371 | .preenable = &tiadc_buffer_preenable, | |
372 | .postenable = &tiadc_buffer_postenable, | |
373 | .predisable = &tiadc_buffer_predisable, | |
374 | .postdisable = &tiadc_buffer_postdisable, | |
375 | }; | |
376 | ||
98c08cf4 | 377 | static int tiadc_iio_buffered_hardware_setup(struct iio_dev *indio_dev, |
ca9a5638 ZL |
378 | irqreturn_t (*pollfunc_bh)(int irq, void *p), |
379 | irqreturn_t (*pollfunc_th)(int irq, void *p), | |
380 | int irq, | |
381 | unsigned long flags, | |
382 | const struct iio_buffer_setup_ops *setup_ops) | |
383 | { | |
fe26980e | 384 | struct iio_buffer *buffer; |
ca9a5638 ZL |
385 | int ret; |
386 | ||
7ab374a0 | 387 | buffer = iio_kfifo_allocate(); |
fe26980e | 388 | if (!buffer) |
ca9a5638 ZL |
389 | return -ENOMEM; |
390 | ||
fe26980e LPC |
391 | iio_device_attach_buffer(indio_dev, buffer); |
392 | ||
ca9a5638 ZL |
393 | ret = request_threaded_irq(irq, pollfunc_th, pollfunc_bh, |
394 | flags, indio_dev->name, indio_dev); | |
395 | if (ret) | |
396 | goto error_kfifo_free; | |
397 | ||
398 | indio_dev->setup_ops = setup_ops; | |
9d0be85d | 399 | indio_dev->modes |= INDIO_BUFFER_SOFTWARE; |
ca9a5638 | 400 | |
ca9a5638 ZL |
401 | return 0; |
402 | ||
ca9a5638 ZL |
403 | error_kfifo_free: |
404 | iio_kfifo_free(indio_dev->buffer); | |
405 | return ret; | |
406 | } | |
407 | ||
408 | static void tiadc_iio_buffered_hardware_remove(struct iio_dev *indio_dev) | |
409 | { | |
410 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
411 | ||
412 | free_irq(adc_dev->mfd_tscadc->irq, indio_dev); | |
413 | iio_kfifo_free(indio_dev->buffer); | |
ca9a5638 ZL |
414 | } |
415 | ||
416 | ||
c80df483 PA |
417 | static const char * const chan_name_ain[] = { |
418 | "AIN0", | |
419 | "AIN1", | |
420 | "AIN2", | |
421 | "AIN3", | |
422 | "AIN4", | |
423 | "AIN5", | |
424 | "AIN6", | |
425 | "AIN7", | |
426 | }; | |
427 | ||
5e53a69b PR |
428 | static int tiadc_channel_init(struct iio_dev *indio_dev, int channels) |
429 | { | |
c80df483 | 430 | struct tiadc_device *adc_dev = iio_priv(indio_dev); |
5e53a69b | 431 | struct iio_chan_spec *chan_array; |
c80df483 | 432 | struct iio_chan_spec *chan; |
5e53a69b PR |
433 | int i; |
434 | ||
435 | indio_dev->num_channels = channels; | |
fea89e2d | 436 | chan_array = kcalloc(channels, sizeof(*chan_array), GFP_KERNEL); |
5e53a69b PR |
437 | if (chan_array == NULL) |
438 | return -ENOMEM; | |
439 | ||
c80df483 PA |
440 | chan = chan_array; |
441 | for (i = 0; i < channels; i++, chan++) { | |
442 | ||
5e53a69b PR |
443 | chan->type = IIO_VOLTAGE; |
444 | chan->indexed = 1; | |
18926ede | 445 | chan->channel = adc_dev->channel_line[i]; |
6c572522 | 446 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); |
18926ede | 447 | chan->datasheet_name = chan_name_ain[chan->channel]; |
ca9a5638 | 448 | chan->scan_index = i; |
c80df483 PA |
449 | chan->scan_type.sign = 'u'; |
450 | chan->scan_type.realbits = 12; | |
0f6fc7d5 | 451 | chan->scan_type.storagebits = 16; |
5e53a69b PR |
452 | } |
453 | ||
454 | indio_dev->channels = chan_array; | |
455 | ||
c80df483 | 456 | return 0; |
5e53a69b PR |
457 | } |
458 | ||
459 | static void tiadc_channels_remove(struct iio_dev *indio_dev) | |
460 | { | |
461 | kfree(indio_dev->channels); | |
462 | } | |
463 | ||
464 | static int tiadc_read_raw(struct iio_dev *indio_dev, | |
465 | struct iio_chan_spec const *chan, | |
466 | int *val, int *val2, long mask) | |
467 | { | |
468 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
90c43ec6 | 469 | int ret = IIO_VAL_INT; |
b1451e54 PR |
470 | int i, map_val; |
471 | unsigned int fifo1count, read, stepid; | |
1460c152 | 472 | bool found = false; |
b1451e54 | 473 | u32 step_en; |
7ca6740c | 474 | unsigned long timeout; |
ca9a5638 ZL |
475 | |
476 | if (iio_buffer_enabled(indio_dev)) | |
477 | return -EBUSY; | |
478 | ||
7ca6740c SAS |
479 | step_en = get_adc_chan_step_mask(adc_dev, chan); |
480 | if (!step_en) | |
481 | return -EINVAL; | |
482 | ||
90c43ec6 | 483 | mutex_lock(&adc_dev->fifo1_lock); |
7ca6740c SAS |
484 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); |
485 | while (fifo1count--) | |
486 | tiadc_readl(adc_dev, REG_FIFO1); | |
487 | ||
7e170c6e | 488 | am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en); |
b1451e54 | 489 | |
7175cce1 | 490 | timeout = jiffies + msecs_to_jiffies |
7ca6740c SAS |
491 | (IDLE_TIMEOUT * adc_dev->channels); |
492 | /* Wait for Fifo threshold interrupt */ | |
493 | while (1) { | |
494 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); | |
495 | if (fifo1count) | |
496 | break; | |
497 | ||
498 | if (time_after(jiffies, timeout)) { | |
499 | am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); | |
90c43ec6 V |
500 | ret = -EAGAIN; |
501 | goto err_unlock; | |
b1451e54 | 502 | } |
fb7f8ce3 | 503 | } |
baa3c652 | 504 | map_val = adc_dev->channel_step[chan->scan_index]; |
5e53a69b PR |
505 | |
506 | /* | |
7ca6740c SAS |
507 | * We check the complete FIFO. We programmed just one entry but in case |
508 | * something went wrong we left empty handed (-EAGAIN previously) and | |
509 | * then the value apeared somehow in the FIFO we would have two entries. | |
510 | * Therefore we read every item and keep only the latest version of the | |
511 | * requested channel. | |
5e53a69b | 512 | */ |
5e53a69b | 513 | for (i = 0; i < fifo1count; i++) { |
18926ede | 514 | read = tiadc_readl(adc_dev, REG_FIFO1); |
b1451e54 PR |
515 | stepid = read & FIFOREAD_CHNLID_MASK; |
516 | stepid = stepid >> 0x10; | |
517 | ||
518 | if (stepid == map_val) { | |
519 | read = read & FIFOREAD_DATA_MASK; | |
1460c152 | 520 | found = true; |
0f6fc7d5 | 521 | *val = (u16) read; |
1460c152 | 522 | } |
5e53a69b | 523 | } |
7ca6740c | 524 | am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); |
b1451e54 | 525 | |
1460c152 | 526 | if (found == false) |
90c43ec6 V |
527 | ret = -EBUSY; |
528 | ||
529 | err_unlock: | |
530 | mutex_unlock(&adc_dev->fifo1_lock); | |
531 | return ret; | |
5e53a69b PR |
532 | } |
533 | ||
534 | static const struct iio_info tiadc_info = { | |
535 | .read_raw = &tiadc_read_raw, | |
bc93aa76 | 536 | .driver_module = THIS_MODULE, |
5e53a69b PR |
537 | }; |
538 | ||
f438b9da M |
539 | static int tiadc_request_dma(struct platform_device *pdev, |
540 | struct tiadc_device *adc_dev) | |
541 | { | |
542 | struct tiadc_dma *dma = &adc_dev->dma; | |
543 | dma_cap_mask_t mask; | |
544 | ||
545 | /* Default slave configuration parameters */ | |
546 | dma->conf.direction = DMA_DEV_TO_MEM; | |
547 | dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
548 | dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1; | |
549 | ||
550 | dma_cap_zero(mask); | |
551 | dma_cap_set(DMA_CYCLIC, mask); | |
552 | ||
553 | /* Get a channel for RX */ | |
554 | dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1"); | |
555 | if (IS_ERR(dma->chan)) { | |
556 | int ret = PTR_ERR(dma->chan); | |
557 | ||
558 | dma->chan = NULL; | |
559 | return ret; | |
560 | } | |
561 | ||
562 | /* RX buffer */ | |
563 | dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, | |
564 | &dma->addr, GFP_KERNEL); | |
565 | if (!dma->buf) | |
566 | goto err; | |
567 | ||
568 | return 0; | |
569 | err: | |
570 | dma_release_channel(dma->chan); | |
571 | return -ENOMEM; | |
572 | } | |
573 | ||
dee1f550 V |
574 | static int tiadc_parse_dt(struct platform_device *pdev, |
575 | struct tiadc_device *adc_dev) | |
576 | { | |
577 | struct device_node *node = pdev->dev.of_node; | |
578 | struct property *prop; | |
579 | const __be32 *cur; | |
580 | int channels = 0; | |
581 | u32 val; | |
582 | ||
583 | of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { | |
584 | adc_dev->channel_line[channels] = val; | |
5dc11e81 V |
585 | |
586 | /* Set Default values for optional DT parameters */ | |
587 | adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY; | |
588 | adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY; | |
589 | adc_dev->step_avg[channels] = 16; | |
590 | ||
dee1f550 V |
591 | channels++; |
592 | } | |
593 | ||
5dc11e81 V |
594 | of_property_read_u32_array(node, "ti,chan-step-avg", |
595 | adc_dev->step_avg, channels); | |
596 | of_property_read_u32_array(node, "ti,chan-step-opendelay", | |
597 | adc_dev->open_delay, channels); | |
598 | of_property_read_u32_array(node, "ti,chan-step-sampledelay", | |
599 | adc_dev->sample_delay, channels); | |
600 | ||
dee1f550 V |
601 | adc_dev->channels = channels; |
602 | return 0; | |
603 | } | |
604 | ||
fc52692c | 605 | static int tiadc_probe(struct platform_device *pdev) |
5e53a69b PR |
606 | { |
607 | struct iio_dev *indio_dev; | |
608 | struct tiadc_device *adc_dev; | |
6f39ac4e | 609 | struct device_node *node = pdev->dev.of_node; |
5e53a69b PR |
610 | int err; |
611 | ||
0ead4fb2 SAS |
612 | if (!node) { |
613 | dev_err(&pdev->dev, "Could not find valid DT data.\n"); | |
5e53a69b PR |
614 | return -EINVAL; |
615 | } | |
616 | ||
fea89e2d | 617 | indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*indio_dev)); |
5e53a69b PR |
618 | if (indio_dev == NULL) { |
619 | dev_err(&pdev->dev, "failed to allocate iio device\n"); | |
a0648130 | 620 | return -ENOMEM; |
5e53a69b PR |
621 | } |
622 | adc_dev = iio_priv(indio_dev); | |
623 | ||
6f39ac4e | 624 | adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev); |
dee1f550 | 625 | tiadc_parse_dt(pdev, adc_dev); |
5e53a69b PR |
626 | |
627 | indio_dev->dev.parent = &pdev->dev; | |
628 | indio_dev->name = dev_name(&pdev->dev); | |
629 | indio_dev->modes = INDIO_DIRECT_MODE; | |
630 | indio_dev->info = &tiadc_info; | |
631 | ||
ca9a5638 ZL |
632 | tiadc_step_config(indio_dev); |
633 | tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD); | |
90c43ec6 | 634 | mutex_init(&adc_dev->fifo1_lock); |
5e53a69b PR |
635 | |
636 | err = tiadc_channel_init(indio_dev, adc_dev->channels); | |
637 | if (err < 0) | |
a0648130 | 638 | return err; |
5e53a69b | 639 | |
ca9a5638 ZL |
640 | err = tiadc_iio_buffered_hardware_setup(indio_dev, |
641 | &tiadc_worker_h, | |
642 | &tiadc_irq_h, | |
643 | adc_dev->mfd_tscadc->irq, | |
644 | IRQF_SHARED, | |
645 | &tiadc_buffer_setup_ops); | |
646 | ||
5e53a69b PR |
647 | if (err) |
648 | goto err_free_channels; | |
649 | ||
ca9a5638 ZL |
650 | err = iio_device_register(indio_dev); |
651 | if (err) | |
652 | goto err_buffer_unregister; | |
653 | ||
5e53a69b PR |
654 | platform_set_drvdata(pdev, indio_dev); |
655 | ||
f438b9da M |
656 | err = tiadc_request_dma(pdev, adc_dev); |
657 | if (err && err == -EPROBE_DEFER) | |
658 | goto err_dma; | |
659 | ||
5e53a69b PR |
660 | return 0; |
661 | ||
f438b9da M |
662 | err_dma: |
663 | iio_device_unregister(indio_dev); | |
ca9a5638 ZL |
664 | err_buffer_unregister: |
665 | tiadc_iio_buffered_hardware_remove(indio_dev); | |
5e53a69b PR |
666 | err_free_channels: |
667 | tiadc_channels_remove(indio_dev); | |
5e53a69b PR |
668 | return err; |
669 | } | |
670 | ||
fc52692c | 671 | static int tiadc_remove(struct platform_device *pdev) |
5e53a69b PR |
672 | { |
673 | struct iio_dev *indio_dev = platform_get_drvdata(pdev); | |
abeccee4 | 674 | struct tiadc_device *adc_dev = iio_priv(indio_dev); |
f438b9da | 675 | struct tiadc_dma *dma = &adc_dev->dma; |
abeccee4 | 676 | u32 step_en; |
5e53a69b | 677 | |
f438b9da M |
678 | if (dma->chan) { |
679 | dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, | |
680 | dma->buf, dma->addr); | |
681 | dma_release_channel(dma->chan); | |
682 | } | |
5e53a69b | 683 | iio_device_unregister(indio_dev); |
ca9a5638 | 684 | tiadc_iio_buffered_hardware_remove(indio_dev); |
5e53a69b PR |
685 | tiadc_channels_remove(indio_dev); |
686 | ||
abeccee4 PR |
687 | step_en = get_adc_step_mask(adc_dev); |
688 | am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en); | |
689 | ||
5e53a69b PR |
690 | return 0; |
691 | } | |
692 | ||
27aa832d | 693 | static int __maybe_unused tiadc_suspend(struct device *dev) |
5e53a69b PR |
694 | { |
695 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
696 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
a9bce1b0 | 697 | struct ti_tscadc_dev *tscadc_dev; |
5e53a69b PR |
698 | unsigned int idle; |
699 | ||
a9bce1b0 | 700 | tscadc_dev = ti_tscadc_dev_get(to_platform_device(dev)); |
5e53a69b PR |
701 | if (!device_may_wakeup(tscadc_dev->dev)) { |
702 | idle = tiadc_readl(adc_dev, REG_CTRL); | |
703 | idle &= ~(CNTRLREG_TSCSSENB); | |
704 | tiadc_writel(adc_dev, REG_CTRL, (idle | | |
705 | CNTRLREG_POWERDOWN)); | |
706 | } | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
27aa832d | 711 | static int __maybe_unused tiadc_resume(struct device *dev) |
5e53a69b PR |
712 | { |
713 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
714 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
715 | unsigned int restore; | |
716 | ||
717 | /* Make sure ADC is powered up */ | |
718 | restore = tiadc_readl(adc_dev, REG_CTRL); | |
719 | restore &= ~(CNTRLREG_POWERDOWN); | |
720 | tiadc_writel(adc_dev, REG_CTRL, restore); | |
721 | ||
ca9a5638 | 722 | tiadc_step_config(indio_dev); |
7ca6740c SAS |
723 | am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, |
724 | adc_dev->buffer_en_ch_steps); | |
5e53a69b PR |
725 | return 0; |
726 | } | |
727 | ||
27aa832d | 728 | static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); |
5e53a69b | 729 | |
6f39ac4e PR |
730 | static const struct of_device_id ti_adc_dt_ids[] = { |
731 | { .compatible = "ti,am3359-adc", }, | |
732 | { } | |
733 | }; | |
734 | MODULE_DEVICE_TABLE(of, ti_adc_dt_ids); | |
735 | ||
5e53a69b PR |
736 | static struct platform_driver tiadc_driver = { |
737 | .driver = { | |
9f99928f | 738 | .name = "TI-am335x-adc", |
27aa832d | 739 | .pm = &tiadc_pm_ops, |
de06b344 | 740 | .of_match_table = ti_adc_dt_ids, |
5e53a69b PR |
741 | }, |
742 | .probe = tiadc_probe, | |
fc52692c | 743 | .remove = tiadc_remove, |
5e53a69b | 744 | }; |
5e53a69b PR |
745 | module_platform_driver(tiadc_driver); |
746 | ||
747 | MODULE_DESCRIPTION("TI ADC controller driver"); | |
748 | MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); | |
749 | MODULE_LICENSE("GPL"); |