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f99c1d4f K |
1 | /* |
2 | * | |
3 | * TWL4030 MADC module driver-This driver monitors the real time | |
4 | * conversion of analog signals like battery temperature, | |
5 | * battery type, battery level etc. | |
6 | * | |
7 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
8 | * J Keerthy <j-keerthy@ti.com> | |
9 | * | |
10 | * Based on twl4030-madc.c | |
11 | * Copyright (C) 2008 Nokia Corporation | |
12 | * Mikko Ylinen <mikko.k.ylinen@nokia.com> | |
13 | * | |
14 | * Amit Kucheria <amit.kucheria@canonical.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License | |
18 | * version 2 as published by the Free Software Foundation. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, but | |
21 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
23 | * General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
28 | * 02110-1301 USA | |
29 | * | |
30 | */ | |
31 | ||
f99c1d4f K |
32 | #include <linux/device.h> |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/i2c/twl.h> | |
39 | #include <linux/i2c/twl4030-madc.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/stddef.h> | |
42 | #include <linux/mutex.h> | |
43 | #include <linux/bitops.h> | |
44 | #include <linux/jiffies.h> | |
45 | #include <linux/types.h> | |
46 | #include <linux/gfp.h> | |
47 | #include <linux/err.h> | |
7cc97d77 | 48 | #include <linux/regulator/consumer.h> |
f99c1d4f | 49 | |
2f39b70f SR |
50 | #include <linux/iio/iio.h> |
51 | ||
7cc97d77 AYL |
52 | #define TWL4030_USB_SEL_MADC_MCPC (1<<3) |
53 | #define TWL4030_USB_CARKIT_ANA_CTRL 0xBB | |
54 | ||
99be0245 | 55 | /** |
f99c1d4f | 56 | * struct twl4030_madc_data - a container for madc info |
99be0245 SR |
57 | * @dev: Pointer to device structure for madc |
58 | * @lock: Mutex protecting this data structure | |
7cc97d77 | 59 | * @regulator: Pointer to bias regulator for madc |
99be0245 SR |
60 | * @requests: Array of request struct corresponding to SW1, SW2 and RT |
61 | * @use_second_irq: IRQ selection (main or co-processor) | |
62 | * @imr: Interrupt mask register of MADC | |
63 | * @isr: Interrupt status register of MADC | |
f99c1d4f K |
64 | */ |
65 | struct twl4030_madc_data { | |
66 | struct device *dev; | |
67 | struct mutex lock; /* mutex protecting this data structure */ | |
7cc97d77 | 68 | struct regulator *usb3v1; |
f99c1d4f | 69 | struct twl4030_madc_request requests[TWL4030_MADC_NUM_METHODS]; |
2f39b70f | 70 | bool use_second_irq; |
99be0245 SR |
71 | u8 imr; |
72 | u8 isr; | |
f99c1d4f K |
73 | }; |
74 | ||
2f39b70f SR |
75 | static int twl4030_madc_read(struct iio_dev *iio_dev, |
76 | const struct iio_chan_spec *chan, | |
77 | int *val, int *val2, long mask) | |
78 | { | |
79 | struct twl4030_madc_data *madc = iio_priv(iio_dev); | |
80 | struct twl4030_madc_request req; | |
81 | int ret; | |
82 | ||
83 | req.method = madc->use_second_irq ? TWL4030_MADC_SW2 : TWL4030_MADC_SW1; | |
84 | ||
85 | req.channels = BIT(chan->channel); | |
86 | req.active = false; | |
87 | req.func_cb = NULL; | |
88 | req.type = TWL4030_MADC_WAIT; | |
89 | req.raw = !(mask == IIO_CHAN_INFO_PROCESSED); | |
90 | req.do_avg = (mask == IIO_CHAN_INFO_AVERAGE_RAW); | |
91 | ||
92 | ret = twl4030_madc_conversion(&req); | |
93 | if (ret < 0) | |
94 | return ret; | |
95 | ||
96 | *val = req.rbuf[chan->channel]; | |
97 | ||
98 | return IIO_VAL_INT; | |
99 | } | |
100 | ||
101 | static const struct iio_info twl4030_madc_iio_info = { | |
102 | .read_raw = &twl4030_madc_read, | |
103 | .driver_module = THIS_MODULE, | |
104 | }; | |
105 | ||
106 | #define TWL4030_ADC_CHANNEL(_channel, _type, _name) { \ | |
107 | .type = _type, \ | |
108 | .channel = _channel, \ | |
109 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ | |
110 | BIT(IIO_CHAN_INFO_AVERAGE_RAW) | \ | |
111 | BIT(IIO_CHAN_INFO_PROCESSED), \ | |
112 | .datasheet_name = _name, \ | |
113 | .indexed = 1, \ | |
114 | } | |
115 | ||
116 | static const struct iio_chan_spec twl4030_madc_iio_channels[] = { | |
117 | TWL4030_ADC_CHANNEL(0, IIO_VOLTAGE, "ADCIN0"), | |
118 | TWL4030_ADC_CHANNEL(1, IIO_TEMP, "ADCIN1"), | |
119 | TWL4030_ADC_CHANNEL(2, IIO_VOLTAGE, "ADCIN2"), | |
120 | TWL4030_ADC_CHANNEL(3, IIO_VOLTAGE, "ADCIN3"), | |
121 | TWL4030_ADC_CHANNEL(4, IIO_VOLTAGE, "ADCIN4"), | |
122 | TWL4030_ADC_CHANNEL(5, IIO_VOLTAGE, "ADCIN5"), | |
123 | TWL4030_ADC_CHANNEL(6, IIO_VOLTAGE, "ADCIN6"), | |
124 | TWL4030_ADC_CHANNEL(7, IIO_VOLTAGE, "ADCIN7"), | |
125 | TWL4030_ADC_CHANNEL(8, IIO_VOLTAGE, "ADCIN8"), | |
126 | TWL4030_ADC_CHANNEL(9, IIO_VOLTAGE, "ADCIN9"), | |
127 | TWL4030_ADC_CHANNEL(10, IIO_CURRENT, "ADCIN10"), | |
128 | TWL4030_ADC_CHANNEL(11, IIO_VOLTAGE, "ADCIN11"), | |
129 | TWL4030_ADC_CHANNEL(12, IIO_VOLTAGE, "ADCIN12"), | |
130 | TWL4030_ADC_CHANNEL(13, IIO_VOLTAGE, "ADCIN13"), | |
131 | TWL4030_ADC_CHANNEL(14, IIO_VOLTAGE, "ADCIN14"), | |
132 | TWL4030_ADC_CHANNEL(15, IIO_VOLTAGE, "ADCIN15"), | |
133 | }; | |
134 | ||
f99c1d4f K |
135 | static struct twl4030_madc_data *twl4030_madc; |
136 | ||
137 | struct twl4030_prescale_divider_ratios { | |
138 | s16 numerator; | |
139 | s16 denominator; | |
140 | }; | |
141 | ||
142 | static const struct twl4030_prescale_divider_ratios | |
143 | twl4030_divider_ratios[16] = { | |
144 | {1, 1}, /* CHANNEL 0 No Prescaler */ | |
145 | {1, 1}, /* CHANNEL 1 No Prescaler */ | |
146 | {6, 10}, /* CHANNEL 2 */ | |
147 | {6, 10}, /* CHANNEL 3 */ | |
148 | {6, 10}, /* CHANNEL 4 */ | |
149 | {6, 10}, /* CHANNEL 5 */ | |
150 | {6, 10}, /* CHANNEL 6 */ | |
151 | {6, 10}, /* CHANNEL 7 */ | |
152 | {3, 14}, /* CHANNEL 8 */ | |
153 | {1, 3}, /* CHANNEL 9 */ | |
154 | {1, 1}, /* CHANNEL 10 No Prescaler */ | |
155 | {15, 100}, /* CHANNEL 11 */ | |
156 | {1, 4}, /* CHANNEL 12 */ | |
157 | {1, 1}, /* CHANNEL 13 Reserved channels */ | |
158 | {1, 1}, /* CHANNEL 14 Reseved channels */ | |
159 | {5, 11}, /* CHANNEL 15 */ | |
160 | }; | |
161 | ||
162 | ||
99be0245 SR |
163 | /* Conversion table from -3 to 55 degrees Celcius */ |
164 | static int twl4030_therm_tbl[] = { | |
165 | 30800, 29500, 28300, 27100, | |
166 | 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, | |
167 | 17900, 17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, | |
168 | 12600, 12100, 11600, 11200, 10800, 10400, 10000, 9630, 9280, | |
169 | 8950, 8620, 8310, 8020, 7730, 7460, 7200, 6950, 6710, | |
170 | 6470, 6250, 6040, 5830, 5640, 5450, 5260, 5090, 4920, | |
171 | 4760, 4600, 4450, 4310, 4170, 4040, 3910, 3790, 3670, | |
172 | 3550 | |
f99c1d4f K |
173 | }; |
174 | ||
175 | /* | |
176 | * Structure containing the registers | |
177 | * of different conversion methods supported by MADC. | |
178 | * Hardware or RT real time conversion request initiated by external host | |
179 | * processor for RT Signal conversions. | |
180 | * External host processors can also request for non RT conversions | |
181 | * SW1 and SW2 software conversions also called asynchronous or GPC request. | |
182 | */ | |
183 | static | |
184 | const struct twl4030_madc_conversion_method twl4030_conversion_methods[] = { | |
185 | [TWL4030_MADC_RT] = { | |
186 | .sel = TWL4030_MADC_RTSELECT_LSB, | |
187 | .avg = TWL4030_MADC_RTAVERAGE_LSB, | |
188 | .rbase = TWL4030_MADC_RTCH0_LSB, | |
189 | }, | |
190 | [TWL4030_MADC_SW1] = { | |
191 | .sel = TWL4030_MADC_SW1SELECT_LSB, | |
192 | .avg = TWL4030_MADC_SW1AVERAGE_LSB, | |
193 | .rbase = TWL4030_MADC_GPCH0_LSB, | |
194 | .ctrl = TWL4030_MADC_CTRL_SW1, | |
195 | }, | |
196 | [TWL4030_MADC_SW2] = { | |
197 | .sel = TWL4030_MADC_SW2SELECT_LSB, | |
198 | .avg = TWL4030_MADC_SW2AVERAGE_LSB, | |
199 | .rbase = TWL4030_MADC_GPCH0_LSB, | |
200 | .ctrl = TWL4030_MADC_CTRL_SW2, | |
201 | }, | |
202 | }; | |
203 | ||
99be0245 SR |
204 | /** |
205 | * twl4030_madc_channel_raw_read() - Function to read a particular channel value | |
206 | * @madc: pointer to struct twl4030_madc_data | |
207 | * @reg: lsb of ADC Channel | |
208 | * | |
209 | * Return: 0 on success, an error code otherwise. | |
f99c1d4f K |
210 | */ |
211 | static int twl4030_madc_channel_raw_read(struct twl4030_madc_data *madc, u8 reg) | |
212 | { | |
168ae308 | 213 | u16 val; |
f99c1d4f K |
214 | int ret; |
215 | /* | |
216 | * For each ADC channel, we have MSB and LSB register pair. MSB address | |
217 | * is always LSB address+1. reg parameter is the address of LSB register | |
218 | */ | |
168ae308 | 219 | ret = twl_i2c_read_u16(TWL4030_MODULE_MADC, &val, reg); |
f99c1d4f | 220 | if (ret) { |
168ae308 | 221 | dev_err(madc->dev, "unable to read register 0x%X\n", reg); |
f99c1d4f K |
222 | return ret; |
223 | } | |
224 | ||
168ae308 | 225 | return (int)(val >> 6); |
f99c1d4f K |
226 | } |
227 | ||
228 | /* | |
99be0245 | 229 | * Return battery temperature in degrees Celsius |
f99c1d4f K |
230 | * Or < 0 on failure. |
231 | */ | |
232 | static int twl4030battery_temperature(int raw_volt) | |
233 | { | |
234 | u8 val; | |
235 | int temp, curr, volt, res, ret; | |
236 | ||
237 | volt = (raw_volt * TEMP_STEP_SIZE) / TEMP_PSR_R; | |
99be0245 | 238 | /* Getting and calculating the supply current in micro amperes */ |
e45342f6 | 239 | ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, &val, |
f99c1d4f K |
240 | REG_BCICTL2); |
241 | if (ret < 0) | |
242 | return ret; | |
99be0245 | 243 | |
0cbb39f1 | 244 | curr = ((val & TWL4030_BCI_ITHSENS) + 1) * 10; |
f99c1d4f K |
245 | /* Getting and calculating the thermistor resistance in ohms */ |
246 | res = volt * 1000 / curr; | |
247 | /* calculating temperature */ | |
248 | for (temp = 58; temp >= 0; temp--) { | |
99be0245 | 249 | int actual = twl4030_therm_tbl[temp]; |
f99c1d4f K |
250 | if ((actual - res) >= 0) |
251 | break; | |
252 | } | |
253 | ||
254 | return temp + 1; | |
255 | } | |
256 | ||
257 | static int twl4030battery_current(int raw_volt) | |
258 | { | |
259 | int ret; | |
260 | u8 val; | |
261 | ||
e45342f6 | 262 | ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, &val, |
f99c1d4f K |
263 | TWL4030_BCI_BCICTL1); |
264 | if (ret) | |
265 | return ret; | |
266 | if (val & TWL4030_BCI_CGAIN) /* slope of 0.44 mV/mA */ | |
267 | return (raw_volt * CURR_STEP_SIZE) / CURR_PSR_R1; | |
268 | else /* slope of 0.88 mV/mA */ | |
269 | return (raw_volt * CURR_STEP_SIZE) / CURR_PSR_R2; | |
270 | } | |
99be0245 | 271 | |
f99c1d4f K |
272 | /* |
273 | * Function to read channel values | |
274 | * @madc - pointer to twl4030_madc_data struct | |
275 | * @reg_base - Base address of the first channel | |
99be0245 | 276 | * @Channels - 16 bit bitmap. If the bit is set, channel's value is read |
f99c1d4f | 277 | * @buf - The channel values are stored here. if read fails error |
a5055d5d | 278 | * @raw - Return raw values without conversion |
f99c1d4f K |
279 | * value is stored |
280 | * Returns the number of successfully read channels. | |
281 | */ | |
282 | static int twl4030_madc_read_channels(struct twl4030_madc_data *madc, | |
283 | u8 reg_base, unsigned | |
a5055d5d PR |
284 | long channels, int *buf, |
285 | bool raw) | |
f99c1d4f | 286 | { |
99be0245 SR |
287 | int count = 0; |
288 | int i; | |
f99c1d4f K |
289 | u8 reg; |
290 | ||
291 | for_each_set_bit(i, &channels, TWL4030_MADC_MAX_CHANNELS) { | |
99be0245 | 292 | reg = reg_base + (2 * i); |
f99c1d4f K |
293 | buf[i] = twl4030_madc_channel_raw_read(madc, reg); |
294 | if (buf[i] < 0) { | |
99be0245 SR |
295 | dev_err(madc->dev, "Unable to read register 0x%X\n", |
296 | reg); | |
297 | return buf[i]; | |
f99c1d4f | 298 | } |
a5055d5d PR |
299 | if (raw) { |
300 | count++; | |
301 | continue; | |
302 | } | |
f99c1d4f K |
303 | switch (i) { |
304 | case 10: | |
305 | buf[i] = twl4030battery_current(buf[i]); | |
306 | if (buf[i] < 0) { | |
307 | dev_err(madc->dev, "err reading current\n"); | |
99be0245 | 308 | return buf[i]; |
f99c1d4f K |
309 | } else { |
310 | count++; | |
311 | buf[i] = buf[i] - 750; | |
312 | } | |
313 | break; | |
314 | case 1: | |
315 | buf[i] = twl4030battery_temperature(buf[i]); | |
316 | if (buf[i] < 0) { | |
317 | dev_err(madc->dev, "err reading temperature\n"); | |
99be0245 | 318 | return buf[i]; |
f99c1d4f K |
319 | } else { |
320 | buf[i] -= 3; | |
321 | count++; | |
322 | } | |
323 | break; | |
324 | default: | |
325 | count++; | |
326 | /* Analog Input (V) = conv_result * step_size / R | |
327 | * conv_result = decimal value of 10-bit conversion | |
328 | * result | |
329 | * step size = 1.5 / (2 ^ 10 -1) | |
330 | * R = Prescaler ratio for input channels. | |
331 | * Result given in mV hence multiplied by 1000. | |
332 | */ | |
333 | buf[i] = (buf[i] * 3 * 1000 * | |
334 | twl4030_divider_ratios[i].denominator) | |
335 | / (2 * 1023 * | |
336 | twl4030_divider_ratios[i].numerator); | |
337 | } | |
338 | } | |
f99c1d4f K |
339 | |
340 | return count; | |
341 | } | |
342 | ||
343 | /* | |
344 | * Enables irq. | |
345 | * @madc - pointer to twl4030_madc_data struct | |
346 | * @id - irq number to be enabled | |
347 | * can take one of TWL4030_MADC_RT, TWL4030_MADC_SW1, TWL4030_MADC_SW2 | |
348 | * corresponding to RT, SW1, SW2 conversion requests. | |
349 | * If the i2c read fails it returns an error else returns 0. | |
350 | */ | |
351 | static int twl4030_madc_enable_irq(struct twl4030_madc_data *madc, u8 id) | |
352 | { | |
353 | u8 val; | |
354 | int ret; | |
355 | ||
356 | ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &val, madc->imr); | |
357 | if (ret) { | |
358 | dev_err(madc->dev, "unable to read imr register 0x%X\n", | |
359 | madc->imr); | |
360 | return ret; | |
361 | } | |
99be0245 | 362 | |
f99c1d4f K |
363 | val &= ~(1 << id); |
364 | ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, val, madc->imr); | |
365 | if (ret) { | |
366 | dev_err(madc->dev, | |
367 | "unable to write imr register 0x%X\n", madc->imr); | |
368 | return ret; | |
f99c1d4f K |
369 | } |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | /* | |
375 | * Disables irq. | |
376 | * @madc - pointer to twl4030_madc_data struct | |
377 | * @id - irq number to be disabled | |
378 | * can take one of TWL4030_MADC_RT, TWL4030_MADC_SW1, TWL4030_MADC_SW2 | |
379 | * corresponding to RT, SW1, SW2 conversion requests. | |
380 | * Returns error if i2c read/write fails. | |
381 | */ | |
382 | static int twl4030_madc_disable_irq(struct twl4030_madc_data *madc, u8 id) | |
383 | { | |
384 | u8 val; | |
385 | int ret; | |
386 | ||
387 | ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &val, madc->imr); | |
388 | if (ret) { | |
389 | dev_err(madc->dev, "unable to read imr register 0x%X\n", | |
390 | madc->imr); | |
391 | return ret; | |
392 | } | |
393 | val |= (1 << id); | |
394 | ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, val, madc->imr); | |
395 | if (ret) { | |
396 | dev_err(madc->dev, | |
397 | "unable to write imr register 0x%X\n", madc->imr); | |
398 | return ret; | |
399 | } | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
404 | static irqreturn_t twl4030_madc_threaded_irq_handler(int irq, void *_madc) | |
405 | { | |
406 | struct twl4030_madc_data *madc = _madc; | |
407 | const struct twl4030_madc_conversion_method *method; | |
408 | u8 isr_val, imr_val; | |
409 | int i, len, ret; | |
410 | struct twl4030_madc_request *r; | |
411 | ||
412 | mutex_lock(&madc->lock); | |
413 | ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &isr_val, madc->isr); | |
414 | if (ret) { | |
415 | dev_err(madc->dev, "unable to read isr register 0x%X\n", | |
416 | madc->isr); | |
417 | goto err_i2c; | |
418 | } | |
419 | ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &imr_val, madc->imr); | |
420 | if (ret) { | |
421 | dev_err(madc->dev, "unable to read imr register 0x%X\n", | |
422 | madc->imr); | |
423 | goto err_i2c; | |
424 | } | |
425 | isr_val &= ~imr_val; | |
426 | for (i = 0; i < TWL4030_MADC_NUM_METHODS; i++) { | |
427 | if (!(isr_val & (1 << i))) | |
428 | continue; | |
429 | ret = twl4030_madc_disable_irq(madc, i); | |
430 | if (ret < 0) | |
99be0245 | 431 | dev_dbg(madc->dev, "Disable interrupt failed %d\n", i); |
f99c1d4f K |
432 | madc->requests[i].result_pending = 1; |
433 | } | |
434 | for (i = 0; i < TWL4030_MADC_NUM_METHODS; i++) { | |
435 | r = &madc->requests[i]; | |
436 | /* No pending results for this method, move to next one */ | |
437 | if (!r->result_pending) | |
438 | continue; | |
439 | method = &twl4030_conversion_methods[r->method]; | |
440 | /* Read results */ | |
441 | len = twl4030_madc_read_channels(madc, method->rbase, | |
a5055d5d | 442 | r->channels, r->rbuf, r->raw); |
f99c1d4f K |
443 | /* Return results to caller */ |
444 | if (r->func_cb != NULL) { | |
445 | r->func_cb(len, r->channels, r->rbuf); | |
446 | r->func_cb = NULL; | |
447 | } | |
448 | /* Free request */ | |
449 | r->result_pending = 0; | |
450 | r->active = 0; | |
451 | } | |
452 | mutex_unlock(&madc->lock); | |
453 | ||
454 | return IRQ_HANDLED; | |
455 | ||
456 | err_i2c: | |
457 | /* | |
458 | * In case of error check whichever request is active | |
459 | * and service the same. | |
460 | */ | |
461 | for (i = 0; i < TWL4030_MADC_NUM_METHODS; i++) { | |
462 | r = &madc->requests[i]; | |
463 | if (r->active == 0) | |
464 | continue; | |
465 | method = &twl4030_conversion_methods[r->method]; | |
466 | /* Read results */ | |
467 | len = twl4030_madc_read_channels(madc, method->rbase, | |
a5055d5d | 468 | r->channels, r->rbuf, r->raw); |
f99c1d4f K |
469 | /* Return results to caller */ |
470 | if (r->func_cb != NULL) { | |
471 | r->func_cb(len, r->channels, r->rbuf); | |
472 | r->func_cb = NULL; | |
473 | } | |
474 | /* Free request */ | |
475 | r->result_pending = 0; | |
476 | r->active = 0; | |
477 | } | |
478 | mutex_unlock(&madc->lock); | |
479 | ||
480 | return IRQ_HANDLED; | |
481 | } | |
482 | ||
483 | static int twl4030_madc_set_irq(struct twl4030_madc_data *madc, | |
484 | struct twl4030_madc_request *req) | |
485 | { | |
486 | struct twl4030_madc_request *p; | |
487 | int ret; | |
488 | ||
489 | p = &madc->requests[req->method]; | |
490 | memcpy(p, req, sizeof(*req)); | |
491 | ret = twl4030_madc_enable_irq(madc, req->method); | |
492 | if (ret < 0) { | |
493 | dev_err(madc->dev, "enable irq failed!!\n"); | |
494 | return ret; | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | /* | |
501 | * Function which enables the madc conversion | |
502 | * by writing to the control register. | |
503 | * @madc - pointer to twl4030_madc_data struct | |
504 | * @conv_method - can be TWL4030_MADC_RT, TWL4030_MADC_SW2, TWL4030_MADC_SW1 | |
505 | * corresponding to RT SW1 or SW2 conversion methods. | |
506 | * Returns 0 if succeeds else a negative error value | |
507 | */ | |
508 | static int twl4030_madc_start_conversion(struct twl4030_madc_data *madc, | |
509 | int conv_method) | |
510 | { | |
511 | const struct twl4030_madc_conversion_method *method; | |
512 | int ret = 0; | |
99be0245 SR |
513 | |
514 | if (conv_method != TWL4030_MADC_SW1 && conv_method != TWL4030_MADC_SW2) | |
515 | return -ENOTSUPP; | |
516 | ||
f99c1d4f | 517 | method = &twl4030_conversion_methods[conv_method]; |
99be0245 SR |
518 | ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, TWL4030_MADC_SW_START, |
519 | method->ctrl); | |
520 | if (ret) { | |
521 | dev_err(madc->dev, "unable to write ctrl register 0x%X\n", | |
522 | method->ctrl); | |
523 | return ret; | |
f99c1d4f K |
524 | } |
525 | ||
526 | return 0; | |
527 | } | |
528 | ||
529 | /* | |
530 | * Function that waits for conversion to be ready | |
531 | * @madc - pointer to twl4030_madc_data struct | |
532 | * @timeout_ms - timeout value in milliseconds | |
533 | * @status_reg - ctrl register | |
534 | * returns 0 if succeeds else a negative error value | |
535 | */ | |
536 | static int twl4030_madc_wait_conversion_ready(struct twl4030_madc_data *madc, | |
537 | unsigned int timeout_ms, | |
538 | u8 status_reg) | |
539 | { | |
540 | unsigned long timeout; | |
541 | int ret; | |
542 | ||
543 | timeout = jiffies + msecs_to_jiffies(timeout_ms); | |
544 | do { | |
545 | u8 reg; | |
546 | ||
547 | ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, ®, status_reg); | |
548 | if (ret) { | |
549 | dev_err(madc->dev, | |
550 | "unable to read status register 0x%X\n", | |
551 | status_reg); | |
552 | return ret; | |
553 | } | |
554 | if (!(reg & TWL4030_MADC_BUSY) && (reg & TWL4030_MADC_EOC_SW)) | |
555 | return 0; | |
556 | usleep_range(500, 2000); | |
557 | } while (!time_after(jiffies, timeout)); | |
558 | dev_err(madc->dev, "conversion timeout!\n"); | |
559 | ||
560 | return -EAGAIN; | |
561 | } | |
562 | ||
563 | /* | |
564 | * An exported function which can be called from other kernel drivers. | |
565 | * @req twl4030_madc_request structure | |
566 | * req->rbuf will be filled with read values of channels based on the | |
567 | * channel index. If a particular channel reading fails there will | |
568 | * be a negative error value in the corresponding array element. | |
569 | * returns 0 if succeeds else error value | |
570 | */ | |
571 | int twl4030_madc_conversion(struct twl4030_madc_request *req) | |
572 | { | |
573 | const struct twl4030_madc_conversion_method *method; | |
f99c1d4f K |
574 | int ret; |
575 | ||
d0e84cae | 576 | if (!req || !twl4030_madc) |
f99c1d4f | 577 | return -EINVAL; |
d0e84cae | 578 | |
f99c1d4f K |
579 | mutex_lock(&twl4030_madc->lock); |
580 | if (req->method < TWL4030_MADC_RT || req->method > TWL4030_MADC_SW2) { | |
581 | ret = -EINVAL; | |
582 | goto out; | |
583 | } | |
584 | /* Do we have a conversion request ongoing */ | |
585 | if (twl4030_madc->requests[req->method].active) { | |
586 | ret = -EBUSY; | |
587 | goto out; | |
588 | } | |
f99c1d4f K |
589 | method = &twl4030_conversion_methods[req->method]; |
590 | /* Select channels to be converted */ | |
168ae308 | 591 | ret = twl_i2c_write_u16(TWL4030_MODULE_MADC, req->channels, method->sel); |
f99c1d4f K |
592 | if (ret) { |
593 | dev_err(twl4030_madc->dev, | |
168ae308 | 594 | "unable to write sel register 0x%X\n", method->sel); |
e178ccb3 | 595 | goto out; |
f99c1d4f K |
596 | } |
597 | /* Select averaging for all channels if do_avg is set */ | |
598 | if (req->do_avg) { | |
168ae308 SR |
599 | ret = twl_i2c_write_u16(TWL4030_MODULE_MADC, req->channels, |
600 | method->avg); | |
f99c1d4f K |
601 | if (ret) { |
602 | dev_err(twl4030_madc->dev, | |
603 | "unable to write avg register 0x%X\n", | |
99be0245 | 604 | method->avg); |
e178ccb3 | 605 | goto out; |
f99c1d4f K |
606 | } |
607 | } | |
608 | if (req->type == TWL4030_MADC_IRQ_ONESHOT && req->func_cb != NULL) { | |
609 | ret = twl4030_madc_set_irq(twl4030_madc, req); | |
610 | if (ret < 0) | |
611 | goto out; | |
612 | ret = twl4030_madc_start_conversion(twl4030_madc, req->method); | |
613 | if (ret < 0) | |
614 | goto out; | |
615 | twl4030_madc->requests[req->method].active = 1; | |
616 | ret = 0; | |
617 | goto out; | |
618 | } | |
619 | /* With RT method we should not be here anymore */ | |
620 | if (req->method == TWL4030_MADC_RT) { | |
621 | ret = -EINVAL; | |
622 | goto out; | |
623 | } | |
624 | ret = twl4030_madc_start_conversion(twl4030_madc, req->method); | |
625 | if (ret < 0) | |
626 | goto out; | |
627 | twl4030_madc->requests[req->method].active = 1; | |
628 | /* Wait until conversion is ready (ctrl register returns EOC) */ | |
629 | ret = twl4030_madc_wait_conversion_ready(twl4030_madc, 5, method->ctrl); | |
630 | if (ret) { | |
631 | twl4030_madc->requests[req->method].active = 0; | |
632 | goto out; | |
633 | } | |
634 | ret = twl4030_madc_read_channels(twl4030_madc, method->rbase, | |
a5055d5d | 635 | req->channels, req->rbuf, req->raw); |
f99c1d4f K |
636 | twl4030_madc->requests[req->method].active = 0; |
637 | ||
638 | out: | |
639 | mutex_unlock(&twl4030_madc->lock); | |
640 | ||
641 | return ret; | |
642 | } | |
643 | EXPORT_SYMBOL_GPL(twl4030_madc_conversion); | |
644 | ||
f99c1d4f K |
645 | int twl4030_get_madc_conversion(int channel_no) |
646 | { | |
647 | struct twl4030_madc_request req; | |
648 | int temp = 0; | |
649 | int ret; | |
650 | ||
651 | req.channels = (1 << channel_no); | |
652 | req.method = TWL4030_MADC_SW2; | |
653 | req.active = 0; | |
e0326be0 | 654 | req.raw = 0; |
f99c1d4f K |
655 | req.func_cb = NULL; |
656 | ret = twl4030_madc_conversion(&req); | |
657 | if (ret < 0) | |
658 | return ret; | |
659 | if (req.rbuf[channel_no] > 0) | |
660 | temp = req.rbuf[channel_no]; | |
661 | ||
662 | return temp; | |
663 | } | |
664 | EXPORT_SYMBOL_GPL(twl4030_get_madc_conversion); | |
665 | ||
99be0245 SR |
666 | /** |
667 | * twl4030_madc_set_current_generator() - setup bias current | |
668 | * | |
669 | * @madc: pointer to twl4030_madc_data struct | |
670 | * @chan: can be one of the two values: | |
994bda83 NS |
671 | * 0 - Enables bias current for main battery type reading |
672 | * 1 - Enables bias current for main battery temperature sensing | |
99be0245 SR |
673 | * @on: enable or disable chan. |
674 | * | |
f99c1d4f K |
675 | * Function to enable or disable bias current for |
676 | * main battery type reading or temperature sensing | |
f99c1d4f K |
677 | */ |
678 | static int twl4030_madc_set_current_generator(struct twl4030_madc_data *madc, | |
679 | int chan, int on) | |
680 | { | |
681 | int ret; | |
99be0245 | 682 | int regmask; |
f99c1d4f K |
683 | u8 regval; |
684 | ||
e45342f6 | 685 | ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, |
f99c1d4f K |
686 | ®val, TWL4030_BCI_BCICTL1); |
687 | if (ret) { | |
688 | dev_err(madc->dev, "unable to read BCICTL1 reg 0x%X", | |
689 | TWL4030_BCI_BCICTL1); | |
690 | return ret; | |
691 | } | |
99be0245 SR |
692 | |
693 | regmask = chan ? TWL4030_BCI_ITHEN : TWL4030_BCI_TYPEN; | |
f99c1d4f | 694 | if (on) |
99be0245 | 695 | regval |= regmask; |
f99c1d4f | 696 | else |
99be0245 SR |
697 | regval &= ~regmask; |
698 | ||
e45342f6 | 699 | ret = twl_i2c_write_u8(TWL_MODULE_MAIN_CHARGE, |
f99c1d4f K |
700 | regval, TWL4030_BCI_BCICTL1); |
701 | if (ret) { | |
702 | dev_err(madc->dev, "unable to write BCICTL1 reg 0x%X\n", | |
703 | TWL4030_BCI_BCICTL1); | |
704 | return ret; | |
705 | } | |
706 | ||
707 | return 0; | |
708 | } | |
709 | ||
710 | /* | |
711 | * Function that sets MADC software power on bit to enable MADC | |
712 | * @madc - pointer to twl4030_madc_data struct | |
99be0245 | 713 | * @on - Enable or disable MADC software power on bit. |
f99c1d4f K |
714 | * returns error if i2c read/write fails else 0 |
715 | */ | |
716 | static int twl4030_madc_set_power(struct twl4030_madc_data *madc, int on) | |
717 | { | |
718 | u8 regval; | |
719 | int ret; | |
720 | ||
e45342f6 | 721 | ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, |
f99c1d4f K |
722 | ®val, TWL4030_MADC_CTRL1); |
723 | if (ret) { | |
724 | dev_err(madc->dev, "unable to read madc ctrl1 reg 0x%X\n", | |
725 | TWL4030_MADC_CTRL1); | |
726 | return ret; | |
727 | } | |
728 | if (on) | |
729 | regval |= TWL4030_MADC_MADCON; | |
730 | else | |
731 | regval &= ~TWL4030_MADC_MADCON; | |
732 | ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, regval, TWL4030_MADC_CTRL1); | |
733 | if (ret) { | |
734 | dev_err(madc->dev, "unable to write madc ctrl1 reg 0x%X\n", | |
735 | TWL4030_MADC_CTRL1); | |
736 | return ret; | |
737 | } | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
742 | /* | |
743 | * Initialize MADC and request for threaded irq | |
744 | */ | |
f791be49 | 745 | static int twl4030_madc_probe(struct platform_device *pdev) |
f99c1d4f K |
746 | { |
747 | struct twl4030_madc_data *madc; | |
334a41ce | 748 | struct twl4030_madc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
2f39b70f | 749 | struct device_node *np = pdev->dev.of_node; |
e7f22b75 | 750 | int irq, ret; |
f99c1d4f | 751 | u8 regval; |
2f39b70f | 752 | struct iio_dev *iio_dev = NULL; |
f99c1d4f | 753 | |
2f39b70f SR |
754 | if (!pdata && !np) { |
755 | dev_err(&pdev->dev, "neither platform data nor Device Tree node available\n"); | |
f99c1d4f K |
756 | return -EINVAL; |
757 | } | |
2f39b70f SR |
758 | |
759 | iio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*madc)); | |
760 | if (!iio_dev) { | |
761 | dev_err(&pdev->dev, "failed allocating iio device\n"); | |
f99c1d4f | 762 | return -ENOMEM; |
2f39b70f | 763 | } |
f99c1d4f | 764 | |
2f39b70f | 765 | madc = iio_priv(iio_dev); |
66cc5b8e KM |
766 | madc->dev = &pdev->dev; |
767 | ||
2f39b70f SR |
768 | iio_dev->name = dev_name(&pdev->dev); |
769 | iio_dev->dev.parent = &pdev->dev; | |
770 | iio_dev->dev.of_node = pdev->dev.of_node; | |
771 | iio_dev->info = &twl4030_madc_iio_info; | |
772 | iio_dev->modes = INDIO_DIRECT_MODE; | |
773 | iio_dev->channels = twl4030_madc_iio_channels; | |
774 | iio_dev->num_channels = ARRAY_SIZE(twl4030_madc_iio_channels); | |
775 | ||
f99c1d4f K |
776 | /* |
777 | * Phoenix provides 2 interrupt lines. The first one is connected to | |
778 | * the OMAP. The other one can be connected to the other processor such | |
779 | * as modem. Hence two separate ISR and IMR registers. | |
780 | */ | |
2f39b70f SR |
781 | if (pdata) |
782 | madc->use_second_irq = (pdata->irq_line != 1); | |
783 | else | |
784 | madc->use_second_irq = of_property_read_bool(np, | |
785 | "ti,system-uses-second-madc-irq"); | |
786 | ||
787 | madc->imr = madc->use_second_irq ? TWL4030_MADC_IMR2 : | |
788 | TWL4030_MADC_IMR1; | |
789 | madc->isr = madc->use_second_irq ? TWL4030_MADC_ISR2 : | |
790 | TWL4030_MADC_ISR1; | |
791 | ||
f99c1d4f K |
792 | ret = twl4030_madc_set_power(madc, 1); |
793 | if (ret < 0) | |
e7f22b75 | 794 | return ret; |
f99c1d4f K |
795 | ret = twl4030_madc_set_current_generator(madc, 0, 1); |
796 | if (ret < 0) | |
797 | goto err_current_generator; | |
798 | ||
e45342f6 | 799 | ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, |
f99c1d4f K |
800 | ®val, TWL4030_BCI_BCICTL1); |
801 | if (ret) { | |
802 | dev_err(&pdev->dev, "unable to read reg BCI CTL1 0x%X\n", | |
803 | TWL4030_BCI_BCICTL1); | |
804 | goto err_i2c; | |
805 | } | |
806 | regval |= TWL4030_BCI_MESBAT; | |
e45342f6 | 807 | ret = twl_i2c_write_u8(TWL_MODULE_MAIN_CHARGE, |
f99c1d4f K |
808 | regval, TWL4030_BCI_BCICTL1); |
809 | if (ret) { | |
810 | dev_err(&pdev->dev, "unable to write reg BCI Ctl1 0x%X\n", | |
811 | TWL4030_BCI_BCICTL1); | |
812 | goto err_i2c; | |
813 | } | |
3d6271f9 KM |
814 | |
815 | /* Check that MADC clock is on */ | |
816 | ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, ®val, TWL4030_REG_GPBR1); | |
817 | if (ret) { | |
818 | dev_err(&pdev->dev, "unable to read reg GPBR1 0x%X\n", | |
819 | TWL4030_REG_GPBR1); | |
820 | goto err_i2c; | |
821 | } | |
822 | ||
823 | /* If MADC clk is not on, turn it on */ | |
824 | if (!(regval & TWL4030_GPBR1_MADC_HFCLK_EN)) { | |
825 | dev_info(&pdev->dev, "clk disabled, enabling\n"); | |
826 | regval |= TWL4030_GPBR1_MADC_HFCLK_EN; | |
827 | ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, regval, | |
828 | TWL4030_REG_GPBR1); | |
829 | if (ret) { | |
830 | dev_err(&pdev->dev, "unable to write reg GPBR1 0x%X\n", | |
831 | TWL4030_REG_GPBR1); | |
832 | goto err_i2c; | |
833 | } | |
834 | } | |
835 | ||
2f39b70f | 836 | platform_set_drvdata(pdev, iio_dev); |
f99c1d4f | 837 | mutex_init(&madc->lock); |
e7f22b75 SR |
838 | |
839 | irq = platform_get_irq(pdev, 0); | |
840 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
f99c1d4f | 841 | twl4030_madc_threaded_irq_handler, |
6c0d48cb FE |
842 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, |
843 | "twl4030_madc", madc); | |
f99c1d4f | 844 | if (ret) { |
2f39b70f | 845 | dev_err(&pdev->dev, "could not request irq\n"); |
c3d6a0a3 | 846 | goto err_i2c; |
f99c1d4f K |
847 | } |
848 | twl4030_madc = madc; | |
2f39b70f | 849 | |
7cc97d77 AYL |
850 | /* Configure MADC[3:6] */ |
851 | ret = twl_i2c_read_u8(TWL_MODULE_USB, ®val, | |
852 | TWL4030_USB_CARKIT_ANA_CTRL); | |
853 | if (ret) { | |
854 | dev_err(&pdev->dev, "unable to read reg CARKIT_ANA_CTRL 0x%X\n", | |
855 | TWL4030_USB_CARKIT_ANA_CTRL); | |
856 | goto err_i2c; | |
857 | } | |
858 | regval |= TWL4030_USB_SEL_MADC_MCPC; | |
859 | ret = twl_i2c_write_u8(TWL_MODULE_USB, regval, | |
860 | TWL4030_USB_CARKIT_ANA_CTRL); | |
861 | if (ret) { | |
862 | dev_err(&pdev->dev, "unable to write reg CARKIT_ANA_CTRL 0x%X\n", | |
863 | TWL4030_USB_CARKIT_ANA_CTRL); | |
864 | goto err_i2c; | |
865 | } | |
866 | ||
867 | /* Enable 3v1 bias regulator for MADC[3:6] */ | |
868 | madc->usb3v1 = devm_regulator_get(madc->dev, "vusb3v1"); | |
869 | if (IS_ERR(madc->usb3v1)) | |
870 | return -ENODEV; | |
871 | ||
872 | ret = regulator_enable(madc->usb3v1); | |
873 | if (ret) | |
874 | dev_err(madc->dev, "could not enable 3v1 bias regulator\n"); | |
875 | ||
2f39b70f SR |
876 | ret = iio_device_register(iio_dev); |
877 | if (ret) { | |
878 | dev_err(&pdev->dev, "could not register iio device\n"); | |
879 | goto err_i2c; | |
880 | } | |
881 | ||
f99c1d4f | 882 | return 0; |
2f39b70f | 883 | |
f99c1d4f K |
884 | err_i2c: |
885 | twl4030_madc_set_current_generator(madc, 0, 0); | |
886 | err_current_generator: | |
887 | twl4030_madc_set_power(madc, 0); | |
f99c1d4f K |
888 | return ret; |
889 | } | |
890 | ||
4740f73f | 891 | static int twl4030_madc_remove(struct platform_device *pdev) |
f99c1d4f | 892 | { |
2f39b70f SR |
893 | struct iio_dev *iio_dev = platform_get_drvdata(pdev); |
894 | struct twl4030_madc_data *madc = iio_priv(iio_dev); | |
895 | ||
896 | iio_device_unregister(iio_dev); | |
f99c1d4f | 897 | |
f99c1d4f K |
898 | twl4030_madc_set_current_generator(madc, 0, 0); |
899 | twl4030_madc_set_power(madc, 0); | |
f99c1d4f | 900 | |
7cc97d77 AYL |
901 | regulator_disable(madc->usb3v1); |
902 | ||
f99c1d4f K |
903 | return 0; |
904 | } | |
905 | ||
2f39b70f SR |
906 | #ifdef CONFIG_OF |
907 | static const struct of_device_id twl_madc_of_match[] = { | |
908 | { .compatible = "ti,twl4030-madc", }, | |
909 | { }, | |
910 | }; | |
911 | MODULE_DEVICE_TABLE(of, twl_madc_of_match); | |
912 | #endif | |
913 | ||
f99c1d4f K |
914 | static struct platform_driver twl4030_madc_driver = { |
915 | .probe = twl4030_madc_probe, | |
03715410 | 916 | .remove = twl4030_madc_remove, |
f99c1d4f K |
917 | .driver = { |
918 | .name = "twl4030_madc", | |
2f39b70f | 919 | .of_match_table = of_match_ptr(twl_madc_of_match), |
99be0245 | 920 | }, |
f99c1d4f K |
921 | }; |
922 | ||
65349d60 | 923 | module_platform_driver(twl4030_madc_driver); |
f99c1d4f K |
924 | |
925 | MODULE_DESCRIPTION("TWL4030 ADC driver"); | |
926 | MODULE_LICENSE("GPL"); | |
927 | MODULE_AUTHOR("J Keerthy"); | |
0ea3e83b | 928 | MODULE_ALIAS("platform:twl4030_madc"); |