[mirror_ubuntu-artful-kernel.git] / drivers / iio / adc / vf610_adc.c

/*
 * Freescale Vybrid vf610 ADC driver
 *
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/regulator/consumer.h>
#include <linux/of_platform.h>
#include <linux/err.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/driver.h>

/* This will be the driver name the kernel reports */
#define DRIVER_NAME "vf610-adc"

/* Vybrid/IMX ADC registers */
#define VF610_REG_ADC_HC0		0x00
#define VF610_REG_ADC_HC1		0x04
#define VF610_REG_ADC_HS		0x08
#define VF610_REG_ADC_R0		0x0c
#define VF610_REG_ADC_R1		0x10
#define VF610_REG_ADC_CFG		0x14
#define VF610_REG_ADC_GC		0x18
#define VF610_REG_ADC_GS		0x1c
#define VF610_REG_ADC_CV		0x20
#define VF610_REG_ADC_OFS		0x24
#define VF610_REG_ADC_CAL		0x28
#define VF610_REG_ADC_PCTL		0x30

/* Configuration register field define */
#define VF610_ADC_MODE_BIT8		0x00
#define VF610_ADC_MODE_BIT10		0x04
#define VF610_ADC_MODE_BIT12		0x08
#define VF610_ADC_MODE_MASK		0x0c
#define VF610_ADC_BUSCLK2_SEL		0x01
#define VF610_ADC_ALTCLK_SEL		0x02
#define VF610_ADC_ADACK_SEL		0x03
#define VF610_ADC_ADCCLK_MASK		0x03
#define VF610_ADC_CLK_DIV2		0x20
#define VF610_ADC_CLK_DIV4		0x40
#define VF610_ADC_CLK_DIV8		0x60
#define VF610_ADC_CLK_MASK		0x60
#define VF610_ADC_ADLSMP_LONG		0x10
#define VF610_ADC_ADSTS_MASK		0x300
#define VF610_ADC_ADLPC_EN		0x80
#define VF610_ADC_ADHSC_EN		0x400
#define VF610_ADC_REFSEL_VALT		0x100
#define VF610_ADC_REFSEL_VBG		0x1000
#define VF610_ADC_ADTRG_HARD		0x2000
#define VF610_ADC_AVGS_8		0x4000
#define VF610_ADC_AVGS_16		0x8000
#define VF610_ADC_AVGS_32		0xC000
#define VF610_ADC_AVGS_MASK		0xC000
#define VF610_ADC_OVWREN		0x10000

/* General control register field define */
#define VF610_ADC_ADACKEN		0x1
#define VF610_ADC_DMAEN			0x2
#define VF610_ADC_ACREN			0x4
#define VF610_ADC_ACFGT			0x8
#define VF610_ADC_ACFE			0x10
#define VF610_ADC_AVGEN			0x20
#define VF610_ADC_ADCON			0x40
#define VF610_ADC_CAL			0x80

/* Other field define */
#define VF610_ADC_ADCHC(x)		((x) & 0x1F)
#define VF610_ADC_AIEN			(0x1 << 7)
#define VF610_ADC_CONV_DISABLE		0x1F
#define VF610_ADC_HS_COCO0		0x1
#define VF610_ADC_CALF			0x2
#define VF610_ADC_TIMEOUT		msecs_to_jiffies(100)

enum clk_sel {
	VF610_ADCIOC_BUSCLK_SET,
	VF610_ADCIOC_ALTCLK_SET,
	VF610_ADCIOC_ADACK_SET,
};

enum vol_ref {
	VF610_ADCIOC_VR_VREF_SET,
	VF610_ADCIOC_VR_VALT_SET,
	VF610_ADCIOC_VR_VBG_SET,
};

enum average_sel {
	VF610_ADC_SAMPLE_1,
	VF610_ADC_SAMPLE_4,
	VF610_ADC_SAMPLE_8,
	VF610_ADC_SAMPLE_16,
	VF610_ADC_SAMPLE_32,
};

struct vf610_adc_feature {
	enum clk_sel	clk_sel;
	enum vol_ref	vol_ref;

	int	clk_div;
	int     sample_rate;
	int	res_mode;

	bool	lpm;
	bool	calibration;
	bool	ovwren;
};

struct vf610_adc {
	struct device *dev;
	void __iomem *regs;
	struct clk *clk;

	u32 vref_uv;
	u32 value;
	struct regulator *vref;
	struct vf610_adc_feature adc_feature;

	u32 sample_freq_avail[5];

	struct completion completion;
};

static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };

#define VF610_ADC_CHAN(_idx, _chan_type) {			\
	.type = (_chan_type),					\
	.indexed = 1,						\
	.channel = (_idx),					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
}

#define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) {	\
	.type = (_chan_type),	\
	.channel = (_idx),		\
	.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),	\
}

static const struct iio_chan_spec vf610_adc_iio_channels[] = {
	VF610_ADC_CHAN(0, IIO_VOLTAGE),
	VF610_ADC_CHAN(1, IIO_VOLTAGE),
	VF610_ADC_CHAN(2, IIO_VOLTAGE),
	VF610_ADC_CHAN(3, IIO_VOLTAGE),
	VF610_ADC_CHAN(4, IIO_VOLTAGE),
	VF610_ADC_CHAN(5, IIO_VOLTAGE),
	VF610_ADC_CHAN(6, IIO_VOLTAGE),
	VF610_ADC_CHAN(7, IIO_VOLTAGE),
	VF610_ADC_CHAN(8, IIO_VOLTAGE),
	VF610_ADC_CHAN(9, IIO_VOLTAGE),
	VF610_ADC_CHAN(10, IIO_VOLTAGE),
	VF610_ADC_CHAN(11, IIO_VOLTAGE),
	VF610_ADC_CHAN(12, IIO_VOLTAGE),
	VF610_ADC_CHAN(13, IIO_VOLTAGE),
	VF610_ADC_CHAN(14, IIO_VOLTAGE),
	VF610_ADC_CHAN(15, IIO_VOLTAGE),
	VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
	/* sentinel */
};

static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
{
	unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
	int i;

	/*
	 * Calculate ADC sample frequencies
	 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
	 * which is the same as bus clock.
	 *
	 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
	 * SFCAdder: fixed to 6 ADCK cycles
	 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
	 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
	 * LSTAdder(Long Sample Time): fixed to 3 ADCK cycles
	 */
	adck_rate = ipg_rate / info->adc_feature.clk_div;
	for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
		info->sample_freq_avail[i] =
			adck_rate / (6 + vf610_hw_avgs[i] * (25 + 3));
}

static inline void vf610_adc_cfg_init(struct vf610_adc *info)
{
	struct vf610_adc_feature *adc_feature = &info->adc_feature;

	/* set default Configuration for ADC controller */
	adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
	adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;

	adc_feature->calibration = true;
	adc_feature->ovwren = true;

	adc_feature->res_mode = 12;
	adc_feature->sample_rate = 1;
	adc_feature->lpm = true;

	/* Use a save ADCK which is below 20MHz on all devices */
	adc_feature->clk_div = 8;

	vf610_adc_calculate_rates(info);
}

static void vf610_adc_cfg_post_set(struct vf610_adc *info)
{
	struct vf610_adc_feature *adc_feature = &info->adc_feature;
	int cfg_data = 0;
	int gc_data = 0;

	switch (adc_feature->clk_sel) {
	case VF610_ADCIOC_ALTCLK_SET:
		cfg_data |= VF610_ADC_ALTCLK_SEL;
		break;
	case VF610_ADCIOC_ADACK_SET:
		cfg_data |= VF610_ADC_ADACK_SEL;
		break;
	default:
		break;
	}

	/* low power set for calibration */
	cfg_data |= VF610_ADC_ADLPC_EN;

	/* enable high speed for calibration */
	cfg_data |= VF610_ADC_ADHSC_EN;

	/* voltage reference */
	switch (adc_feature->vol_ref) {
	case VF610_ADCIOC_VR_VREF_SET:
		break;
	case VF610_ADCIOC_VR_VALT_SET:
		cfg_data |= VF610_ADC_REFSEL_VALT;
		break;
	case VF610_ADCIOC_VR_VBG_SET:
		cfg_data |= VF610_ADC_REFSEL_VBG;
		break;
	default:
		dev_err(info->dev, "error voltage reference\n");
	}

	/* data overwrite enable */
	if (adc_feature->ovwren)
		cfg_data |= VF610_ADC_OVWREN;

	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
	writel(gc_data, info->regs + VF610_REG_ADC_GC);
}

static void vf610_adc_calibration(struct vf610_adc *info)
{
	int adc_gc, hc_cfg;

	if (!info->adc_feature.calibration)
		return;

	/* enable calibration interrupt */
	hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
	writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);

	adc_gc = readl(info->regs + VF610_REG_ADC_GC);
	writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);

	if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
		dev_err(info->dev, "Timeout for adc calibration\n");

	adc_gc = readl(info->regs + VF610_REG_ADC_GS);
	if (adc_gc & VF610_ADC_CALF)
		dev_err(info->dev, "ADC calibration failed\n");

	info->adc_feature.calibration = false;
}

static void vf610_adc_cfg_set(struct vf610_adc *info)
{
	struct vf610_adc_feature *adc_feature = &(info->adc_feature);
	int cfg_data;

	cfg_data = readl(info->regs + VF610_REG_ADC_CFG);

	cfg_data &= ~VF610_ADC_ADLPC_EN;
	if (adc_feature->lpm)
		cfg_data |= VF610_ADC_ADLPC_EN;

	cfg_data &= ~VF610_ADC_ADHSC_EN;

	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
}

static void vf610_adc_sample_set(struct vf610_adc *info)
{
	struct vf610_adc_feature *adc_feature = &(info->adc_feature);
	int cfg_data, gc_data;

	cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
	gc_data = readl(info->regs + VF610_REG_ADC_GC);

	/* resolution mode */
	cfg_data &= ~VF610_ADC_MODE_MASK;
	switch (adc_feature->res_mode) {
	case 8:
		cfg_data |= VF610_ADC_MODE_BIT8;
		break;
	case 10:
		cfg_data |= VF610_ADC_MODE_BIT10;
		break;
	case 12:
		cfg_data |= VF610_ADC_MODE_BIT12;
		break;
	default:
		dev_err(info->dev, "error resolution mode\n");
		break;
	}

	/* clock select and clock divider */
	cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
	switch (adc_feature->clk_div) {
	case 1:
		break;
	case 2:
		cfg_data |= VF610_ADC_CLK_DIV2;
		break;
	case 4:
		cfg_data |= VF610_ADC_CLK_DIV4;
		break;
	case 8:
		cfg_data |= VF610_ADC_CLK_DIV8;
		break;
	case 16:
		switch (adc_feature->clk_sel) {
		case VF610_ADCIOC_BUSCLK_SET:
			cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
			break;
		default:
			dev_err(info->dev, "error clk divider\n");
			break;
		}
		break;
	}

	/* Use the short sample mode */
	cfg_data &= ~(VF610_ADC_ADLSMP_LONG | VF610_ADC_ADSTS_MASK);

	/* update hardware average selection */
	cfg_data &= ~VF610_ADC_AVGS_MASK;
	gc_data &= ~VF610_ADC_AVGEN;
	switch (adc_feature->sample_rate) {
	case VF610_ADC_SAMPLE_1:
		break;
	case VF610_ADC_SAMPLE_4:
		gc_data |= VF610_ADC_AVGEN;
		break;
	case VF610_ADC_SAMPLE_8:
		gc_data |= VF610_ADC_AVGEN;
		cfg_data |= VF610_ADC_AVGS_8;
		break;
	case VF610_ADC_SAMPLE_16:
		gc_data |= VF610_ADC_AVGEN;
		cfg_data |= VF610_ADC_AVGS_16;
		break;
	case VF610_ADC_SAMPLE_32:
		gc_data |= VF610_ADC_AVGEN;
		cfg_data |= VF610_ADC_AVGS_32;
		break;
	default:
		dev_err(info->dev,
			"error hardware sample average select\n");
	}

	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
	writel(gc_data, info->regs + VF610_REG_ADC_GC);
}

static void vf610_adc_hw_init(struct vf610_adc *info)
{
	/* CFG: Feature set */
	vf610_adc_cfg_post_set(info);
	vf610_adc_sample_set(info);

	/* adc calibration */
	vf610_adc_calibration(info);

	/* CFG: power and speed set */
	vf610_adc_cfg_set(info);
}

static int vf610_adc_read_data(struct vf610_adc *info)
{
	int result;

	result = readl(info->regs + VF610_REG_ADC_R0);

	switch (info->adc_feature.res_mode) {
	case 8:
		result &= 0xFF;
		break;
	case 10:
		result &= 0x3FF;
		break;
	case 12:
		result &= 0xFFF;
		break;
	default:
		break;
	}

	return result;
}

static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
{
	struct vf610_adc *info = (struct vf610_adc *)dev_id;
	int coco;

	coco = readl(info->regs + VF610_REG_ADC_HS);
	if (coco & VF610_ADC_HS_COCO0) {
		info->value = vf610_adc_read_data(info);
		complete(&info->completion);
	}

	return IRQ_HANDLED;
}

static ssize_t vf610_show_samp_freq_avail(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
	size_t len = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
		len += scnprintf(buf + len, PAGE_SIZE - len,
			"%u ", info->sample_freq_avail[i]);

	/* replace trailing space by newline */
	buf[len - 1] = '\n';

	return len;
}

static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);

static struct attribute *vf610_attributes[] = {
	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
	NULL
};

static const struct attribute_group vf610_attribute_group = {
	.attrs = vf610_attributes,
};

static int vf610_read_raw(struct iio_dev *indio_dev,
			struct iio_chan_spec const *chan,
			int *val,
			int *val2,
			long mask)
{
	struct vf610_adc *info = iio_priv(indio_dev);
	unsigned int hc_cfg;
	long ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
	case IIO_CHAN_INFO_PROCESSED:
		mutex_lock(&indio_dev->mlock);
		reinit_completion(&info->completion);

		hc_cfg = VF610_ADC_ADCHC(chan->channel);
		hc_cfg |= VF610_ADC_AIEN;
		writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
		ret = wait_for_completion_interruptible_timeout
				(&info->completion, VF610_ADC_TIMEOUT);
		if (ret == 0) {
			mutex_unlock(&indio_dev->mlock);
			return -ETIMEDOUT;
		}
		if (ret < 0) {
			mutex_unlock(&indio_dev->mlock);
			return ret;
		}

		switch (chan->type) {
		case IIO_VOLTAGE:
			*val = info->value;
			break;
		case IIO_TEMP:
			/*
			* Calculate in degree Celsius times 1000
			* Using sensor slope of 1.84 mV/°C and
			* V at 25°C of 696 mV
			*/
			*val = 25000 - ((int)info->value - 864) * 1000000 / 1840;
			break;
		default:
			mutex_unlock(&indio_dev->mlock);
			return -EINVAL;
		}

		mutex_unlock(&indio_dev->mlock);
		return IIO_VAL_INT;

	case IIO_CHAN_INFO_SCALE:
		*val = info->vref_uv / 1000;
		*val2 = info->adc_feature.res_mode;
		return IIO_VAL_FRACTIONAL_LOG2;

	case IIO_CHAN_INFO_SAMP_FREQ:
		*val = info->sample_freq_avail[info->adc_feature.sample_rate];
		*val2 = 0;
		return IIO_VAL_INT;

	default:
		break;
	}

	return -EINVAL;
}

static int vf610_write_raw(struct iio_dev *indio_dev,
			struct iio_chan_spec const *chan,
			int val,
			int val2,
			long mask)
{
	struct vf610_adc *info = iio_priv(indio_dev);
	int i;

	switch (mask) {
		case IIO_CHAN_INFO_SAMP_FREQ:
			for (i = 0;
				i < ARRAY_SIZE(info->sample_freq_avail);
				i++)
				if (val == info->sample_freq_avail[i]) {
					info->adc_feature.sample_rate = i;
					vf610_adc_sample_set(info);
					return 0;
				}
			break;

		default:
			break;
	}

	return -EINVAL;
}

static int vf610_adc_reg_access(struct iio_dev *indio_dev,
			unsigned reg, unsigned writeval,
			unsigned *readval)
{
	struct vf610_adc *info = iio_priv(indio_dev);

	if ((readval == NULL) ||
		(!(reg % 4) || (reg > VF610_REG_ADC_PCTL)))
		return -EINVAL;

	*readval = readl(info->regs + reg);

	return 0;
}

static const struct iio_info vf610_adc_iio_info = {
	.driver_module = THIS_MODULE,
	.read_raw = &vf610_read_raw,
	.write_raw = &vf610_write_raw,
	.debugfs_reg_access = &vf610_adc_reg_access,
	.attrs = &vf610_attribute_group,
};

static const struct of_device_id vf610_adc_match[] = {
	{ .compatible = "fsl,vf610-adc", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, vf610_adc_match);

static int vf610_adc_probe(struct platform_device *pdev)
{
	struct vf610_adc *info;
	struct iio_dev *indio_dev;
	struct resource *mem;
	int irq;
	int ret;

	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
	if (!indio_dev) {
		dev_err(&pdev->dev, "Failed allocating iio device\n");
		return -ENOMEM;
	}

	info = iio_priv(indio_dev);
	info->dev = &pdev->dev;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	info->regs = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(info->regs))
		return PTR_ERR(info->regs);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "no irq resource?\n");
		return irq;
	}

	ret = devm_request_irq(info->dev, irq,
				vf610_adc_isr, 0,
				dev_name(&pdev->dev), info);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
		return ret;
	}

	info->clk = devm_clk_get(&pdev->dev, "adc");
	if (IS_ERR(info->clk)) {
		dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
						PTR_ERR(info->clk));
		return PTR_ERR(info->clk);
	}

	info->vref = devm_regulator_get(&pdev->dev, "vref");
	if (IS_ERR(info->vref))
		return PTR_ERR(info->vref);

	ret = regulator_enable(info->vref);
	if (ret)
		return ret;

	info->vref_uv = regulator_get_voltage(info->vref);

	platform_set_drvdata(pdev, indio_dev);

	init_completion(&info->completion);

	indio_dev->name = dev_name(&pdev->dev);
	indio_dev->dev.parent = &pdev->dev;
	indio_dev->dev.of_node = pdev->dev.of_node;
	indio_dev->info = &vf610_adc_iio_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = vf610_adc_iio_channels;
	indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);

	ret = clk_prepare_enable(info->clk);
	if (ret) {
		dev_err(&pdev->dev,
			"Could not prepare or enable the clock.\n");
		goto error_adc_clk_enable;
	}

	vf610_adc_cfg_init(info);
	vf610_adc_hw_init(info);

	ret = iio_device_register(indio_dev);
	if (ret) {
		dev_err(&pdev->dev, "Couldn't register the device.\n");
		goto error_iio_device_register;
	}

	return 0;


error_iio_device_register:
	clk_disable_unprepare(info->clk);
error_adc_clk_enable:
	regulator_disable(info->vref);

	return ret;
}

static int vf610_adc_remove(struct platform_device *pdev)
{
	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
	struct vf610_adc *info = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	regulator_disable(info->vref);
	clk_disable_unprepare(info->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int vf610_adc_suspend(struct device *dev)
{
	struct iio_dev *indio_dev = dev_get_drvdata(dev);
	struct vf610_adc *info = iio_priv(indio_dev);
	int hc_cfg;

	/* ADC controller enters to stop mode */
	hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
	hc_cfg |= VF610_ADC_CONV_DISABLE;
	writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);

	clk_disable_unprepare(info->clk);
	regulator_disable(info->vref);

	return 0;
}

static int vf610_adc_resume(struct device *dev)
{
	struct iio_dev *indio_dev = dev_get_drvdata(dev);
	struct vf610_adc *info = iio_priv(indio_dev);
	int ret;

	ret = regulator_enable(info->vref);
	if (ret)
		return ret;

	ret = clk_prepare_enable(info->clk);
	if (ret)
		goto disable_reg;

	vf610_adc_hw_init(info);

	return 0;

disable_reg:
	regulator_disable(info->vref);
	return ret;
}
#endif

static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);

static struct platform_driver vf610_adc_driver = {
	.probe          = vf610_adc_probe,
	.remove         = vf610_adc_remove,
	.driver         = {
		.name   = DRIVER_NAME,
		.of_match_table = vf610_adc_match,
		.pm     = &vf610_adc_pm_ops,
	},
};

module_platform_driver(vf610_adc_driver);

MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
MODULE_DESCRIPTION("Freescale VF610 ADC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a7754276 FD	1	/*
	2	* Freescale Vybrid vf610 ADC driver
	3	*
	4	* Copyright 2013 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/delay.h>
	25	#include <linux/kernel.h>
	26	#include <linux/slab.h>
	27	#include <linux/io.h>
	28	#include <linux/clk.h>
	29	#include <linux/completion.h>
	30	#include <linux/of.h>
	31	#include <linux/of_irq.h>
	32	#include <linux/regulator/consumer.h>
	33	#include <linux/of_platform.h>
	34	#include <linux/err.h>
	35
	36	#include <linux/iio/iio.h>
	37	#include <linux/iio/sysfs.h>
	38	#include <linux/iio/driver.h>
	39
	40	/* This will be the driver name the kernel reports */
	41	#define DRIVER_NAME "vf610-adc"
	42
	43	/* Vybrid/IMX ADC registers */
	44	#define VF610_REG_ADC_HC0 0x00
	45	#define VF610_REG_ADC_HC1 0x04
	46	#define VF610_REG_ADC_HS 0x08
	47	#define VF610_REG_ADC_R0 0x0c
	48	#define VF610_REG_ADC_R1 0x10
	49	#define VF610_REG_ADC_CFG 0x14
	50	#define VF610_REG_ADC_GC 0x18
	51	#define VF610_REG_ADC_GS 0x1c
	52	#define VF610_REG_ADC_CV 0x20
	53	#define VF610_REG_ADC_OFS 0x24
	54	#define VF610_REG_ADC_CAL 0x28
	55	#define VF610_REG_ADC_PCTL 0x30
	56
	57	/* Configuration register field define */
	58	#define VF610_ADC_MODE_BIT8 0x00
	59	#define VF610_ADC_MODE_BIT10 0x04
	60	#define VF610_ADC_MODE_BIT12 0x08
	61	#define VF610_ADC_MODE_MASK 0x0c
	62	#define VF610_ADC_BUSCLK2_SEL 0x01
	63	#define VF610_ADC_ALTCLK_SEL 0x02
	64	#define VF610_ADC_ADACK_SEL 0x03
65	#define VF610_ADC_ADCCLK_MASK 0x03
66	#define VF610_ADC_CLK_DIV2 0x20
67	#define VF610_ADC_CLK_DIV4 0x40
68	#define VF610_ADC_CLK_DIV8 0x60
69	#define VF610_ADC_CLK_MASK 0x60
70	#define VF610_ADC_ADLSMP_LONG 0x10
71	#define VF610_ADC_ADSTS_MASK 0x300
72	#define VF610_ADC_ADLPC_EN 0x80
73	#define VF610_ADC_ADHSC_EN 0x400
74	#define VF610_ADC_REFSEL_VALT 0x100
75	#define VF610_ADC_REFSEL_VBG 0x1000
76	#define VF610_ADC_ADTRG_HARD 0x2000
77	#define VF610_ADC_AVGS_8 0x4000
78	#define VF610_ADC_AVGS_16 0x8000
79	#define VF610_ADC_AVGS_32 0xC000
80	#define VF610_ADC_AVGS_MASK 0xC000
81	#define VF610_ADC_OVWREN 0x10000
82
83	/* General control register field define */
84	#define VF610_ADC_ADACKEN 0x1
85	#define VF610_ADC_DMAEN 0x2
86	#define VF610_ADC_ACREN 0x4
87	#define VF610_ADC_ACFGT 0x8
88	#define VF610_ADC_ACFE 0x10
89	#define VF610_ADC_AVGEN 0x20
90	#define VF610_ADC_ADCON 0x40
91	#define VF610_ADC_CAL 0x80
92
93	/* Other field define */
774623ca	94	#define VF610_ADC_ADCHC(x) ((x) & 0x1F)
a7754276 FD	95	#define VF610_ADC_AIEN (0x1 << 7)
	96	#define VF610_ADC_CONV_DISABLE 0x1F
	97	#define VF610_ADC_HS_COCO0 0x1
	98	#define VF610_ADC_CALF 0x2
	99	#define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
	100
	101	enum clk_sel {
	102	VF610_ADCIOC_BUSCLK_SET,
	103	VF610_ADCIOC_ALTCLK_SET,
	104	VF610_ADCIOC_ADACK_SET,
	105	};
	106
	107	enum vol_ref {
	108	VF610_ADCIOC_VR_VREF_SET,
	109	VF610_ADCIOC_VR_VALT_SET,
	110	VF610_ADCIOC_VR_VBG_SET,
	111	};
	112
	113	enum average_sel {
	114	VF610_ADC_SAMPLE_1,
	115	VF610_ADC_SAMPLE_4,
	116	VF610_ADC_SAMPLE_8,
	117	VF610_ADC_SAMPLE_16,
	118	VF610_ADC_SAMPLE_32,
	119	};
	120
	121	struct vf610_adc_feature {
	122	enum clk_sel clk_sel;
	123	enum vol_ref vol_ref;
	124
	125	int clk_div;
	126	int sample_rate;
	127	int res_mode;
	128
	129	bool lpm;
	130	bool calibration;
	131	bool ovwren;
	132	};
	133
	134	struct vf610_adc {
	135	struct device *dev;
	136	void __iomem *regs;
	137	struct clk *clk;
	138
	139	u32 vref_uv;
	140	u32 value;
	141	struct regulator *vref;
	142	struct vf610_adc_feature adc_feature;
	143
f54e9f2b SA	144	u32 sample_freq_avail[5];
f54e9f2b SA	145
a7754276 FD	146	struct completion completion;
	147	};
	148
f54e9f2b SA	149	static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
f54e9f2b SA	150
a7754276 FD	151	#define VF610_ADC_CHAN(_idx, _chan_type) { \
	152	.type = (_chan_type), \
	153	.indexed = 1, \
	154	.channel = (_idx), \
	155	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
	156	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \| \
	157	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	158	}
	159
774623ca SM	160	#define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
	161	.type = (_chan_type), \
	162	.channel = (_idx), \
	163	.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
	164	}
	165
a7754276 FD	166	static const struct iio_chan_spec vf610_adc_iio_channels[] = {
	167	VF610_ADC_CHAN(0, IIO_VOLTAGE),
	168	VF610_ADC_CHAN(1, IIO_VOLTAGE),
	169	VF610_ADC_CHAN(2, IIO_VOLTAGE),
	170	VF610_ADC_CHAN(3, IIO_VOLTAGE),
	171	VF610_ADC_CHAN(4, IIO_VOLTAGE),
	172	VF610_ADC_CHAN(5, IIO_VOLTAGE),
	173	VF610_ADC_CHAN(6, IIO_VOLTAGE),
	174	VF610_ADC_CHAN(7, IIO_VOLTAGE),
	175	VF610_ADC_CHAN(8, IIO_VOLTAGE),
	176	VF610_ADC_CHAN(9, IIO_VOLTAGE),
	177	VF610_ADC_CHAN(10, IIO_VOLTAGE),
	178	VF610_ADC_CHAN(11, IIO_VOLTAGE),
	179	VF610_ADC_CHAN(12, IIO_VOLTAGE),
	180	VF610_ADC_CHAN(13, IIO_VOLTAGE),
	181	VF610_ADC_CHAN(14, IIO_VOLTAGE),
	182	VF610_ADC_CHAN(15, IIO_VOLTAGE),
774623ca	183	VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
a7754276 FD	184	/* sentinel */
	185	};
	186
f54e9f2b SA	187	static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
	188	{
	189	unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
	190	int i;
	191
	192	/*
	193	* Calculate ADC sample frequencies
	194	* Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
	195	* which is the same as bus clock.
	196	*
	197	* ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
	198	* SFCAdder: fixed to 6 ADCK cycles
	199	* AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
	200	* BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
	201	* LSTAdder(Long Sample Time): fixed to 3 ADCK cycles
	202	*/
	203	adck_rate = ipg_rate / info->adc_feature.clk_div;
	204	for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
	205	info->sample_freq_avail[i] =
	206	adck_rate / (6 + vf610_hw_avgs[i] * (25 + 3));
	207	}
a7754276 FD	208
	209	static inline void vf610_adc_cfg_init(struct vf610_adc *info)
	210	{
f54e9f2b SA	211	struct vf610_adc_feature *adc_feature = &info->adc_feature;
f54e9f2b SA	212
a7754276	213	/* set default Configuration for ADC controller */
f54e9f2b SA	214	adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
	215	adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
	216
	217	adc_feature->calibration = true;
	218	adc_feature->ovwren = true;
	219
	220	adc_feature->res_mode = 12;
	221	adc_feature->sample_rate = 1;
	222	adc_feature->lpm = true;
a7754276	223
f54e9f2b SA	224	/* Use a save ADCK which is below 20MHz on all devices */
f54e9f2b SA	225	adc_feature->clk_div = 8;
a7754276	226
f54e9f2b	227	vf610_adc_calculate_rates(info);
a7754276 FD	228	}
	229
	230	static void vf610_adc_cfg_post_set(struct vf610_adc *info)
	231	{
	232	struct vf610_adc_feature *adc_feature = &info->adc_feature;
	233	int cfg_data = 0;
	234	int gc_data = 0;
	235
	236	switch (adc_feature->clk_sel) {
	237	case VF610_ADCIOC_ALTCLK_SET:
	238	cfg_data \|= VF610_ADC_ALTCLK_SEL;
	239	break;
	240	case VF610_ADCIOC_ADACK_SET:
	241	cfg_data \|= VF610_ADC_ADACK_SEL;
	242	break;
	243	default:
	244	break;
	245	}
	246
	247	/* low power set for calibration */
	248	cfg_data \|= VF610_ADC_ADLPC_EN;
	249
	250	/* enable high speed for calibration */
	251	cfg_data \|= VF610_ADC_ADHSC_EN;
	252
	253	/* voltage reference */
	254	switch (adc_feature->vol_ref) {
	255	case VF610_ADCIOC_VR_VREF_SET:
	256	break;
	257	case VF610_ADCIOC_VR_VALT_SET:
	258	cfg_data \|= VF610_ADC_REFSEL_VALT;
	259	break;
	260	case VF610_ADCIOC_VR_VBG_SET:
	261	cfg_data \|= VF610_ADC_REFSEL_VBG;
	262	break;
	263	default:
	264	dev_err(info->dev, "error voltage reference\n");
	265	}
	266
	267	/* data overwrite enable */
	268	if (adc_feature->ovwren)
	269	cfg_data \|= VF610_ADC_OVWREN;
	270
	271	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
	272	writel(gc_data, info->regs + VF610_REG_ADC_GC);
	273	}
	274
	275	static void vf610_adc_calibration(struct vf610_adc *info)
	276	{
	277	int adc_gc, hc_cfg;
a7754276 FD	278
	279	if (!info->adc_feature.calibration)
	280	return;
	281
	282	/* enable calibration interrupt */
	283	hc_cfg = VF610_ADC_AIEN \| VF610_ADC_CONV_DISABLE;
	284	writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
	285
	286	adc_gc = readl(info->regs + VF610_REG_ADC_GC);
	287	writel(adc_gc \| VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
	288
ee3ac290	289	if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
a7754276 FD	290	dev_err(info->dev, "Timeout for adc calibration\n");
	291
	292	adc_gc = readl(info->regs + VF610_REG_ADC_GS);
	293	if (adc_gc & VF610_ADC_CALF)
	294	dev_err(info->dev, "ADC calibration failed\n");
	295
	296	info->adc_feature.calibration = false;
	297	}
	298
	299	static void vf610_adc_cfg_set(struct vf610_adc *info)
	300	{
	301	struct vf610_adc_feature *adc_feature = &(info->adc_feature);
	302	int cfg_data;
	303
	304	cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
	305
a7754276 FD	306	cfg_data &= ~VF610_ADC_ADLPC_EN;
	307	if (adc_feature->lpm)
	308	cfg_data \|= VF610_ADC_ADLPC_EN;
	309
a7754276 FD	310	cfg_data &= ~VF610_ADC_ADHSC_EN;
	311
	312	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
	313	}
	314
	315	static void vf610_adc_sample_set(struct vf610_adc *info)
	316	{
	317	struct vf610_adc_feature *adc_feature = &(info->adc_feature);
	318	int cfg_data, gc_data;
	319
	320	cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
	321	gc_data = readl(info->regs + VF610_REG_ADC_GC);
	322
	323	/* resolution mode */
	324	cfg_data &= ~VF610_ADC_MODE_MASK;
	325	switch (adc_feature->res_mode) {
	326	case 8:
	327	cfg_data \|= VF610_ADC_MODE_BIT8;
	328	break;
	329	case 10:
	330	cfg_data \|= VF610_ADC_MODE_BIT10;
	331	break;
	332	case 12:
	333	cfg_data \|= VF610_ADC_MODE_BIT12;
	334	break;
	335	default:
	336	dev_err(info->dev, "error resolution mode\n");
	337	break;
	338	}
	339
	340	/* clock select and clock divider */
	341	cfg_data &= ~(VF610_ADC_CLK_MASK \| VF610_ADC_ADCCLK_MASK);
	342	switch (adc_feature->clk_div) {
	343	case 1:
	344	break;
	345	case 2:
	346	cfg_data \|= VF610_ADC_CLK_DIV2;
	347	break;
	348	case 4:
	349	cfg_data \|= VF610_ADC_CLK_DIV4;
	350	break;
	351	case 8:
	352	cfg_data \|= VF610_ADC_CLK_DIV8;
	353	break;
	354	case 16:
	355	switch (adc_feature->clk_sel) {
	356	case VF610_ADCIOC_BUSCLK_SET:
	357	cfg_data \|= VF610_ADC_BUSCLK2_SEL \| VF610_ADC_CLK_DIV8;
	358	break;
	359	default:
	360	dev_err(info->dev, "error clk divider\n");
	361	break;
	362	}
	363	break;
	364	}
	365
	366	/* Use the short sample mode */
	367	cfg_data &= ~(VF610_ADC_ADLSMP_LONG \| VF610_ADC_ADSTS_MASK);
	368
	369	/* update hardware average selection */
	370	cfg_data &= ~VF610_ADC_AVGS_MASK;
	371	gc_data &= ~VF610_ADC_AVGEN;
	372	switch (adc_feature->sample_rate) {
	373	case VF610_ADC_SAMPLE_1:
374	break;
375	case VF610_ADC_SAMPLE_4:
376	gc_data \|= VF610_ADC_AVGEN;
377	break;
378	case VF610_ADC_SAMPLE_8:
379	gc_data \|= VF610_ADC_AVGEN;
380	cfg_data \|= VF610_ADC_AVGS_8;
381	break;
382	case VF610_ADC_SAMPLE_16:
383	gc_data \|= VF610_ADC_AVGEN;
384	cfg_data \|= VF610_ADC_AVGS_16;
385	break;
386	case VF610_ADC_SAMPLE_32:
387	gc_data \|= VF610_ADC_AVGEN;
388	cfg_data \|= VF610_ADC_AVGS_32;
389	break;
390	default:
391	dev_err(info->dev,
392	"error hardware sample average select\n");
393	}
394
395	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
396	writel(gc_data, info->regs + VF610_REG_ADC_GC);
397	}
398
399	static void vf610_adc_hw_init(struct vf610_adc *info)
400	{
401	/* CFG: Feature set */
402	vf610_adc_cfg_post_set(info);
403	vf610_adc_sample_set(info);
404
405	/* adc calibration */
406	vf610_adc_calibration(info);
407
408	/* CFG: power and speed set */
409	vf610_adc_cfg_set(info);
410	}
411
412	static int vf610_adc_read_data(struct vf610_adc *info)
413	{
414	int result;
415
416	result = readl(info->regs + VF610_REG_ADC_R0);
417
418	switch (info->adc_feature.res_mode) {
419	case 8:
420	result &= 0xFF;
421	break;
422	case 10:
423	result &= 0x3FF;
424	break;
425	case 12:
426	result &= 0xFFF;
427	break;
428	default:
429	break;
430	}
431
432	return result;
433	}
434
435	static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
436	{
437	struct vf610_adc info = (struct vf610_adc )dev_id;
438	int coco;
439
440	coco = readl(info->regs + VF610_REG_ADC_HS);
441	if (coco & VF610_ADC_HS_COCO0) {
442	info->value = vf610_adc_read_data(info);
443	complete(&info->completion);
444	}
445
446	return IRQ_HANDLED;
447	}
448
f54e9f2b SA	449	static ssize_t vf610_show_samp_freq_avail(struct device *dev,
	450	struct device_attribute attr, char buf)
	451	{
	452	struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
	453	size_t len = 0;
	454	int i;
	455
	456	for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
	457	len += scnprintf(buf + len, PAGE_SIZE - len,
	458	"%u ", info->sample_freq_avail[i]);
	459
	460	/* replace trailing space by newline */
	461	buf[len - 1] = '\n';
	462
	463	return len;
	464	}
	465
	466	static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
a7754276 FD	467
a7754276 FD	468	static struct attribute *vf610_attributes[] = {
f54e9f2b	469	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
a7754276 FD	470	NULL
	471	};
	472
	473	static const struct attribute_group vf610_attribute_group = {
	474	.attrs = vf610_attributes,
	475	};
	476
	477	static int vf610_read_raw(struct iio_dev *indio_dev,
	478	struct iio_chan_spec const *chan,
	479	int *val,
	480	int *val2,
	481	long mask)
	482	{
	483	struct vf610_adc *info = iio_priv(indio_dev);
	484	unsigned int hc_cfg;
db8fa731	485	long ret;
a7754276 FD	486
	487	switch (mask) {
	488	case IIO_CHAN_INFO_RAW:
774623ca	489	case IIO_CHAN_INFO_PROCESSED:
a7754276 FD	490	mutex_lock(&indio_dev->mlock);
	491	reinit_completion(&info->completion);
	492
	493	hc_cfg = VF610_ADC_ADCHC(chan->channel);
	494	hc_cfg \|= VF610_ADC_AIEN;
	495	writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
	496	ret = wait_for_completion_interruptible_timeout
	497	(&info->completion, VF610_ADC_TIMEOUT);
	498	if (ret == 0) {
	499	mutex_unlock(&indio_dev->mlock);
	500	return -ETIMEDOUT;
	501	}
	502	if (ret < 0) {
	503	mutex_unlock(&indio_dev->mlock);
	504	return ret;
	505	}
	506
774623ca SM	507	switch (chan->type) {
	508	case IIO_VOLTAGE:
	509	*val = info->value;
	510	break;
	511	case IIO_TEMP:
	512	/*
	513	* Calculate in degree Celsius times 1000
	514	* Using sensor slope of 1.84 mV/°C and
	515	* V at 25°C of 696 mV
	516	*/
	517	val = 25000 - ((int)info->value - 864) 1000000 / 1840;
	518	break;
	519	default:
	520	mutex_unlock(&indio_dev->mlock);
	521	return -EINVAL;
	522	}
	523
a7754276 FD	524	mutex_unlock(&indio_dev->mlock);
	525	return IIO_VAL_INT;
	526
	527	case IIO_CHAN_INFO_SCALE:
	528	*val = info->vref_uv / 1000;
	529	*val2 = info->adc_feature.res_mode;
	530	return IIO_VAL_FRACTIONAL_LOG2;
	531
	532	case IIO_CHAN_INFO_SAMP_FREQ:
f54e9f2b	533	*val = info->sample_freq_avail[info->adc_feature.sample_rate];
a7754276 FD	534	*val2 = 0;
	535	return IIO_VAL_INT;
	536
	537	default:
	538	break;
	539	}
	540
	541	return -EINVAL;
	542	}
	543
	544	static int vf610_write_raw(struct iio_dev *indio_dev,
	545	struct iio_chan_spec const *chan,
	546	int val,
	547	int val2,
	548	long mask)
	549	{
	550	struct vf610_adc *info = iio_priv(indio_dev);
	551	int i;
	552
	553	switch (mask) {
	554	case IIO_CHAN_INFO_SAMP_FREQ:
	555	for (i = 0;
f54e9f2b	556	i < ARRAY_SIZE(info->sample_freq_avail);
a7754276	557	i++)
f54e9f2b	558	if (val == info->sample_freq_avail[i]) {
a7754276 FD	559	info->adc_feature.sample_rate = i;
	560	vf610_adc_sample_set(info);
	561	return 0;
	562	}
	563	break;
	564
	565	default:
	566	break;
	567	}
	568
	569	return -EINVAL;
	570	}
	571
	572	static int vf610_adc_reg_access(struct iio_dev *indio_dev,
	573	unsigned reg, unsigned writeval,
	574	unsigned *readval)
	575	{
	576	struct vf610_adc *info = iio_priv(indio_dev);
	577
	578	if ((readval == NULL) \|\|
	579	(!(reg % 4) \|\| (reg > VF610_REG_ADC_PCTL)))
	580	return -EINVAL;
	581
	582	*readval = readl(info->regs + reg);
	583
	584	return 0;
	585	}
	586
	587	static const struct iio_info vf610_adc_iio_info = {
	588	.driver_module = THIS_MODULE,
	589	.read_raw = &vf610_read_raw,
	590	.write_raw = &vf610_write_raw,
	591	.debugfs_reg_access = &vf610_adc_reg_access,
	592	.attrs = &vf610_attribute_group,
	593	};
	594
	595	static const struct of_device_id vf610_adc_match[] = {
	596	{ .compatible = "fsl,vf610-adc", },
	597	{ /* sentinel */ }
	598	};
	599	MODULE_DEVICE_TABLE(of, vf610_adc_match);
	600
	601	static int vf610_adc_probe(struct platform_device *pdev)
	602	{
	603	struct vf610_adc *info;
	604	struct iio_dev *indio_dev;
	605	struct resource *mem;
	606	int irq;
	607	int ret;
	608
	609	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
	610	if (!indio_dev) {
	611	dev_err(&pdev->dev, "Failed allocating iio device\n");
	612	return -ENOMEM;
	613	}
	614
	615	info = iio_priv(indio_dev);
	616	info->dev = &pdev->dev;
	617
	618	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	619	info->regs = devm_ioremap_resource(&pdev->dev, mem);
	620	if (IS_ERR(info->regs))
	621	return PTR_ERR(info->regs);
	622
623	irq = platform_get_irq(pdev, 0);
8552befa	624	if (irq < 0) {
a7754276	625	dev_err(&pdev->dev, "no irq resource?\n");
8552befa	626	return irq;
a7754276 FD	627	}
	628
	629	ret = devm_request_irq(info->dev, irq,
	630	vf610_adc_isr, 0,
	631	dev_name(&pdev->dev), info);
	632	if (ret < 0) {
	633	dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
	634	return ret;
	635	}
	636
	637	info->clk = devm_clk_get(&pdev->dev, "adc");
	638	if (IS_ERR(info->clk)) {
	639	dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
	640	PTR_ERR(info->clk));
2e3d6675	641	return PTR_ERR(info->clk);
a7754276 FD	642	}
	643
	644	info->vref = devm_regulator_get(&pdev->dev, "vref");
	645	if (IS_ERR(info->vref))
	646	return PTR_ERR(info->vref);
	647
	648	ret = regulator_enable(info->vref);
	649	if (ret)
	650	return ret;
	651
	652	info->vref_uv = regulator_get_voltage(info->vref);
	653
	654	platform_set_drvdata(pdev, indio_dev);
	655
	656	init_completion(&info->completion);
	657
	658	indio_dev->name = dev_name(&pdev->dev);
	659	indio_dev->dev.parent = &pdev->dev;
	660	indio_dev->dev.of_node = pdev->dev.of_node;
	661	indio_dev->info = &vf610_adc_iio_info;
	662	indio_dev->modes = INDIO_DIRECT_MODE;
	663	indio_dev->channels = vf610_adc_iio_channels;
	664	indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
	665
	666	ret = clk_prepare_enable(info->clk);
	667	if (ret) {
	668	dev_err(&pdev->dev,
	669	"Could not prepare or enable the clock.\n");
	670	goto error_adc_clk_enable;
	671	}
	672
	673	vf610_adc_cfg_init(info);
	674	vf610_adc_hw_init(info);
	675
	676	ret = iio_device_register(indio_dev);
	677	if (ret) {
	678	dev_err(&pdev->dev, "Couldn't register the device.\n");
	679	goto error_iio_device_register;
	680	}
	681
	682	return 0;
	683
	684
	685	error_iio_device_register:
	686	clk_disable_unprepare(info->clk);
	687	error_adc_clk_enable:
	688	regulator_disable(info->vref);
	689
	690	return ret;
	691	}
	692
	693	static int vf610_adc_remove(struct platform_device *pdev)
	694	{
	695	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
	696	struct vf610_adc *info = iio_priv(indio_dev);
	697
	698	iio_device_unregister(indio_dev);
	699	regulator_disable(info->vref);
	700	clk_disable_unprepare(info->clk);
	701
	702	return 0;
	703	}
	704
	705	#ifdef CONFIG_PM_SLEEP
706	static int vf610_adc_suspend(struct device *dev)
707	{
708	struct iio_dev *indio_dev = dev_get_drvdata(dev);
709	struct vf610_adc *info = iio_priv(indio_dev);
710	int hc_cfg;
711
712	/* ADC controller enters to stop mode */
713	hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
714	hc_cfg \|= VF610_ADC_CONV_DISABLE;
715	writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
716
717	clk_disable_unprepare(info->clk);
718	regulator_disable(info->vref);
719
720	return 0;
721	}
722
723	static int vf610_adc_resume(struct device *dev)
724	{
725	struct iio_dev *indio_dev = dev_get_drvdata(dev);
726	struct vf610_adc *info = iio_priv(indio_dev);
727	int ret;
728
729	ret = regulator_enable(info->vref);
730	if (ret)
731	return ret;
732
733	ret = clk_prepare_enable(info->clk);
734	if (ret)
9da64c25	735	goto disable_reg;
a7754276 FD	736
	737	vf610_adc_hw_init(info);
	738
	739	return 0;
9da64c25 FE	740
	741	disable_reg:
	742	regulator_disable(info->vref);
	743	return ret;
a7754276 FD	744	}
	745	#endif
	746
ef0d5454	747	static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
a7754276 FD	748
	749	static struct platform_driver vf610_adc_driver = {
	750	.probe = vf610_adc_probe,
	751	.remove = vf610_adc_remove,
	752	.driver = {
	753	.name = DRIVER_NAME,
a7754276 FD	754	.of_match_table = vf610_adc_match,
	755	.pm = &vf610_adc_pm_ops,
	756	},
	757	};
	758
	759	module_platform_driver(vf610_adc_driver);
	760
	761	MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
	762	MODULE_DESCRIPTION("Freescale VF610 ADC driver");
	763	MODULE_LICENSE("GPL v2");