[mirror_ubuntu-hirsute-kernel.git] / drivers / iio / dac / ad5064.c

/*
 * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5628, AD5629R,
 * AD5648, AD5666, AD5668, AD5669R Digital to analog converters driver
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <asm/unaligned.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>

#define AD5064_MAX_DAC_CHANNELS			8
#define AD5064_MAX_VREFS			4

#define AD5064_ADDR(x)				((x) << 20)
#define AD5064_CMD(x)				((x) << 24)

#define AD5064_ADDR_ALL_DAC			0xF

#define AD5064_CMD_WRITE_INPUT_N		0x0
#define AD5064_CMD_UPDATE_DAC_N			0x1
#define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL	0x2
#define AD5064_CMD_WRITE_INPUT_N_UPDATE_N	0x3
#define AD5064_CMD_POWERDOWN_DAC		0x4
#define AD5064_CMD_CLEAR			0x5
#define AD5064_CMD_LDAC_MASK			0x6
#define AD5064_CMD_RESET			0x7
#define AD5064_CMD_CONFIG			0x8

#define AD5064_CONFIG_DAISY_CHAIN_ENABLE	BIT(1)
#define AD5064_CONFIG_INT_VREF_ENABLE		BIT(0)

#define AD5064_LDAC_PWRDN_NONE			0x0
#define AD5064_LDAC_PWRDN_1K			0x1
#define AD5064_LDAC_PWRDN_100K			0x2
#define AD5064_LDAC_PWRDN_3STATE		0x3

/**
 * struct ad5064_chip_info - chip specific information
 * @shared_vref:	whether the vref supply is shared between channels
 * @internal_vref:	internal reference voltage. 0 if the chip has no internal
 *			vref.
 * @channel:		channel specification
 * @num_channels:	number of channels
 */

struct ad5064_chip_info {
	bool shared_vref;
	unsigned long internal_vref;
	const struct iio_chan_spec *channels;
	unsigned int num_channels;
};

struct ad5064_state;

typedef int (*ad5064_write_func)(struct ad5064_state *st, unsigned int cmd,
		unsigned int addr, unsigned int val);

/**
 * struct ad5064_state - driver instance specific data
 * @dev:		the device for this driver instance
 * @chip_info:		chip model specific constants, available modes etc
 * @vref_reg:		vref supply regulators
 * @pwr_down:		whether channel is powered down
 * @pwr_down_mode:	channel's current power down mode
 * @dac_cache:		current DAC raw value (chip does not support readback)
 * @use_internal_vref:	set to true if the internal reference voltage should be
 *			used.
 * @write:		register write callback
 * @data:		i2c/spi transfer buffers
 */

struct ad5064_state {
	struct device			*dev;
	const struct ad5064_chip_info	*chip_info;
	struct regulator_bulk_data	vref_reg[AD5064_MAX_VREFS];
	bool				pwr_down[AD5064_MAX_DAC_CHANNELS];
	u8				pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
	unsigned int			dac_cache[AD5064_MAX_DAC_CHANNELS];
	bool				use_internal_vref;

	ad5064_write_func		write;

	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 */
	union {
		u8 i2c[3];
		__be32 spi;
	} data ____cacheline_aligned;
};

enum ad5064_type {
	ID_AD5024,
	ID_AD5025,
	ID_AD5044,
	ID_AD5045,
	ID_AD5064,
	ID_AD5064_1,
	ID_AD5065,
	ID_AD5628_1,
	ID_AD5628_2,
	ID_AD5648_1,
	ID_AD5648_2,
	ID_AD5666_1,
	ID_AD5666_2,
	ID_AD5668_1,
	ID_AD5668_2,
};

static int ad5064_write(struct ad5064_state *st, unsigned int cmd,
	unsigned int addr, unsigned int val, unsigned int shift)
{
	val <<= shift;

	return st->write(st, cmd, addr, val);
}

static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
	const struct iio_chan_spec *chan)
{
	unsigned int val;
	int ret;

	val = (0x1 << chan->address);

	if (st->pwr_down[chan->channel])
		val |= st->pwr_down_mode[chan->channel] << 8;

	ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, 0, val, 0);

	return ret;
}

static const char * const ad5064_powerdown_modes[] = {
	"1kohm_to_gnd",
	"100kohm_to_gnd",
	"three_state",
};

static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan)
{
	struct ad5064_state *st = iio_priv(indio_dev);

	return st->pwr_down_mode[chan->channel] - 1;
}

static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev,
	const struct iio_chan_spec *chan, unsigned int mode)
{
	struct ad5064_state *st = iio_priv(indio_dev);
	int ret;

	mutex_lock(&indio_dev->mlock);
	st->pwr_down_mode[chan->channel] = mode + 1;

	ret = ad5064_sync_powerdown_mode(st, chan);
	mutex_unlock(&indio_dev->mlock);

	return ret;
}

static const struct iio_enum ad5064_powerdown_mode_enum = {
	.items = ad5064_powerdown_modes,
	.num_items = ARRAY_SIZE(ad5064_powerdown_modes),
	.get = ad5064_get_powerdown_mode,
	.set = ad5064_set_powerdown_mode,
};

static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
	uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
	struct ad5064_state *st = iio_priv(indio_dev);

	return sprintf(buf, "%d\n", st->pwr_down[chan->channel]);
}

static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
	 uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
	 size_t len)
{
	struct ad5064_state *st = iio_priv(indio_dev);
	bool pwr_down;
	int ret;

	ret = strtobool(buf, &pwr_down);
	if (ret)
		return ret;

	mutex_lock(&indio_dev->mlock);
	st->pwr_down[chan->channel] = pwr_down;

	ret = ad5064_sync_powerdown_mode(st, chan);
	mutex_unlock(&indio_dev->mlock);
	return ret ? ret : len;
}

static int ad5064_get_vref(struct ad5064_state *st,
	struct iio_chan_spec const *chan)
{
	unsigned int i;

	if (st->use_internal_vref)
		return st->chip_info->internal_vref;

	i = st->chip_info->shared_vref ? 0 : chan->channel;
	return regulator_get_voltage(st->vref_reg[i].consumer);
}

static int ad5064_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	struct ad5064_state *st = iio_priv(indio_dev);
	int scale_uv;

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		*val = st->dac_cache[chan->channel];
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		scale_uv = ad5064_get_vref(st, chan);
		if (scale_uv < 0)
			return scale_uv;

		scale_uv = (scale_uv * 100) >> chan->scan_type.realbits;
		*val =  scale_uv / 100000;
		*val2 = (scale_uv % 100000) * 10;
		return IIO_VAL_INT_PLUS_MICRO;
	default:
		break;
	}
	return -EINVAL;
}

static int ad5064_write_raw(struct iio_dev *indio_dev,
	struct iio_chan_spec const *chan, int val, int val2, long mask)
{
	struct ad5064_state *st = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		if (val >= (1 << chan->scan_type.realbits) || val < 0)
			return -EINVAL;

		mutex_lock(&indio_dev->mlock);
		ret = ad5064_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
				chan->address, val, chan->scan_type.shift);
		if (ret == 0)
			st->dac_cache[chan->channel] = val;
		mutex_unlock(&indio_dev->mlock);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static const struct iio_info ad5064_info = {
	.read_raw = ad5064_read_raw,
	.write_raw = ad5064_write_raw,
	.driver_module = THIS_MODULE,
};

static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
	{
		.name = "powerdown",
		.read = ad5064_read_dac_powerdown,
		.write = ad5064_write_dac_powerdown,
	},
	IIO_ENUM("powerdown_mode", false, &ad5064_powerdown_mode_enum),
	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5064_powerdown_mode_enum),
	{ },
};

#define AD5064_CHANNEL(chan, addr, bits) {			\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.output = 1,						\
	.channel = (chan),					\
	.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |		\
	IIO_CHAN_INFO_SCALE_SEPARATE_BIT,			\
	.address = addr,					\
	.scan_type = IIO_ST('u', (bits), 16, 20 - (bits)),	\
	.ext_info = ad5064_ext_info,				\
}

#define DECLARE_AD5064_CHANNELS(name, bits) \
const struct iio_chan_spec name[] = { \
	AD5064_CHANNEL(0, 0, bits), \
	AD5064_CHANNEL(1, 1, bits), \
	AD5064_CHANNEL(2, 2, bits), \
	AD5064_CHANNEL(3, 3, bits), \
	AD5064_CHANNEL(4, 4, bits), \
	AD5064_CHANNEL(5, 5, bits), \
	AD5064_CHANNEL(6, 6, bits), \
	AD5064_CHANNEL(7, 7, bits), \
}

#define DECLARE_AD5065_CHANNELS(name, bits) \
const struct iio_chan_spec name[] = { \
	AD5064_CHANNEL(0, 0, bits), \
	AD5064_CHANNEL(1, 3, bits), \
}

static DECLARE_AD5064_CHANNELS(ad5024_channels, 12);
static DECLARE_AD5064_CHANNELS(ad5044_channels, 14);
static DECLARE_AD5064_CHANNELS(ad5064_channels, 16);

static DECLARE_AD5065_CHANNELS(ad5025_channels, 12);
static DECLARE_AD5065_CHANNELS(ad5045_channels, 14);
static DECLARE_AD5065_CHANNELS(ad5065_channels, 16);

static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
	[ID_AD5024] = {
		.shared_vref = false,
		.channels = ad5024_channels,
		.num_channels = 4,
	},
	[ID_AD5025] = {
		.shared_vref = false,
		.channels = ad5025_channels,
		.num_channels = 2,
	},
	[ID_AD5044] = {
		.shared_vref = false,
		.channels = ad5044_channels,
		.num_channels = 4,
	},
	[ID_AD5045] = {
		.shared_vref = false,
		.channels = ad5045_channels,
		.num_channels = 2,
	},
	[ID_AD5064] = {
		.shared_vref = false,
		.channels = ad5064_channels,
		.num_channels = 4,
	},
	[ID_AD5064_1] = {
		.shared_vref = true,
		.channels = ad5064_channels,
		.num_channels = 4,
	},
	[ID_AD5065] = {
		.shared_vref = false,
		.channels = ad5065_channels,
		.num_channels = 2,
	},
	[ID_AD5628_1] = {
		.shared_vref = true,
		.internal_vref = 2500000,
		.channels = ad5024_channels,
		.num_channels = 8,
	},
	[ID_AD5628_2] = {
		.shared_vref = true,
		.internal_vref = 5000000,
		.channels = ad5024_channels,
		.num_channels = 8,
	},
	[ID_AD5648_1] = {
		.shared_vref = true,
		.internal_vref = 2500000,
		.channels = ad5044_channels,
		.num_channels = 8,
	},
	[ID_AD5648_2] = {
		.shared_vref = true,
		.internal_vref = 5000000,
		.channels = ad5044_channels,
		.num_channels = 8,
	},
	[ID_AD5666_1] = {
		.shared_vref = true,
		.internal_vref = 2500000,
		.channels = ad5064_channels,
		.num_channels = 4,
	},
	[ID_AD5666_2] = {
		.shared_vref = true,
		.internal_vref = 5000000,
		.channels = ad5064_channels,
		.num_channels = 4,
	},
	[ID_AD5668_1] = {
		.shared_vref = true,
		.internal_vref = 2500000,
		.channels = ad5064_channels,
		.num_channels = 8,
	},
	[ID_AD5668_2] = {
		.shared_vref = true,
		.internal_vref = 5000000,
		.channels = ad5064_channels,
		.num_channels = 8,
	},
};

static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
{
	return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
}

static const char * const ad5064_vref_names[] = {
	"vrefA",
	"vrefB",
	"vrefC",
	"vrefD",
};

static const char * const ad5064_vref_name(struct ad5064_state *st,
	unsigned int vref)
{
	return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
}

static int ad5064_probe(struct device *dev, enum ad5064_type type,
			const char *name, ad5064_write_func write)
{
	struct iio_dev *indio_dev;
	struct ad5064_state *st;
	unsigned int i;
	int ret;

	indio_dev = iio_device_alloc(sizeof(*st));
	if (indio_dev == NULL)
		return  -ENOMEM;

	st = iio_priv(indio_dev);
	dev_set_drvdata(dev, indio_dev);

	st->chip_info = &ad5064_chip_info_tbl[type];
	st->dev = dev;
	st->write = write;

	for (i = 0; i < ad5064_num_vref(st); ++i)
		st->vref_reg[i].supply = ad5064_vref_name(st, i);

	ret = regulator_bulk_get(dev, ad5064_num_vref(st),
		st->vref_reg);
	if (ret) {
		if (!st->chip_info->internal_vref)
			goto error_free;
		st->use_internal_vref = true;
		ret = ad5064_write(st, AD5064_CMD_CONFIG, 0,
			AD5064_CONFIG_INT_VREF_ENABLE, 0);
		if (ret) {
			dev_err(dev, "Failed to enable internal vref: %d\n",
				ret);
			goto error_free;
		}
	} else {
		ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
		if (ret)
			goto error_free_reg;
	}

	for (i = 0; i < st->chip_info->num_channels; ++i) {
		st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
		st->dac_cache[i] = 0x8000;
	}

	indio_dev->dev.parent = dev;
	indio_dev->name = name;
	indio_dev->info = &ad5064_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = st->chip_info->channels;
	indio_dev->num_channels = st->chip_info->num_channels;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_disable_reg;

	return 0;

error_disable_reg:
	if (!st->use_internal_vref)
		regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
error_free_reg:
	if (!st->use_internal_vref)
		regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
error_free:
	iio_device_free(indio_dev);

	return ret;
}

static int ad5064_remove(struct device *dev)
{
	struct iio_dev *indio_dev = dev_get_drvdata(dev);
	struct ad5064_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);

	if (!st->use_internal_vref) {
		regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
		regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
	}

	iio_device_free(indio_dev);

	return 0;
}

#if IS_ENABLED(CONFIG_SPI_MASTER)

static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
	unsigned int addr, unsigned int val)
{
	struct spi_device *spi = to_spi_device(st->dev);

	st->data.spi = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val);
	return spi_write(spi, &st->data.spi, sizeof(st->data.spi));
}

static int ad5064_spi_probe(struct spi_device *spi)
{
	const struct spi_device_id *id = spi_get_device_id(spi);

	return ad5064_probe(&spi->dev, id->driver_data, id->name,
				ad5064_spi_write);
}

static int ad5064_spi_remove(struct spi_device *spi)
{
	return ad5064_remove(&spi->dev);
}

static const struct spi_device_id ad5064_spi_ids[] = {
	{"ad5024", ID_AD5024},
	{"ad5025", ID_AD5025},
	{"ad5044", ID_AD5044},
	{"ad5045", ID_AD5045},
	{"ad5064", ID_AD5064},
	{"ad5064-1", ID_AD5064_1},
	{"ad5065", ID_AD5065},
	{"ad5628-1", ID_AD5628_1},
	{"ad5628-2", ID_AD5628_2},
	{"ad5648-1", ID_AD5648_1},
	{"ad5648-2", ID_AD5648_2},
	{"ad5666-1", ID_AD5666_1},
	{"ad5666-2", ID_AD5666_2},
	{"ad5668-1", ID_AD5668_1},
	{"ad5668-2", ID_AD5668_2},
	{"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */
	{}
};
MODULE_DEVICE_TABLE(spi, ad5064_spi_ids);

static struct spi_driver ad5064_spi_driver = {
	.driver = {
		   .name = "ad5064",
		   .owner = THIS_MODULE,
	},
	.probe = ad5064_spi_probe,
	.remove = ad5064_spi_remove,
	.id_table = ad5064_spi_ids,
};

static int __init ad5064_spi_register_driver(void)
{
	return spi_register_driver(&ad5064_spi_driver);
}

static void ad5064_spi_unregister_driver(void)
{
	spi_unregister_driver(&ad5064_spi_driver);
}

#else

static inline int ad5064_spi_register_driver(void) { return 0; }
static inline void ad5064_spi_unregister_driver(void) { }

#endif

#if IS_ENABLED(CONFIG_I2C)

static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd,
	unsigned int addr, unsigned int val)
{
	struct i2c_client *i2c = to_i2c_client(st->dev);

	st->data.i2c[0] = (cmd << 4) | addr;
	put_unaligned_be16(val, &st->data.i2c[1]);
	return i2c_master_send(i2c, st->data.i2c, 3);
}

static int ad5064_i2c_probe(struct i2c_client *i2c,
	const struct i2c_device_id *id)
{
	return ad5064_probe(&i2c->dev, id->driver_data, id->name,
						ad5064_i2c_write);
}

static int ad5064_i2c_remove(struct i2c_client *i2c)
{
	return ad5064_remove(&i2c->dev);
}

static const struct i2c_device_id ad5064_i2c_ids[] = {
	{"ad5629-1", ID_AD5628_1},
	{"ad5629-2", ID_AD5628_2},
	{"ad5629-3", ID_AD5628_2}, /* similar enough to ad5629-2 */
	{"ad5669-1", ID_AD5668_1},
	{"ad5669-2", ID_AD5668_2},
	{"ad5669-3", ID_AD5668_2}, /* similar enough to ad5669-2 */
	{}
};
MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids);

static struct i2c_driver ad5064_i2c_driver = {
	.driver = {
		   .name = "ad5064",
		   .owner = THIS_MODULE,
	},
	.probe = ad5064_i2c_probe,
	.remove = ad5064_i2c_remove,
	.id_table = ad5064_i2c_ids,
};

static int __init ad5064_i2c_register_driver(void)
{
	return i2c_add_driver(&ad5064_i2c_driver);
}

static void __exit ad5064_i2c_unregister_driver(void)
{
	i2c_del_driver(&ad5064_i2c_driver);
}

#else

static inline int ad5064_i2c_register_driver(void) { return 0; }
static inline void ad5064_i2c_unregister_driver(void) { }

#endif

static int __init ad5064_init(void)
{
	int ret;

	ret = ad5064_spi_register_driver();
	if (ret)
		return ret;

	ret = ad5064_i2c_register_driver();
	if (ret) {
		ad5064_spi_unregister_driver();
		return ret;
	}

	return 0;
}
module_init(ad5064_init);

static void __exit ad5064_exit(void)
{
	ad5064_i2c_unregister_driver();
	ad5064_spi_unregister_driver();
}
module_exit(ad5064_exit);

MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("Analog Devices AD5024 and similar multi-channel DACs");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fcf265d6	1	/*
6a17a076 LPC	2	* AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5628, AD5629R,
6a17a076 LPC	3	* AD5648, AD5666, AD5668, AD5669R Digital to analog converters driver
fcf265d6 LPC	4	*
	5	* Copyright 2011 Analog Devices Inc.
	6	*
	7	* Licensed under the GPL-2.
	8	*/
	9
	10	#include <linux/device.h>
	11	#include <linux/err.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/spi/spi.h>
6a17a076	15	#include <linux/i2c.h>
fcf265d6 LPC	16	#include <linux/slab.h>
	17	#include <linux/sysfs.h>
	18	#include <linux/regulator/consumer.h>
6a17a076	19	#include <asm/unaligned.h>
fcf265d6	20
06458e27 JC	21	#include <linux/iio/iio.h>
06458e27 JC	22	#include <linux/iio/sysfs.h>
fcf265d6	23
bb92ff3e	24	#define AD5064_MAX_DAC_CHANNELS 8
83c169d5	25	#define AD5064_MAX_VREFS 4
fcf265d6 LPC	26
	27	#define AD5064_ADDR(x) ((x) << 20)
	28	#define AD5064_CMD(x) ((x) << 24)
	29
fcf265d6 LPC	30	#define AD5064_ADDR_ALL_DAC 0xF
	31
	32	#define AD5064_CMD_WRITE_INPUT_N 0x0
	33	#define AD5064_CMD_UPDATE_DAC_N 0x1
	34	#define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
	35	#define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3
	36	#define AD5064_CMD_POWERDOWN_DAC 0x4
	37	#define AD5064_CMD_CLEAR 0x5
	38	#define AD5064_CMD_LDAC_MASK 0x6
	39	#define AD5064_CMD_RESET 0x7
bb92ff3e LPC	40	#define AD5064_CMD_CONFIG 0x8
	41
	42	#define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1)
	43	#define AD5064_CONFIG_INT_VREF_ENABLE BIT(0)
fcf265d6 LPC	44
	45	#define AD5064_LDAC_PWRDN_NONE 0x0
	46	#define AD5064_LDAC_PWRDN_1K 0x1
	47	#define AD5064_LDAC_PWRDN_100K 0x2
	48	#define AD5064_LDAC_PWRDN_3STATE 0x3
	49
	50	/**
	51	* struct ad5064_chip_info - chip specific information
	52	* @shared_vref: whether the vref supply is shared between channels
bb92ff3e LPC	53	* @internal_vref: internal reference voltage. 0 if the chip has no internal
bb92ff3e LPC	54	* vref.
fcf265d6	55	* @channel: channel specification
83c169d5 LPC	56	* @num_channels: number of channels
83c169d5 LPC	57	*/
fcf265d6 LPC	58
	59	struct ad5064_chip_info {
	60	bool shared_vref;
bb92ff3e	61	unsigned long internal_vref;
83c169d5 LPC	62	const struct iio_chan_spec *channels;
83c169d5 LPC	63	unsigned int num_channels;
fcf265d6 LPC	64	};
fcf265d6 LPC	65
6a17a076 LPC	66	struct ad5064_state;
	67
	68	typedef int (ad5064_write_func)(struct ad5064_state st, unsigned int cmd,
	69	unsigned int addr, unsigned int val);
	70
fcf265d6 LPC	71	/**
fcf265d6 LPC	72	* struct ad5064_state - driver instance specific data
6a17a076	73	* @dev: the device for this driver instance
fcf265d6 LPC	74	* @chip_info: chip model specific constants, available modes etc
	75	* @vref_reg: vref supply regulators
	76	* @pwr_down: whether channel is powered down
	77	* @pwr_down_mode: channel's current power down mode
	78	* @dac_cache: current DAC raw value (chip does not support readback)
bb92ff3e LPC	79	* @use_internal_vref: set to true if the internal reference voltage should be
bb92ff3e LPC	80	* used.
6a17a076 LPC	81	* @write: register write callback
6a17a076 LPC	82	* @data: i2c/spi transfer buffers
fcf265d6 LPC	83	*/
	84
	85	struct ad5064_state {
6a17a076	86	struct device *dev;
fcf265d6	87	const struct ad5064_chip_info *chip_info;
83c169d5 LPC	88	struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS];
	89	bool pwr_down[AD5064_MAX_DAC_CHANNELS];
	90	u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
	91	unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS];
bb92ff3e	92	bool use_internal_vref;
fcf265d6	93
6a17a076 LPC	94	ad5064_write_func write;
6a17a076 LPC	95
fcf265d6 LPC	96	/*
	97	* DMA (thus cache coherency maintenance) requires the
	98	* transfer buffers to live in their own cache lines.
	99	*/
6a17a076 LPC	100	union {
	101	u8 i2c[3];
	102	__be32 spi;
	103	} data ____cacheline_aligned;
fcf265d6 LPC	104	};
	105
	106	enum ad5064_type {
	107	ID_AD5024,
f8be4af1	108	ID_AD5025,
fcf265d6	109	ID_AD5044,
f8be4af1	110	ID_AD5045,
fcf265d6 LPC	111	ID_AD5064,
fcf265d6 LPC	112	ID_AD5064_1,
f8be4af1	113	ID_AD5065,
bb92ff3e LPC	114	ID_AD5628_1,
	115	ID_AD5628_2,
	116	ID_AD5648_1,
	117	ID_AD5648_2,
64f4eaa5 LPC	118	ID_AD5666_1,
64f4eaa5 LPC	119	ID_AD5666_2,
bb92ff3e LPC	120	ID_AD5668_1,
bb92ff3e LPC	121	ID_AD5668_2,
fcf265d6 LPC	122	};
fcf265d6 LPC	123
6a17a076	124	static int ad5064_write(struct ad5064_state *st, unsigned int cmd,
fcf265d6 LPC	125	unsigned int addr, unsigned int val, unsigned int shift)
	126	{
	127	val <<= shift;
	128
6a17a076	129	return st->write(st, cmd, addr, val);
fcf265d6 LPC	130	}
	131
	132	static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
a2630262	133	const struct iio_chan_spec *chan)
fcf265d6 LPC	134	{
	135	unsigned int val;
	136	int ret;
	137
a2630262	138	val = (0x1 << chan->address);
fcf265d6	139
a2630262 LPC	140	if (st->pwr_down[chan->channel])
a2630262 LPC	141	val \|= st->pwr_down_mode[chan->channel] << 8;
fcf265d6	142
6a17a076	143	ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, 0, val, 0);
fcf265d6 LPC	144
	145	return ret;
	146	}
	147
26628f6b LPC	148	static const char * const ad5064_powerdown_modes[] = {
	149	"1kohm_to_gnd",
	150	"100kohm_to_gnd",
	151	"three_state",
fcf265d6 LPC	152	};
fcf265d6 LPC	153
26628f6b LPC	154	static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev,
26628f6b LPC	155	const struct iio_chan_spec *chan)
fcf265d6	156	{
fcf265d6 LPC	157	struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6 LPC	158
26628f6b	159	return st->pwr_down_mode[chan->channel] - 1;
fcf265d6 LPC	160	}
fcf265d6 LPC	161
26628f6b LPC	162	static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev,
26628f6b LPC	163	const struct iio_chan_spec *chan, unsigned int mode)
fcf265d6	164	{
fcf265d6	165	struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6 LPC	166	int ret;
fcf265d6 LPC	167
fcf265d6	168	mutex_lock(&indio_dev->mlock);
26628f6b	169	st->pwr_down_mode[chan->channel] = mode + 1;
fcf265d6	170
a2630262	171	ret = ad5064_sync_powerdown_mode(st, chan);
fcf265d6 LPC	172	mutex_unlock(&indio_dev->mlock);
fcf265d6 LPC	173
26628f6b	174	return ret;
fcf265d6 LPC	175	}
fcf265d6 LPC	176
26628f6b LPC	177	static const struct iio_enum ad5064_powerdown_mode_enum = {
	178	.items = ad5064_powerdown_modes,
	179	.num_items = ARRAY_SIZE(ad5064_powerdown_modes),
	180	.get = ad5064_get_powerdown_mode,
	181	.set = ad5064_set_powerdown_mode,
	182	};
	183
1d0d8794	184	static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
fc6d1139	185	uintptr_t private, const struct iio_chan_spec chan, char buf)
fcf265d6	186	{
fcf265d6	187	struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6	188
1d0d8794	189	return sprintf(buf, "%d\n", st->pwr_down[chan->channel]);
fcf265d6 LPC	190	}
fcf265d6 LPC	191
1d0d8794	192	static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
fc6d1139 MH	193	uintptr_t private, const struct iio_chan_spec chan, const char buf,
fc6d1139 MH	194	size_t len)
fcf265d6	195	{
fcf265d6	196	struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6 LPC	197	bool pwr_down;
	198	int ret;
	199
	200	ret = strtobool(buf, &pwr_down);
	201	if (ret)
	202	return ret;
	203
	204	mutex_lock(&indio_dev->mlock);
1d0d8794	205	st->pwr_down[chan->channel] = pwr_down;
fcf265d6	206
a2630262	207	ret = ad5064_sync_powerdown_mode(st, chan);
fcf265d6 LPC	208	mutex_unlock(&indio_dev->mlock);
	209	return ret ? ret : len;
	210	}
	211
bb92ff3e LPC	212	static int ad5064_get_vref(struct ad5064_state *st,
	213	struct iio_chan_spec const *chan)
	214	{
	215	unsigned int i;
	216
	217	if (st->use_internal_vref)
	218	return st->chip_info->internal_vref;
	219
	220	i = st->chip_info->shared_vref ? 0 : chan->channel;
	221	return regulator_get_voltage(st->vref_reg[i].consumer);
	222	}
	223
fcf265d6 LPC	224	static int ad5064_read_raw(struct iio_dev *indio_dev,
	225	struct iio_chan_spec const *chan,
	226	int *val,
	227	int *val2,
	228	long m)
	229	{
	230	struct ad5064_state *st = iio_priv(indio_dev);
23a3b8cc	231	int scale_uv;
fcf265d6 LPC	232
fcf265d6 LPC	233	switch (m) {
09f4eb40	234	case IIO_CHAN_INFO_RAW:
fcf265d6 LPC	235	*val = st->dac_cache[chan->channel];
fcf265d6 LPC	236	return IIO_VAL_INT;
c8a9f805	237	case IIO_CHAN_INFO_SCALE:
bb92ff3e	238	scale_uv = ad5064_get_vref(st, chan);
fcf265d6 LPC	239	if (scale_uv < 0)
	240	return scale_uv;
	241
	242	scale_uv = (scale_uv * 100) >> chan->scan_type.realbits;
	243	*val = scale_uv / 100000;
	244	val2 = (scale_uv % 100000) 10;
	245	return IIO_VAL_INT_PLUS_MICRO;
	246	default:
	247	break;
	248	}
	249	return -EINVAL;
	250	}
	251
	252	static int ad5064_write_raw(struct iio_dev *indio_dev,
	253	struct iio_chan_spec const *chan, int val, int val2, long mask)
	254	{
	255	struct ad5064_state *st = iio_priv(indio_dev);
	256	int ret;
	257
	258	switch (mask) {
09f4eb40	259	case IIO_CHAN_INFO_RAW:
c5ef717a	260	if (val >= (1 << chan->scan_type.realbits) \|\| val < 0)
fcf265d6 LPC	261	return -EINVAL;
	262
	263	mutex_lock(&indio_dev->mlock);
6a17a076	264	ret = ad5064_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
fcf265d6 LPC	265	chan->address, val, chan->scan_type.shift);
	266	if (ret == 0)
	267	st->dac_cache[chan->channel] = val;
	268	mutex_unlock(&indio_dev->mlock);
	269	break;
	270	default:
	271	ret = -EINVAL;
	272	}
	273
	274	return ret;
	275	}
	276
	277	static const struct iio_info ad5064_info = {
	278	.read_raw = ad5064_read_raw,
	279	.write_raw = ad5064_write_raw,
fcf265d6 LPC	280	.driver_module = THIS_MODULE,
	281	};
	282
26628f6b	283	static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
1d0d8794 LPC	284	{
	285	.name = "powerdown",
	286	.read = ad5064_read_dac_powerdown,
	287	.write = ad5064_write_dac_powerdown,
	288	},
26628f6b LPC	289	IIO_ENUM("powerdown_mode", false, &ad5064_powerdown_mode_enum),
26628f6b LPC	290	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5064_powerdown_mode_enum),
1d0d8794 LPC	291	{ },
	292	};
	293
a2630262	294	#define AD5064_CHANNEL(chan, addr, bits) { \
1d0d8794 LPC	295	.type = IIO_VOLTAGE, \
	296	.indexed = 1, \
	297	.output = 1, \
	298	.channel = (chan), \
09f4eb40 JC	299	.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT \| \
09f4eb40 JC	300	IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \
a2630262	301	.address = addr, \
1d0d8794 LPC	302	.scan_type = IIO_ST('u', (bits), 16, 20 - (bits)), \
	303	.ext_info = ad5064_ext_info, \
	304	}
	305
83c169d5 LPC	306	#define DECLARE_AD5064_CHANNELS(name, bits) \
83c169d5 LPC	307	const struct iio_chan_spec name[] = { \
a2630262 LPC	308	AD5064_CHANNEL(0, 0, bits), \
	309	AD5064_CHANNEL(1, 1, bits), \
	310	AD5064_CHANNEL(2, 2, bits), \
	311	AD5064_CHANNEL(3, 3, bits), \
	312	AD5064_CHANNEL(4, 4, bits), \
	313	AD5064_CHANNEL(5, 5, bits), \
	314	AD5064_CHANNEL(6, 6, bits), \
	315	AD5064_CHANNEL(7, 7, bits), \
	316	}
	317
	318	#define DECLARE_AD5065_CHANNELS(name, bits) \
	319	const struct iio_chan_spec name[] = { \
	320	AD5064_CHANNEL(0, 0, bits), \
	321	AD5064_CHANNEL(1, 3, bits), \
83c169d5 LPC	322	}
	323
	324	static DECLARE_AD5064_CHANNELS(ad5024_channels, 12);
	325	static DECLARE_AD5064_CHANNELS(ad5044_channels, 14);
	326	static DECLARE_AD5064_CHANNELS(ad5064_channels, 16);
	327
a2630262 LPC	328	static DECLARE_AD5065_CHANNELS(ad5025_channels, 12);
	329	static DECLARE_AD5065_CHANNELS(ad5045_channels, 14);
	330	static DECLARE_AD5065_CHANNELS(ad5065_channels, 16);
	331
1d0d8794 LPC	332	static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
	333	[ID_AD5024] = {
	334	.shared_vref = false,
83c169d5 LPC	335	.channels = ad5024_channels,
83c169d5 LPC	336	.num_channels = 4,
1d0d8794	337	},
f8be4af1 LPC	338	[ID_AD5025] = {
f8be4af1 LPC	339	.shared_vref = false,
a2630262	340	.channels = ad5025_channels,
f8be4af1 LPC	341	.num_channels = 2,
f8be4af1 LPC	342	},
1d0d8794 LPC	343	[ID_AD5044] = {
1d0d8794 LPC	344	.shared_vref = false,
83c169d5 LPC	345	.channels = ad5044_channels,
83c169d5 LPC	346	.num_channels = 4,
1d0d8794	347	},
f8be4af1 LPC	348	[ID_AD5045] = {
f8be4af1 LPC	349	.shared_vref = false,
a2630262	350	.channels = ad5045_channels,
f8be4af1 LPC	351	.num_channels = 2,
f8be4af1 LPC	352	},
1d0d8794 LPC	353	[ID_AD5064] = {
1d0d8794 LPC	354	.shared_vref = false,
83c169d5 LPC	355	.channels = ad5064_channels,
83c169d5 LPC	356	.num_channels = 4,
1d0d8794 LPC	357	},
	358	[ID_AD5064_1] = {
	359	.shared_vref = true,
83c169d5 LPC	360	.channels = ad5064_channels,
83c169d5 LPC	361	.num_channels = 4,
1d0d8794	362	},
f8be4af1 LPC	363	[ID_AD5065] = {
f8be4af1 LPC	364	.shared_vref = false,
a2630262	365	.channels = ad5065_channels,
f8be4af1 LPC	366	.num_channels = 2,
f8be4af1 LPC	367	},
bb92ff3e LPC	368	[ID_AD5628_1] = {
	369	.shared_vref = true,
	370	.internal_vref = 2500000,
	371	.channels = ad5024_channels,
	372	.num_channels = 8,
	373	},
	374	[ID_AD5628_2] = {
	375	.shared_vref = true,
	376	.internal_vref = 5000000,
	377	.channels = ad5024_channels,
	378	.num_channels = 8,
	379	},
	380	[ID_AD5648_1] = {
	381	.shared_vref = true,
	382	.internal_vref = 2500000,
	383	.channels = ad5044_channels,
	384	.num_channels = 8,
	385	},
	386	[ID_AD5648_2] = {
	387	.shared_vref = true,
	388	.internal_vref = 5000000,
	389	.channels = ad5044_channels,
	390	.num_channels = 8,
	391	},
64f4eaa5 LPC	392	[ID_AD5666_1] = {
	393	.shared_vref = true,
	394	.internal_vref = 2500000,
	395	.channels = ad5064_channels,
	396	.num_channels = 4,
	397	},
	398	[ID_AD5666_2] = {
	399	.shared_vref = true,
	400	.internal_vref = 5000000,
	401	.channels = ad5064_channels,
	402	.num_channels = 4,
	403	},
bb92ff3e LPC	404	[ID_AD5668_1] = {
	405	.shared_vref = true,
	406	.internal_vref = 2500000,
	407	.channels = ad5064_channels,
	408	.num_channels = 8,
	409	},
	410	[ID_AD5668_2] = {
	411	.shared_vref = true,
	412	.internal_vref = 5000000,
	413	.channels = ad5064_channels,
	414	.num_channels = 8,
	415	},
1d0d8794 LPC	416	};
1d0d8794 LPC	417
fcf265d6 LPC	418	static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
fcf265d6 LPC	419	{
83c169d5	420	return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
fcf265d6 LPC	421	}
	422
	423	static const char * const ad5064_vref_names[] = {
	424	"vrefA",
	425	"vrefB",
	426	"vrefC",
	427	"vrefD",
	428	};
	429
	430	static const char * const ad5064_vref_name(struct ad5064_state *st,
	431	unsigned int vref)
	432	{
	433	return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
	434	}
	435
fc52692c GKH	436	static int ad5064_probe(struct device *dev, enum ad5064_type type,
fc52692c GKH	437	const char *name, ad5064_write_func write)
fcf265d6	438	{
fcf265d6 LPC	439	struct iio_dev *indio_dev;
	440	struct ad5064_state *st;
	441	unsigned int i;
	442	int ret;
	443
7cbb7537	444	indio_dev = iio_device_alloc(sizeof(*st));
fcf265d6 LPC	445	if (indio_dev == NULL)
	446	return -ENOMEM;
	447
	448	st = iio_priv(indio_dev);
6a17a076	449	dev_set_drvdata(dev, indio_dev);
fcf265d6 LPC	450
fcf265d6 LPC	451	st->chip_info = &ad5064_chip_info_tbl[type];
6a17a076 LPC	452	st->dev = dev;
6a17a076 LPC	453	st->write = write;
fcf265d6 LPC	454
	455	for (i = 0; i < ad5064_num_vref(st); ++i)
	456	st->vref_reg[i].supply = ad5064_vref_name(st, i);
	457
6a17a076	458	ret = regulator_bulk_get(dev, ad5064_num_vref(st),
fcf265d6	459	st->vref_reg);
bb92ff3e LPC	460	if (ret) {
	461	if (!st->chip_info->internal_vref)
	462	goto error_free;
	463	st->use_internal_vref = true;
6a17a076	464	ret = ad5064_write(st, AD5064_CMD_CONFIG, 0,
bb92ff3e LPC	465	AD5064_CONFIG_INT_VREF_ENABLE, 0);
bb92ff3e LPC	466	if (ret) {
6a17a076	467	dev_err(dev, "Failed to enable internal vref: %d\n",
bb92ff3e LPC	468	ret);
	469	goto error_free;
	470	}
	471	} else {
	472	ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
	473	if (ret)
	474	goto error_free_reg;
	475	}
fcf265d6	476
83c169d5	477	for (i = 0; i < st->chip_info->num_channels; ++i) {
fcf265d6 LPC	478	st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
	479	st->dac_cache[i] = 0x8000;
	480	}
	481
6a17a076 LPC	482	indio_dev->dev.parent = dev;
6a17a076 LPC	483	indio_dev->name = name;
fcf265d6 LPC	484	indio_dev->info = &ad5064_info;
fcf265d6 LPC	485	indio_dev->modes = INDIO_DIRECT_MODE;
83c169d5 LPC	486	indio_dev->channels = st->chip_info->channels;
83c169d5 LPC	487	indio_dev->num_channels = st->chip_info->num_channels;
fcf265d6 LPC	488
	489	ret = iio_device_register(indio_dev);
	490	if (ret)
	491	goto error_disable_reg;
	492
	493	return 0;
	494
	495	error_disable_reg:
bb92ff3e LPC	496	if (!st->use_internal_vref)
bb92ff3e LPC	497	regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
fcf265d6	498	error_free_reg:
bb92ff3e LPC	499	if (!st->use_internal_vref)
bb92ff3e LPC	500	regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
fcf265d6	501	error_free:
7cbb7537	502	iio_device_free(indio_dev);
fcf265d6 LPC	503
	504	return ret;
	505	}
	506
fc52692c	507	static int ad5064_remove(struct device *dev)
fcf265d6	508	{
6a17a076	509	struct iio_dev *indio_dev = dev_get_drvdata(dev);
fcf265d6 LPC	510	struct ad5064_state *st = iio_priv(indio_dev);
	511
	512	iio_device_unregister(indio_dev);
	513
bb92ff3e LPC	514	if (!st->use_internal_vref) {
	515	regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
	516	regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
	517	}
fcf265d6	518
7cbb7537	519	iio_device_free(indio_dev);
fcf265d6 LPC	520
	521	return 0;
	522	}
	523
6a17a076 LPC	524	#if IS_ENABLED(CONFIG_SPI_MASTER)
6a17a076 LPC	525
9660ac70 LPC	526	static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
	527	unsigned int addr, unsigned int val)
	528	{
	529	struct spi_device *spi = to_spi_device(st->dev);
	530
	531	st->data.spi = cpu_to_be32(AD5064_CMD(cmd) \| AD5064_ADDR(addr) \| val);
	532	return spi_write(spi, &st->data.spi, sizeof(st->data.spi));
	533	}
	534
fc52692c	535	static int ad5064_spi_probe(struct spi_device *spi)
6a17a076 LPC	536	{
	537	const struct spi_device_id *id = spi_get_device_id(spi);
	538
	539	return ad5064_probe(&spi->dev, id->driver_data, id->name,
	540	ad5064_spi_write);
	541	}
	542
fc52692c	543	static int ad5064_spi_remove(struct spi_device *spi)
6a17a076 LPC	544	{
	545	return ad5064_remove(&spi->dev);
	546	}
	547
	548	static const struct spi_device_id ad5064_spi_ids[] = {
fcf265d6	549	{"ad5024", ID_AD5024},
f8be4af1	550	{"ad5025", ID_AD5025},
fcf265d6	551	{"ad5044", ID_AD5044},
f8be4af1	552	{"ad5045", ID_AD5045},
fcf265d6 LPC	553	{"ad5064", ID_AD5064},
fcf265d6 LPC	554	{"ad5064-1", ID_AD5064_1},
f8be4af1	555	{"ad5065", ID_AD5065},
bb92ff3e LPC	556	{"ad5628-1", ID_AD5628_1},
	557	{"ad5628-2", ID_AD5628_2},
	558	{"ad5648-1", ID_AD5648_1},
	559	{"ad5648-2", ID_AD5648_2},
64f4eaa5 LPC	560	{"ad5666-1", ID_AD5666_1},
64f4eaa5 LPC	561	{"ad5666-2", ID_AD5666_2},
bb92ff3e LPC	562	{"ad5668-1", ID_AD5668_1},
	563	{"ad5668-2", ID_AD5668_2},
	564	{"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */
fcf265d6 LPC	565	{}
fcf265d6 LPC	566	};
6a17a076	567	MODULE_DEVICE_TABLE(spi, ad5064_spi_ids);
fcf265d6	568
6a17a076	569	static struct spi_driver ad5064_spi_driver = {
fcf265d6 LPC	570	.driver = {
	571	.name = "ad5064",
	572	.owner = THIS_MODULE,
	573	},
6a17a076	574	.probe = ad5064_spi_probe,
fc52692c	575	.remove = ad5064_spi_remove,
6a17a076	576	.id_table = ad5064_spi_ids,
fcf265d6	577	};
6a17a076 LPC	578
	579	static int __init ad5064_spi_register_driver(void)
	580	{
	581	return spi_register_driver(&ad5064_spi_driver);
	582	}
	583
21fa54e4	584	static void ad5064_spi_unregister_driver(void)
6a17a076 LPC	585	{
	586	spi_unregister_driver(&ad5064_spi_driver);
	587	}
	588
	589	#else
	590
	591	static inline int ad5064_spi_register_driver(void) { return 0; }
	592	static inline void ad5064_spi_unregister_driver(void) { }
	593
	594	#endif
	595
	596	#if IS_ENABLED(CONFIG_I2C)
	597
9660ac70 LPC	598	static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd,
	599	unsigned int addr, unsigned int val)
	600	{
	601	struct i2c_client *i2c = to_i2c_client(st->dev);
	602
	603	st->data.i2c[0] = (cmd << 4) \| addr;
	604	put_unaligned_be16(val, &st->data.i2c[1]);
	605	return i2c_master_send(i2c, st->data.i2c, 3);
	606	}
	607
fc52692c	608	static int ad5064_i2c_probe(struct i2c_client *i2c,
6a17a076 LPC	609	const struct i2c_device_id *id)
	610	{
	611	return ad5064_probe(&i2c->dev, id->driver_data, id->name,
	612	ad5064_i2c_write);
	613	}
	614
fc52692c	615	static int ad5064_i2c_remove(struct i2c_client *i2c)
6a17a076 LPC	616	{
	617	return ad5064_remove(&i2c->dev);
	618	}
	619
	620	static const struct i2c_device_id ad5064_i2c_ids[] = {
	621	{"ad5629-1", ID_AD5628_1},
	622	{"ad5629-2", ID_AD5628_2},
	623	{"ad5629-3", ID_AD5628_2}, /* similar enough to ad5629-2 */
	624	{"ad5669-1", ID_AD5668_1},
	625	{"ad5669-2", ID_AD5668_2},
	626	{"ad5669-3", ID_AD5668_2}, /* similar enough to ad5669-2 */
	627	{}
	628	};
	629	MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids);
	630
	631	static struct i2c_driver ad5064_i2c_driver = {
	632	.driver = {
	633	.name = "ad5064",
	634	.owner = THIS_MODULE,
	635	},
	636	.probe = ad5064_i2c_probe,
fc52692c	637	.remove = ad5064_i2c_remove,
6a17a076 LPC	638	.id_table = ad5064_i2c_ids,
	639	};
	640
	641	static int __init ad5064_i2c_register_driver(void)
	642	{
	643	return i2c_add_driver(&ad5064_i2c_driver);
	644	}
	645
	646	static void __exit ad5064_i2c_unregister_driver(void)
	647	{
	648	i2c_del_driver(&ad5064_i2c_driver);
	649	}
	650
	651	#else
	652
	653	static inline int ad5064_i2c_register_driver(void) { return 0; }
	654	static inline void ad5064_i2c_unregister_driver(void) { }
	655
	656	#endif
	657
	658	static int __init ad5064_init(void)
	659	{
	660	int ret;
	661
	662	ret = ad5064_spi_register_driver();
	663	if (ret)
	664	return ret;
	665
	666	ret = ad5064_i2c_register_driver();
	667	if (ret) {
	668	ad5064_spi_unregister_driver();
	669	return ret;
	670	}
	671
	672	return 0;
	673	}
	674	module_init(ad5064_init);
	675
	676	static void __exit ad5064_exit(void)
	677	{
	678	ad5064_i2c_unregister_driver();
	679	ad5064_spi_unregister_driver();
	680	}
	681	module_exit(ad5064_exit);
fcf265d6 LPC	682
fcf265d6 LPC	683	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
6a17a076	684	MODULE_DESCRIPTION("Analog Devices AD5024 and similar multi-channel DACs");
fcf265d6	685	MODULE_LICENSE("GPL v2");