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56ca9db8 PC |
1 | /* |
2 | * AD5592R Digital <-> Analog converters driver | |
3 | * | |
4 | * Copyright 2014-2016 Analog Devices Inc. | |
5 | * Author: Paul Cercueil <paul.cercueil@analog.com> | |
6 | * | |
7 | * Licensed under the GPL-2. | |
8 | */ | |
9 | ||
10 | #include <linux/bitops.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/iio/iio.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/mutex.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/regulator/consumer.h> | |
17 | #include <linux/gpio/consumer.h> | |
18 | #include <linux/gpio/driver.h> | |
19 | #include <linux/gpio.h> | |
20 | #include <linux/property.h> | |
21 | ||
22 | #include <dt-bindings/iio/adi,ad5592r.h> | |
23 | ||
24 | #include "ad5592r-base.h" | |
25 | ||
26 | static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset) | |
27 | { | |
28 | struct ad5592r_state *st = gpiochip_get_data(chip); | |
29 | int ret = 0; | |
30 | u8 val; | |
31 | ||
32 | mutex_lock(&st->gpio_lock); | |
33 | ||
34 | if (st->gpio_out & BIT(offset)) | |
35 | val = st->gpio_val; | |
36 | else | |
37 | ret = st->ops->gpio_read(st, &val); | |
38 | ||
39 | mutex_unlock(&st->gpio_lock); | |
40 | ||
41 | if (ret < 0) | |
42 | return ret; | |
43 | ||
44 | return !!(val & BIT(offset)); | |
45 | } | |
46 | ||
47 | static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
48 | { | |
49 | struct ad5592r_state *st = gpiochip_get_data(chip); | |
50 | ||
51 | mutex_lock(&st->gpio_lock); | |
52 | ||
53 | if (value) | |
54 | st->gpio_val |= BIT(offset); | |
55 | else | |
56 | st->gpio_val &= ~BIT(offset); | |
57 | ||
58 | st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); | |
59 | ||
60 | mutex_unlock(&st->gpio_lock); | |
61 | } | |
62 | ||
63 | static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
64 | { | |
65 | struct ad5592r_state *st = gpiochip_get_data(chip); | |
66 | int ret; | |
67 | ||
68 | mutex_lock(&st->gpio_lock); | |
69 | ||
70 | st->gpio_out &= ~BIT(offset); | |
71 | st->gpio_in |= BIT(offset); | |
72 | ||
73 | ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); | |
74 | if (ret < 0) | |
75 | goto err_unlock; | |
76 | ||
77 | ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); | |
78 | ||
79 | err_unlock: | |
80 | mutex_unlock(&st->gpio_lock); | |
81 | ||
82 | return ret; | |
83 | } | |
84 | ||
85 | static int ad5592r_gpio_direction_output(struct gpio_chip *chip, | |
86 | unsigned offset, int value) | |
87 | { | |
88 | struct ad5592r_state *st = gpiochip_get_data(chip); | |
89 | int ret; | |
90 | ||
91 | mutex_lock(&st->gpio_lock); | |
92 | ||
93 | if (value) | |
94 | st->gpio_val |= BIT(offset); | |
95 | else | |
96 | st->gpio_val &= ~BIT(offset); | |
97 | ||
98 | st->gpio_in &= ~BIT(offset); | |
99 | st->gpio_out |= BIT(offset); | |
100 | ||
101 | ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); | |
102 | if (ret < 0) | |
103 | goto err_unlock; | |
104 | ||
105 | ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); | |
106 | if (ret < 0) | |
107 | goto err_unlock; | |
108 | ||
109 | ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); | |
110 | ||
111 | err_unlock: | |
112 | mutex_unlock(&st->gpio_lock); | |
113 | ||
114 | return ret; | |
115 | } | |
116 | ||
117 | static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset) | |
118 | { | |
119 | struct ad5592r_state *st = gpiochip_get_data(chip); | |
120 | ||
121 | if (!(st->gpio_map & BIT(offset))) { | |
122 | dev_err(st->dev, "GPIO %d is reserved by alternate function\n", | |
123 | offset); | |
124 | return -ENODEV; | |
125 | } | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
130 | static int ad5592r_gpio_init(struct ad5592r_state *st) | |
131 | { | |
132 | if (!st->gpio_map) | |
133 | return 0; | |
134 | ||
135 | st->gpiochip.label = dev_name(st->dev); | |
136 | st->gpiochip.base = -1; | |
137 | st->gpiochip.ngpio = 8; | |
138 | st->gpiochip.parent = st->dev; | |
139 | st->gpiochip.can_sleep = true; | |
140 | st->gpiochip.direction_input = ad5592r_gpio_direction_input; | |
141 | st->gpiochip.direction_output = ad5592r_gpio_direction_output; | |
142 | st->gpiochip.get = ad5592r_gpio_get; | |
143 | st->gpiochip.set = ad5592r_gpio_set; | |
144 | st->gpiochip.request = ad5592r_gpio_request; | |
145 | st->gpiochip.owner = THIS_MODULE; | |
146 | ||
147 | mutex_init(&st->gpio_lock); | |
148 | ||
149 | return gpiochip_add_data(&st->gpiochip, st); | |
150 | } | |
151 | ||
152 | static void ad5592r_gpio_cleanup(struct ad5592r_state *st) | |
153 | { | |
154 | if (st->gpio_map) | |
155 | gpiochip_remove(&st->gpiochip); | |
156 | } | |
157 | ||
158 | static int ad5592r_reset(struct ad5592r_state *st) | |
159 | { | |
160 | struct gpio_desc *gpio; | |
161 | struct iio_dev *iio_dev = iio_priv_to_dev(st); | |
162 | ||
163 | gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW); | |
164 | if (IS_ERR(gpio)) | |
165 | return PTR_ERR(gpio); | |
166 | ||
167 | if (gpio) { | |
168 | udelay(1); | |
169 | gpiod_set_value(gpio, 1); | |
170 | } else { | |
171 | mutex_lock(&iio_dev->mlock); | |
172 | /* Writing this magic value resets the device */ | |
173 | st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); | |
174 | mutex_unlock(&iio_dev->mlock); | |
175 | } | |
176 | ||
177 | udelay(250); | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static int ad5592r_get_vref(struct ad5592r_state *st) | |
183 | { | |
184 | int ret; | |
185 | ||
186 | if (st->reg) { | |
187 | ret = regulator_get_voltage(st->reg); | |
188 | if (ret < 0) | |
189 | return ret; | |
190 | ||
191 | return ret / 1000; | |
192 | } else { | |
193 | return 2500; | |
194 | } | |
195 | } | |
196 | ||
197 | static int ad5592r_set_channel_modes(struct ad5592r_state *st) | |
198 | { | |
199 | const struct ad5592r_rw_ops *ops = st->ops; | |
200 | int ret; | |
201 | unsigned i; | |
202 | struct iio_dev *iio_dev = iio_priv_to_dev(st); | |
203 | u8 pulldown = 0, tristate = 0, dac = 0, adc = 0; | |
204 | u16 read_back; | |
205 | ||
206 | for (i = 0; i < st->num_channels; i++) { | |
207 | switch (st->channel_modes[i]) { | |
208 | case CH_MODE_DAC: | |
209 | dac |= BIT(i); | |
210 | break; | |
211 | ||
212 | case CH_MODE_ADC: | |
213 | adc |= BIT(i); | |
214 | break; | |
215 | ||
216 | case CH_MODE_DAC_AND_ADC: | |
217 | dac |= BIT(i); | |
218 | adc |= BIT(i); | |
219 | break; | |
220 | ||
221 | case CH_MODE_GPIO: | |
222 | st->gpio_map |= BIT(i); | |
223 | st->gpio_in |= BIT(i); /* Default to input */ | |
224 | break; | |
225 | ||
226 | case CH_MODE_UNUSED: | |
227 | /* fall-through */ | |
228 | default: | |
229 | switch (st->channel_offstate[i]) { | |
230 | case CH_OFFSTATE_OUT_TRISTATE: | |
231 | tristate |= BIT(i); | |
232 | break; | |
233 | ||
234 | case CH_OFFSTATE_OUT_LOW: | |
235 | st->gpio_out |= BIT(i); | |
236 | break; | |
237 | ||
238 | case CH_OFFSTATE_OUT_HIGH: | |
239 | st->gpio_out |= BIT(i); | |
240 | st->gpio_val |= BIT(i); | |
241 | break; | |
242 | ||
243 | case CH_OFFSTATE_PULLDOWN: | |
244 | /* fall-through */ | |
245 | default: | |
246 | pulldown |= BIT(i); | |
247 | break; | |
248 | } | |
249 | } | |
250 | } | |
251 | ||
252 | mutex_lock(&iio_dev->mlock); | |
253 | ||
254 | /* Pull down unused pins to GND */ | |
255 | ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); | |
256 | if (ret) | |
257 | goto err_unlock; | |
258 | ||
259 | ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); | |
260 | if (ret) | |
261 | goto err_unlock; | |
262 | ||
263 | /* Configure pins that we use */ | |
264 | ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac); | |
265 | if (ret) | |
266 | goto err_unlock; | |
267 | ||
268 | ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc); | |
269 | if (ret) | |
270 | goto err_unlock; | |
271 | ||
272 | ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); | |
273 | if (ret) | |
274 | goto err_unlock; | |
275 | ||
276 | ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); | |
277 | if (ret) | |
278 | goto err_unlock; | |
279 | ||
280 | ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); | |
281 | if (ret) | |
282 | goto err_unlock; | |
283 | ||
284 | /* Verify that we can read back at least one register */ | |
285 | ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back); | |
286 | if (!ret && (read_back & 0xff) != adc) | |
287 | ret = -EIO; | |
288 | ||
289 | err_unlock: | |
290 | mutex_unlock(&iio_dev->mlock); | |
291 | return ret; | |
292 | } | |
293 | ||
294 | static int ad5592r_reset_channel_modes(struct ad5592r_state *st) | |
295 | { | |
296 | int i; | |
297 | ||
298 | for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++) | |
299 | st->channel_modes[i] = CH_MODE_UNUSED; | |
300 | ||
301 | return ad5592r_set_channel_modes(st); | |
302 | } | |
303 | ||
304 | static int ad5592r_write_raw(struct iio_dev *iio_dev, | |
305 | struct iio_chan_spec const *chan, int val, int val2, long mask) | |
306 | { | |
307 | struct ad5592r_state *st = iio_priv(iio_dev); | |
308 | int ret; | |
309 | ||
310 | switch (mask) { | |
311 | case IIO_CHAN_INFO_RAW: | |
312 | ||
313 | if (val >= (1 << chan->scan_type.realbits) || val < 0) | |
314 | return -EINVAL; | |
315 | ||
316 | if (!chan->output) | |
317 | return -EINVAL; | |
318 | ||
319 | mutex_lock(&iio_dev->mlock); | |
320 | ret = st->ops->write_dac(st, chan->channel, val); | |
321 | if (!ret) | |
322 | st->cached_dac[chan->channel] = val; | |
323 | mutex_unlock(&iio_dev->mlock); | |
324 | return ret; | |
325 | case IIO_CHAN_INFO_SCALE: | |
326 | if (chan->type == IIO_VOLTAGE) { | |
327 | bool gain; | |
328 | ||
329 | if (val == st->scale_avail[0][0] && | |
330 | val2 == st->scale_avail[0][1]) | |
331 | gain = false; | |
332 | else if (val == st->scale_avail[1][0] && | |
333 | val2 == st->scale_avail[1][1]) | |
334 | gain = true; | |
335 | else | |
336 | return -EINVAL; | |
337 | ||
338 | mutex_lock(&iio_dev->mlock); | |
339 | ||
340 | ret = st->ops->reg_read(st, AD5592R_REG_CTRL, | |
341 | &st->cached_gp_ctrl); | |
342 | if (ret < 0) { | |
343 | mutex_unlock(&iio_dev->mlock); | |
344 | return ret; | |
345 | } | |
346 | ||
347 | if (chan->output) { | |
348 | if (gain) | |
349 | st->cached_gp_ctrl |= | |
350 | AD5592R_REG_CTRL_DAC_RANGE; | |
351 | else | |
352 | st->cached_gp_ctrl &= | |
353 | ~AD5592R_REG_CTRL_DAC_RANGE; | |
354 | } else { | |
355 | if (gain) | |
356 | st->cached_gp_ctrl |= | |
357 | AD5592R_REG_CTRL_ADC_RANGE; | |
358 | else | |
359 | st->cached_gp_ctrl &= | |
360 | ~AD5592R_REG_CTRL_ADC_RANGE; | |
361 | } | |
362 | ||
363 | ret = st->ops->reg_write(st, AD5592R_REG_CTRL, | |
364 | st->cached_gp_ctrl); | |
365 | mutex_unlock(&iio_dev->mlock); | |
366 | ||
367 | return ret; | |
368 | } | |
369 | break; | |
370 | default: | |
371 | return -EINVAL; | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static int ad5592r_read_raw(struct iio_dev *iio_dev, | |
378 | struct iio_chan_spec const *chan, | |
379 | int *val, int *val2, long m) | |
380 | { | |
381 | struct ad5592r_state *st = iio_priv(iio_dev); | |
382 | u16 read_val; | |
383 | int ret; | |
384 | ||
385 | switch (m) { | |
386 | case IIO_CHAN_INFO_RAW: | |
387 | mutex_lock(&iio_dev->mlock); | |
388 | ||
389 | if (!chan->output) { | |
390 | ret = st->ops->read_adc(st, chan->channel, &read_val); | |
391 | if (ret) | |
392 | goto unlock; | |
393 | ||
394 | if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) { | |
395 | dev_err(st->dev, "Error while reading channel %u\n", | |
396 | chan->channel); | |
397 | ret = -EIO; | |
398 | goto unlock; | |
399 | } | |
400 | ||
401 | read_val &= GENMASK(11, 0); | |
402 | ||
403 | } else { | |
404 | read_val = st->cached_dac[chan->channel]; | |
405 | } | |
406 | ||
407 | dev_dbg(st->dev, "Channel %u read: 0x%04hX\n", | |
408 | chan->channel, read_val); | |
409 | ||
410 | *val = (int) read_val; | |
411 | ret = IIO_VAL_INT; | |
412 | break; | |
413 | case IIO_CHAN_INFO_SCALE: | |
414 | *val = ad5592r_get_vref(st); | |
415 | ||
416 | if (chan->type == IIO_TEMP) { | |
417 | s64 tmp = *val * (3767897513LL / 25LL); | |
418 | *val = div_s64_rem(tmp, 1000000000LL, val2); | |
419 | ||
420 | ret = IIO_VAL_INT_PLUS_MICRO; | |
421 | } else { | |
422 | int mult; | |
423 | ||
424 | mutex_lock(&iio_dev->mlock); | |
425 | ||
426 | if (chan->output) | |
427 | mult = !!(st->cached_gp_ctrl & | |
428 | AD5592R_REG_CTRL_DAC_RANGE); | |
429 | else | |
430 | mult = !!(st->cached_gp_ctrl & | |
431 | AD5592R_REG_CTRL_ADC_RANGE); | |
432 | ||
433 | *val *= ++mult; | |
434 | ||
435 | *val2 = chan->scan_type.realbits; | |
436 | ret = IIO_VAL_FRACTIONAL_LOG2; | |
437 | } | |
438 | break; | |
439 | case IIO_CHAN_INFO_OFFSET: | |
440 | ret = ad5592r_get_vref(st); | |
441 | ||
442 | mutex_lock(&iio_dev->mlock); | |
443 | ||
444 | if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE) | |
445 | *val = (-34365 * 25) / ret; | |
446 | else | |
447 | *val = (-75365 * 25) / ret; | |
448 | ret = IIO_VAL_INT; | |
449 | break; | |
450 | default: | |
451 | ret = -EINVAL; | |
452 | } | |
453 | ||
454 | unlock: | |
455 | mutex_unlock(&iio_dev->mlock); | |
456 | return ret; | |
457 | } | |
458 | ||
459 | static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev, | |
460 | struct iio_chan_spec const *chan, long mask) | |
461 | { | |
462 | switch (mask) { | |
463 | case IIO_CHAN_INFO_SCALE: | |
464 | return IIO_VAL_INT_PLUS_NANO; | |
465 | ||
466 | default: | |
467 | return IIO_VAL_INT_PLUS_MICRO; | |
468 | } | |
469 | ||
470 | return -EINVAL; | |
471 | } | |
472 | ||
473 | static const struct iio_info ad5592r_info = { | |
474 | .read_raw = ad5592r_read_raw, | |
475 | .write_raw = ad5592r_write_raw, | |
476 | .write_raw_get_fmt = ad5592r_write_raw_get_fmt, | |
56ca9db8 PC |
477 | }; |
478 | ||
479 | static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev, | |
480 | uintptr_t private, | |
481 | const struct iio_chan_spec *chan, | |
482 | char *buf) | |
483 | { | |
484 | struct ad5592r_state *st = iio_priv(iio_dev); | |
485 | ||
486 | return sprintf(buf, "%d.%09u %d.%09u\n", | |
487 | st->scale_avail[0][0], st->scale_avail[0][1], | |
488 | st->scale_avail[1][0], st->scale_avail[1][1]); | |
489 | } | |
490 | ||
491 | static struct iio_chan_spec_ext_info ad5592r_ext_info[] = { | |
492 | { | |
493 | .name = "scale_available", | |
494 | .read = ad5592r_show_scale_available, | |
495 | .shared = true, | |
496 | }, | |
497 | {}, | |
498 | }; | |
499 | ||
500 | static void ad5592r_setup_channel(struct iio_dev *iio_dev, | |
501 | struct iio_chan_spec *chan, bool output, unsigned id) | |
502 | { | |
503 | chan->type = IIO_VOLTAGE; | |
504 | chan->indexed = 1; | |
505 | chan->output = output; | |
506 | chan->channel = id; | |
507 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); | |
508 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); | |
509 | chan->scan_type.sign = 'u'; | |
510 | chan->scan_type.realbits = 12; | |
511 | chan->scan_type.storagebits = 16; | |
512 | chan->ext_info = ad5592r_ext_info; | |
513 | } | |
514 | ||
515 | static int ad5592r_alloc_channels(struct ad5592r_state *st) | |
516 | { | |
517 | unsigned i, curr_channel = 0, | |
518 | num_channels = st->num_channels; | |
519 | struct iio_dev *iio_dev = iio_priv_to_dev(st); | |
520 | struct iio_chan_spec *channels; | |
521 | struct fwnode_handle *child; | |
522 | u32 reg, tmp; | |
523 | int ret; | |
524 | ||
525 | device_for_each_child_node(st->dev, child) { | |
526 | ret = fwnode_property_read_u32(child, "reg", ®); | |
04bf0217 | 527 | if (ret || reg >= ARRAY_SIZE(st->channel_modes)) |
56ca9db8 PC |
528 | continue; |
529 | ||
530 | ret = fwnode_property_read_u32(child, "adi,mode", &tmp); | |
531 | if (!ret) | |
532 | st->channel_modes[reg] = tmp; | |
533 | ||
534 | fwnode_property_read_u32(child, "adi,off-state", &tmp); | |
535 | if (!ret) | |
536 | st->channel_offstate[reg] = tmp; | |
537 | } | |
538 | ||
a86854d0 KC |
539 | channels = devm_kcalloc(st->dev, |
540 | 1 + 2 * num_channels, sizeof(*channels), | |
541 | GFP_KERNEL); | |
56ca9db8 PC |
542 | if (!channels) |
543 | return -ENOMEM; | |
544 | ||
545 | for (i = 0; i < num_channels; i++) { | |
546 | switch (st->channel_modes[i]) { | |
547 | case CH_MODE_DAC: | |
548 | ad5592r_setup_channel(iio_dev, &channels[curr_channel], | |
549 | true, i); | |
550 | curr_channel++; | |
551 | break; | |
552 | ||
553 | case CH_MODE_ADC: | |
554 | ad5592r_setup_channel(iio_dev, &channels[curr_channel], | |
555 | false, i); | |
556 | curr_channel++; | |
557 | break; | |
558 | ||
559 | case CH_MODE_DAC_AND_ADC: | |
560 | ad5592r_setup_channel(iio_dev, &channels[curr_channel], | |
561 | true, i); | |
562 | curr_channel++; | |
563 | ad5592r_setup_channel(iio_dev, &channels[curr_channel], | |
564 | false, i); | |
565 | curr_channel++; | |
566 | break; | |
567 | ||
568 | default: | |
569 | continue; | |
570 | } | |
571 | } | |
572 | ||
573 | channels[curr_channel].type = IIO_TEMP; | |
574 | channels[curr_channel].channel = 8; | |
575 | channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | | |
576 | BIT(IIO_CHAN_INFO_SCALE) | | |
577 | BIT(IIO_CHAN_INFO_OFFSET); | |
578 | curr_channel++; | |
579 | ||
580 | iio_dev->num_channels = curr_channel; | |
581 | iio_dev->channels = channels; | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV) | |
587 | { | |
588 | s64 tmp = (s64)vref_mV * 1000000000LL >> 12; | |
589 | ||
590 | st->scale_avail[0][0] = | |
591 | div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]); | |
592 | st->scale_avail[1][0] = | |
593 | div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]); | |
594 | } | |
595 | ||
596 | int ad5592r_probe(struct device *dev, const char *name, | |
597 | const struct ad5592r_rw_ops *ops) | |
598 | { | |
599 | struct iio_dev *iio_dev; | |
600 | struct ad5592r_state *st; | |
601 | int ret; | |
602 | ||
603 | iio_dev = devm_iio_device_alloc(dev, sizeof(*st)); | |
604 | if (!iio_dev) | |
605 | return -ENOMEM; | |
606 | ||
607 | st = iio_priv(iio_dev); | |
608 | st->dev = dev; | |
609 | st->ops = ops; | |
610 | st->num_channels = 8; | |
611 | dev_set_drvdata(dev, iio_dev); | |
612 | ||
613 | st->reg = devm_regulator_get_optional(dev, "vref"); | |
614 | if (IS_ERR(st->reg)) { | |
615 | if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node) | |
616 | return PTR_ERR(st->reg); | |
617 | ||
618 | st->reg = NULL; | |
619 | } else { | |
620 | ret = regulator_enable(st->reg); | |
621 | if (ret) | |
622 | return ret; | |
623 | } | |
624 | ||
625 | iio_dev->dev.parent = dev; | |
626 | iio_dev->name = name; | |
627 | iio_dev->info = &ad5592r_info; | |
628 | iio_dev->modes = INDIO_DIRECT_MODE; | |
629 | ||
630 | ad5592r_init_scales(st, ad5592r_get_vref(st)); | |
631 | ||
632 | ret = ad5592r_reset(st); | |
633 | if (ret) | |
634 | goto error_disable_reg; | |
635 | ||
636 | ret = ops->reg_write(st, AD5592R_REG_PD, | |
637 | (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0); | |
638 | if (ret) | |
639 | goto error_disable_reg; | |
640 | ||
641 | ret = ad5592r_alloc_channels(st); | |
642 | if (ret) | |
643 | goto error_disable_reg; | |
644 | ||
645 | ret = ad5592r_set_channel_modes(st); | |
646 | if (ret) | |
647 | goto error_reset_ch_modes; | |
648 | ||
649 | ret = iio_device_register(iio_dev); | |
650 | if (ret) | |
651 | goto error_reset_ch_modes; | |
652 | ||
653 | ret = ad5592r_gpio_init(st); | |
654 | if (ret) | |
655 | goto error_dev_unregister; | |
656 | ||
657 | return 0; | |
658 | ||
659 | error_dev_unregister: | |
660 | iio_device_unregister(iio_dev); | |
661 | ||
662 | error_reset_ch_modes: | |
663 | ad5592r_reset_channel_modes(st); | |
664 | ||
665 | error_disable_reg: | |
666 | if (st->reg) | |
667 | regulator_disable(st->reg); | |
668 | ||
669 | return ret; | |
670 | } | |
671 | EXPORT_SYMBOL_GPL(ad5592r_probe); | |
672 | ||
673 | int ad5592r_remove(struct device *dev) | |
674 | { | |
675 | struct iio_dev *iio_dev = dev_get_drvdata(dev); | |
676 | struct ad5592r_state *st = iio_priv(iio_dev); | |
677 | ||
678 | iio_device_unregister(iio_dev); | |
679 | ad5592r_reset_channel_modes(st); | |
680 | ad5592r_gpio_cleanup(st); | |
681 | ||
682 | if (st->reg) | |
683 | regulator_disable(st->reg); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | EXPORT_SYMBOL_GPL(ad5592r_remove); | |
688 | ||
689 | MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>"); | |
690 | MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters"); | |
691 | MODULE_LICENSE("GPL v2"); |