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22b46c45 SP |
1 | /* |
2 | * BMG160 Gyro Sensor driver | |
3 | * Copyright (c) 2014, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
22b46c45 SP |
16 | #include <linux/interrupt.h> |
17 | #include <linux/delay.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/acpi.h> | |
22b46c45 SP |
20 | #include <linux/pm.h> |
21 | #include <linux/pm_runtime.h> | |
22 | #include <linux/iio/iio.h> | |
23 | #include <linux/iio/sysfs.h> | |
24 | #include <linux/iio/buffer.h> | |
25 | #include <linux/iio/trigger.h> | |
26 | #include <linux/iio/events.h> | |
27 | #include <linux/iio/trigger_consumer.h> | |
28 | #include <linux/iio/triggered_buffer.h> | |
c6c9e995 | 29 | #include <linux/regmap.h> |
4bdc9029 | 30 | #include <linux/delay.h> |
13426454 | 31 | #include "bmg160.h" |
22b46c45 | 32 | |
22b46c45 | 33 | #define BMG160_IRQ_NAME "bmg160_event" |
22b46c45 SP |
34 | |
35 | #define BMG160_REG_CHIP_ID 0x00 | |
36 | #define BMG160_CHIP_ID_VAL 0x0F | |
37 | ||
38 | #define BMG160_REG_PMU_LPW 0x11 | |
39 | #define BMG160_MODE_NORMAL 0x00 | |
40 | #define BMG160_MODE_DEEP_SUSPEND 0x20 | |
41 | #define BMG160_MODE_SUSPEND 0x80 | |
42 | ||
43 | #define BMG160_REG_RANGE 0x0F | |
44 | ||
45 | #define BMG160_RANGE_2000DPS 0 | |
46 | #define BMG160_RANGE_1000DPS 1 | |
47 | #define BMG160_RANGE_500DPS 2 | |
48 | #define BMG160_RANGE_250DPS 3 | |
49 | #define BMG160_RANGE_125DPS 4 | |
50 | ||
51 | #define BMG160_REG_PMU_BW 0x10 | |
52 | #define BMG160_NO_FILTER 0 | |
53 | #define BMG160_DEF_BW 100 | |
bf61f5d2 | 54 | #define BMG160_REG_PMU_BW_RES BIT(7) |
22b46c45 | 55 | |
4bdc9029 QS |
56 | #define BMG160_GYRO_REG_RESET 0x14 |
57 | #define BMG160_GYRO_RESET_VAL 0xb6 | |
58 | ||
22b46c45 SP |
59 | #define BMG160_REG_INT_MAP_0 0x17 |
60 | #define BMG160_INT_MAP_0_BIT_ANY BIT(1) | |
61 | ||
62 | #define BMG160_REG_INT_MAP_1 0x18 | |
63 | #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) | |
64 | ||
65 | #define BMG160_REG_INT_RST_LATCH 0x21 | |
66 | #define BMG160_INT_MODE_LATCH_RESET 0x80 | |
67 | #define BMG160_INT_MODE_LATCH_INT 0x0F | |
68 | #define BMG160_INT_MODE_NON_LATCH_INT 0x00 | |
69 | ||
70 | #define BMG160_REG_INT_EN_0 0x15 | |
71 | #define BMG160_DATA_ENABLE_INT BIT(7) | |
72 | ||
5af6b307 SP |
73 | #define BMG160_REG_INT_EN_1 0x16 |
74 | #define BMG160_INT1_BIT_OD BIT(1) | |
75 | ||
22b46c45 SP |
76 | #define BMG160_REG_XOUT_L 0x02 |
77 | #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) | |
78 | ||
79 | #define BMG160_REG_SLOPE_THRES 0x1B | |
80 | #define BMG160_SLOPE_THRES_MASK 0x0F | |
81 | ||
82 | #define BMG160_REG_MOTION_INTR 0x1C | |
83 | #define BMG160_INT_MOTION_X BIT(0) | |
84 | #define BMG160_INT_MOTION_Y BIT(1) | |
85 | #define BMG160_INT_MOTION_Z BIT(2) | |
86 | #define BMG160_ANY_DUR_MASK 0x30 | |
87 | #define BMG160_ANY_DUR_SHIFT 4 | |
88 | ||
89 | #define BMG160_REG_INT_STATUS_2 0x0B | |
90 | #define BMG160_ANY_MOTION_MASK 0x07 | |
cb80f6a3 SP |
91 | #define BMG160_ANY_MOTION_BIT_X BIT(0) |
92 | #define BMG160_ANY_MOTION_BIT_Y BIT(1) | |
93 | #define BMG160_ANY_MOTION_BIT_Z BIT(2) | |
22b46c45 SP |
94 | |
95 | #define BMG160_REG_TEMP 0x08 | |
96 | #define BMG160_TEMP_CENTER_VAL 23 | |
97 | ||
98 | #define BMG160_MAX_STARTUP_TIME_MS 80 | |
99 | ||
100 | #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 | |
101 | ||
102 | struct bmg160_data { | |
c6c9e995 | 103 | struct regmap *regmap; |
22b46c45 SP |
104 | struct iio_trigger *dready_trig; |
105 | struct iio_trigger *motion_trig; | |
106 | struct mutex mutex; | |
107 | s16 buffer[8]; | |
22b46c45 SP |
108 | u32 dps_range; |
109 | int ev_enable_state; | |
110 | int slope_thres; | |
111 | bool dready_trigger_on; | |
112 | bool motion_trigger_on; | |
5d889abb | 113 | int irq; |
22b46c45 SP |
114 | }; |
115 | ||
116 | enum bmg160_axis { | |
117 | AXIS_X, | |
118 | AXIS_Y, | |
119 | AXIS_Z, | |
ee8c5419 | 120 | AXIS_MAX, |
22b46c45 SP |
121 | }; |
122 | ||
123 | static const struct { | |
bf61f5d2 ST |
124 | int odr; |
125 | int filter; | |
22b46c45 | 126 | int bw_bits; |
bf61f5d2 ST |
127 | } bmg160_samp_freq_table[] = { {100, 32, 0x07}, |
128 | {200, 64, 0x06}, | |
129 | {100, 12, 0x05}, | |
130 | {200, 23, 0x04}, | |
131 | {400, 47, 0x03}, | |
132 | {1000, 116, 0x02}, | |
133 | {2000, 230, 0x01} }; | |
22b46c45 SP |
134 | |
135 | static const struct { | |
136 | int scale; | |
137 | int dps_range; | |
138 | } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, | |
139 | { 532, BMG160_RANGE_1000DPS}, | |
140 | { 266, BMG160_RANGE_500DPS}, | |
141 | { 133, BMG160_RANGE_250DPS}, | |
142 | { 66, BMG160_RANGE_125DPS} }; | |
143 | ||
144 | static int bmg160_set_mode(struct bmg160_data *data, u8 mode) | |
145 | { | |
dc2c5715 | 146 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 SP |
147 | int ret; |
148 | ||
c6c9e995 | 149 | ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); |
22b46c45 | 150 | if (ret < 0) { |
dc2c5715 | 151 | dev_err(dev, "Error writing reg_pmu_lpw\n"); |
22b46c45 SP |
152 | return ret; |
153 | } | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | static int bmg160_convert_freq_to_bit(int val) | |
159 | { | |
160 | int i; | |
161 | ||
162 | for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { | |
bf61f5d2 | 163 | if (bmg160_samp_freq_table[i].odr == val) |
22b46c45 SP |
164 | return bmg160_samp_freq_table[i].bw_bits; |
165 | } | |
166 | ||
167 | return -EINVAL; | |
168 | } | |
169 | ||
170 | static int bmg160_set_bw(struct bmg160_data *data, int val) | |
171 | { | |
dc2c5715 | 172 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 SP |
173 | int ret; |
174 | int bw_bits; | |
175 | ||
176 | bw_bits = bmg160_convert_freq_to_bit(val); | |
177 | if (bw_bits < 0) | |
178 | return bw_bits; | |
179 | ||
c6c9e995 | 180 | ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); |
22b46c45 | 181 | if (ret < 0) { |
dc2c5715 | 182 | dev_err(dev, "Error writing reg_pmu_bw\n"); |
22b46c45 SP |
183 | return ret; |
184 | } | |
185 | ||
bf61f5d2 ST |
186 | return 0; |
187 | } | |
188 | ||
189 | static int bmg160_get_filter(struct bmg160_data *data, int *val) | |
190 | { | |
191 | struct device *dev = regmap_get_device(data->regmap); | |
192 | int ret; | |
193 | int i; | |
194 | unsigned int bw_bits; | |
195 | ||
196 | ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); | |
197 | if (ret < 0) { | |
198 | dev_err(dev, "Error reading reg_pmu_bw\n"); | |
199 | return ret; | |
200 | } | |
201 | ||
202 | /* Ignore the readonly reserved bit. */ | |
203 | bw_bits &= ~BMG160_REG_PMU_BW_RES; | |
204 | ||
205 | for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { | |
206 | if (bmg160_samp_freq_table[i].bw_bits == bw_bits) | |
207 | break; | |
208 | } | |
209 | ||
210 | *val = bmg160_samp_freq_table[i].filter; | |
211 | ||
212 | return ret ? ret : IIO_VAL_INT; | |
213 | } | |
214 | ||
215 | ||
216 | static int bmg160_set_filter(struct bmg160_data *data, int val) | |
217 | { | |
218 | struct device *dev = regmap_get_device(data->regmap); | |
219 | int ret; | |
220 | int i; | |
221 | ||
222 | for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { | |
223 | if (bmg160_samp_freq_table[i].filter == val) | |
224 | break; | |
225 | } | |
226 | ||
227 | ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, | |
228 | bmg160_samp_freq_table[i].bw_bits); | |
229 | if (ret < 0) { | |
230 | dev_err(dev, "Error writing reg_pmu_bw\n"); | |
231 | return ret; | |
232 | } | |
22b46c45 SP |
233 | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static int bmg160_chip_init(struct bmg160_data *data) | |
238 | { | |
dc2c5715 | 239 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 | 240 | int ret; |
c6c9e995 | 241 | unsigned int val; |
22b46c45 | 242 | |
4bdc9029 QS |
243 | /* |
244 | * Reset chip to get it in a known good state. A delay of 30ms after | |
245 | * reset is required according to the datasheet. | |
246 | */ | |
247 | regmap_write(data->regmap, BMG160_GYRO_REG_RESET, | |
248 | BMG160_GYRO_RESET_VAL); | |
249 | usleep_range(30000, 30700); | |
250 | ||
c6c9e995 | 251 | ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); |
22b46c45 | 252 | if (ret < 0) { |
dc2c5715 | 253 | dev_err(dev, "Error reading reg_chip_id\n"); |
22b46c45 SP |
254 | return ret; |
255 | } | |
256 | ||
dc2c5715 | 257 | dev_dbg(dev, "Chip Id %x\n", val); |
c6c9e995 | 258 | if (val != BMG160_CHIP_ID_VAL) { |
dc2c5715 | 259 | dev_err(dev, "invalid chip %x\n", val); |
22b46c45 SP |
260 | return -ENODEV; |
261 | } | |
262 | ||
263 | ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); | |
264 | if (ret < 0) | |
265 | return ret; | |
266 | ||
267 | /* Wait upto 500 ms to be ready after changing mode */ | |
268 | usleep_range(500, 1000); | |
269 | ||
270 | /* Set Bandwidth */ | |
271 | ret = bmg160_set_bw(data, BMG160_DEF_BW); | |
272 | if (ret < 0) | |
273 | return ret; | |
274 | ||
275 | /* Set Default Range */ | |
c6c9e995 | 276 | ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); |
22b46c45 | 277 | if (ret < 0) { |
dc2c5715 | 278 | dev_err(dev, "Error writing reg_range\n"); |
22b46c45 SP |
279 | return ret; |
280 | } | |
281 | data->dps_range = BMG160_RANGE_500DPS; | |
282 | ||
c6c9e995 | 283 | ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); |
22b46c45 | 284 | if (ret < 0) { |
dc2c5715 | 285 | dev_err(dev, "Error reading reg_slope_thres\n"); |
22b46c45 SP |
286 | return ret; |
287 | } | |
c6c9e995 | 288 | data->slope_thres = val; |
22b46c45 SP |
289 | |
290 | /* Set default interrupt mode */ | |
c6c9e995 MP |
291 | ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1, |
292 | BMG160_INT1_BIT_OD, 0); | |
5af6b307 | 293 | if (ret < 0) { |
dc2c5715 | 294 | dev_err(dev, "Error updating bits in reg_int_en_1\n"); |
5af6b307 SP |
295 | return ret; |
296 | } | |
297 | ||
c6c9e995 MP |
298 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
299 | BMG160_INT_MODE_LATCH_INT | | |
300 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 301 | if (ret < 0) { |
dc2c5715 | 302 | dev_err(dev, |
22b46c45 SP |
303 | "Error writing reg_motion_intr\n"); |
304 | return ret; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static int bmg160_set_power_state(struct bmg160_data *data, bool on) | |
311 | { | |
6f0a13f2 | 312 | #ifdef CONFIG_PM |
dc2c5715 | 313 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 SP |
314 | int ret; |
315 | ||
316 | if (on) | |
dc2c5715 | 317 | ret = pm_runtime_get_sync(dev); |
22b46c45 | 318 | else { |
dc2c5715 AS |
319 | pm_runtime_mark_last_busy(dev); |
320 | ret = pm_runtime_put_autosuspend(dev); | |
22b46c45 SP |
321 | } |
322 | ||
323 | if (ret < 0) { | |
dc2c5715 AS |
324 | dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on); |
325 | ||
10bef289 | 326 | if (on) |
dc2c5715 | 327 | pm_runtime_put_noidle(dev); |
10bef289 | 328 | |
22b46c45 SP |
329 | return ret; |
330 | } | |
ef1c6b23 | 331 | #endif |
22b46c45 SP |
332 | |
333 | return 0; | |
334 | } | |
335 | ||
336 | static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, | |
337 | bool status) | |
338 | { | |
dc2c5715 | 339 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 SP |
340 | int ret; |
341 | ||
342 | /* Enable/Disable INT_MAP0 mapping */ | |
c6c9e995 MP |
343 | ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, |
344 | BMG160_INT_MAP_0_BIT_ANY, | |
345 | (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); | |
22b46c45 | 346 | if (ret < 0) { |
dc2c5715 | 347 | dev_err(dev, "Error updating bits reg_int_map0\n"); |
22b46c45 SP |
348 | return ret; |
349 | } | |
350 | ||
351 | /* Enable/Disable slope interrupts */ | |
352 | if (status) { | |
353 | /* Update slope thres */ | |
c6c9e995 MP |
354 | ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, |
355 | data->slope_thres); | |
22b46c45 | 356 | if (ret < 0) { |
dc2c5715 | 357 | dev_err(dev, "Error writing reg_slope_thres\n"); |
22b46c45 SP |
358 | return ret; |
359 | } | |
360 | ||
c6c9e995 MP |
361 | ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, |
362 | BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | | |
363 | BMG160_INT_MOTION_Z); | |
22b46c45 | 364 | if (ret < 0) { |
dc2c5715 | 365 | dev_err(dev, "Error writing reg_motion_intr\n"); |
22b46c45 SP |
366 | return ret; |
367 | } | |
368 | ||
369 | /* | |
370 | * New data interrupt is always non-latched, | |
371 | * which will have higher priority, so no need | |
372 | * to set latched mode, we will be flooded anyway with INTR | |
373 | */ | |
374 | if (!data->dready_trigger_on) { | |
c6c9e995 MP |
375 | ret = regmap_write(data->regmap, |
376 | BMG160_REG_INT_RST_LATCH, | |
377 | BMG160_INT_MODE_LATCH_INT | | |
378 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 379 | if (ret < 0) { |
dc2c5715 | 380 | dev_err(dev, "Error writing reg_rst_latch\n"); |
22b46c45 SP |
381 | return ret; |
382 | } | |
383 | } | |
384 | ||
c6c9e995 MP |
385 | ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, |
386 | BMG160_DATA_ENABLE_INT); | |
22b46c45 | 387 | |
c6c9e995 MP |
388 | } else { |
389 | ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); | |
390 | } | |
22b46c45 SP |
391 | |
392 | if (ret < 0) { | |
dc2c5715 | 393 | dev_err(dev, "Error writing reg_int_en0\n"); |
22b46c45 SP |
394 | return ret; |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, | |
401 | bool status) | |
402 | { | |
dc2c5715 | 403 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 SP |
404 | int ret; |
405 | ||
406 | /* Enable/Disable INT_MAP1 mapping */ | |
c6c9e995 MP |
407 | ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, |
408 | BMG160_INT_MAP_1_BIT_NEW_DATA, | |
409 | (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); | |
22b46c45 | 410 | if (ret < 0) { |
dc2c5715 | 411 | dev_err(dev, "Error updating bits in reg_int_map1\n"); |
22b46c45 SP |
412 | return ret; |
413 | } | |
414 | ||
415 | if (status) { | |
c6c9e995 MP |
416 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
417 | BMG160_INT_MODE_NON_LATCH_INT | | |
418 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 419 | if (ret < 0) { |
dc2c5715 AS |
420 | dev_err(dev, "Error writing reg_rst_latch\n"); |
421 | return ret; | |
22b46c45 SP |
422 | } |
423 | ||
c6c9e995 MP |
424 | ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, |
425 | BMG160_DATA_ENABLE_INT); | |
22b46c45 SP |
426 | |
427 | } else { | |
428 | /* Restore interrupt mode */ | |
c6c9e995 MP |
429 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
430 | BMG160_INT_MODE_LATCH_INT | | |
431 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 432 | if (ret < 0) { |
dc2c5715 AS |
433 | dev_err(dev, "Error writing reg_rst_latch\n"); |
434 | return ret; | |
22b46c45 SP |
435 | } |
436 | ||
c6c9e995 | 437 | ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); |
22b46c45 SP |
438 | } |
439 | ||
440 | if (ret < 0) { | |
dc2c5715 | 441 | dev_err(dev, "Error writing reg_int_en0\n"); |
22b46c45 SP |
442 | return ret; |
443 | } | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
448 | static int bmg160_get_bw(struct bmg160_data *data, int *val) | |
449 | { | |
bf61f5d2 | 450 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 | 451 | int i; |
bf61f5d2 ST |
452 | unsigned int bw_bits; |
453 | int ret; | |
454 | ||
455 | ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits); | |
456 | if (ret < 0) { | |
457 | dev_err(dev, "Error reading reg_pmu_bw\n"); | |
458 | return ret; | |
459 | } | |
460 | ||
461 | /* Ignore the readonly reserved bit. */ | |
462 | bw_bits &= ~BMG160_REG_PMU_BW_RES; | |
22b46c45 SP |
463 | |
464 | for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { | |
bf61f5d2 ST |
465 | if (bmg160_samp_freq_table[i].bw_bits == bw_bits) { |
466 | *val = bmg160_samp_freq_table[i].odr; | |
22b46c45 SP |
467 | return IIO_VAL_INT; |
468 | } | |
469 | } | |
470 | ||
471 | return -EINVAL; | |
472 | } | |
473 | ||
474 | static int bmg160_set_scale(struct bmg160_data *data, int val) | |
475 | { | |
dc2c5715 | 476 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 SP |
477 | int ret, i; |
478 | ||
479 | for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { | |
480 | if (bmg160_scale_table[i].scale == val) { | |
c6c9e995 MP |
481 | ret = regmap_write(data->regmap, BMG160_REG_RANGE, |
482 | bmg160_scale_table[i].dps_range); | |
22b46c45 | 483 | if (ret < 0) { |
dc2c5715 | 484 | dev_err(dev, "Error writing reg_range\n"); |
22b46c45 SP |
485 | return ret; |
486 | } | |
487 | data->dps_range = bmg160_scale_table[i].dps_range; | |
488 | return 0; | |
489 | } | |
490 | } | |
491 | ||
492 | return -EINVAL; | |
493 | } | |
494 | ||
495 | static int bmg160_get_temp(struct bmg160_data *data, int *val) | |
496 | { | |
dc2c5715 | 497 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 | 498 | int ret; |
c6c9e995 | 499 | unsigned int raw_val; |
22b46c45 SP |
500 | |
501 | mutex_lock(&data->mutex); | |
502 | ret = bmg160_set_power_state(data, true); | |
503 | if (ret < 0) { | |
504 | mutex_unlock(&data->mutex); | |
505 | return ret; | |
506 | } | |
507 | ||
c6c9e995 | 508 | ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); |
22b46c45 | 509 | if (ret < 0) { |
dc2c5715 | 510 | dev_err(dev, "Error reading reg_temp\n"); |
22b46c45 SP |
511 | bmg160_set_power_state(data, false); |
512 | mutex_unlock(&data->mutex); | |
513 | return ret; | |
514 | } | |
515 | ||
c6c9e995 | 516 | *val = sign_extend32(raw_val, 7); |
22b46c45 SP |
517 | ret = bmg160_set_power_state(data, false); |
518 | mutex_unlock(&data->mutex); | |
519 | if (ret < 0) | |
520 | return ret; | |
521 | ||
522 | return IIO_VAL_INT; | |
523 | } | |
524 | ||
525 | static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) | |
526 | { | |
dc2c5715 | 527 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 | 528 | int ret; |
95e7ff03 | 529 | __le16 raw_val; |
22b46c45 SP |
530 | |
531 | mutex_lock(&data->mutex); | |
532 | ret = bmg160_set_power_state(data, true); | |
533 | if (ret < 0) { | |
534 | mutex_unlock(&data->mutex); | |
535 | return ret; | |
536 | } | |
537 | ||
c6c9e995 | 538 | ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, |
95e7ff03 | 539 | sizeof(raw_val)); |
22b46c45 | 540 | if (ret < 0) { |
dc2c5715 | 541 | dev_err(dev, "Error reading axis %d\n", axis); |
22b46c45 SP |
542 | bmg160_set_power_state(data, false); |
543 | mutex_unlock(&data->mutex); | |
544 | return ret; | |
545 | } | |
546 | ||
95e7ff03 | 547 | *val = sign_extend32(le16_to_cpu(raw_val), 15); |
22b46c45 SP |
548 | ret = bmg160_set_power_state(data, false); |
549 | mutex_unlock(&data->mutex); | |
550 | if (ret < 0) | |
551 | return ret; | |
552 | ||
553 | return IIO_VAL_INT; | |
554 | } | |
555 | ||
556 | static int bmg160_read_raw(struct iio_dev *indio_dev, | |
557 | struct iio_chan_spec const *chan, | |
558 | int *val, int *val2, long mask) | |
559 | { | |
560 | struct bmg160_data *data = iio_priv(indio_dev); | |
561 | int ret; | |
562 | ||
563 | switch (mask) { | |
564 | case IIO_CHAN_INFO_RAW: | |
565 | switch (chan->type) { | |
566 | case IIO_TEMP: | |
567 | return bmg160_get_temp(data, val); | |
568 | case IIO_ANGL_VEL: | |
569 | if (iio_buffer_enabled(indio_dev)) | |
570 | return -EBUSY; | |
571 | else | |
572 | return bmg160_get_axis(data, chan->scan_index, | |
573 | val); | |
574 | default: | |
575 | return -EINVAL; | |
576 | } | |
577 | case IIO_CHAN_INFO_OFFSET: | |
578 | if (chan->type == IIO_TEMP) { | |
579 | *val = BMG160_TEMP_CENTER_VAL; | |
580 | return IIO_VAL_INT; | |
581 | } else | |
582 | return -EINVAL; | |
bf61f5d2 ST |
583 | case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: |
584 | return bmg160_get_filter(data, val); | |
22b46c45 SP |
585 | case IIO_CHAN_INFO_SCALE: |
586 | *val = 0; | |
587 | switch (chan->type) { | |
588 | case IIO_TEMP: | |
589 | *val2 = 500000; | |
590 | return IIO_VAL_INT_PLUS_MICRO; | |
591 | case IIO_ANGL_VEL: | |
592 | { | |
593 | int i; | |
594 | ||
595 | for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { | |
596 | if (bmg160_scale_table[i].dps_range == | |
597 | data->dps_range) { | |
598 | *val2 = bmg160_scale_table[i].scale; | |
599 | return IIO_VAL_INT_PLUS_MICRO; | |
600 | } | |
601 | } | |
602 | return -EINVAL; | |
603 | } | |
604 | default: | |
605 | return -EINVAL; | |
606 | } | |
607 | case IIO_CHAN_INFO_SAMP_FREQ: | |
608 | *val2 = 0; | |
609 | mutex_lock(&data->mutex); | |
610 | ret = bmg160_get_bw(data, val); | |
611 | mutex_unlock(&data->mutex); | |
612 | return ret; | |
613 | default: | |
614 | return -EINVAL; | |
615 | } | |
616 | } | |
617 | ||
618 | static int bmg160_write_raw(struct iio_dev *indio_dev, | |
619 | struct iio_chan_spec const *chan, | |
620 | int val, int val2, long mask) | |
621 | { | |
622 | struct bmg160_data *data = iio_priv(indio_dev); | |
623 | int ret; | |
624 | ||
625 | switch (mask) { | |
626 | case IIO_CHAN_INFO_SAMP_FREQ: | |
627 | mutex_lock(&data->mutex); | |
628 | /* | |
629 | * Section 4.2 of spec | |
630 | * In suspend mode, the only supported operations are reading | |
631 | * registers as well as writing to the (0x14) softreset | |
632 | * register. Since we will be in suspend mode by default, change | |
633 | * mode to power on for other writes. | |
634 | */ | |
635 | ret = bmg160_set_power_state(data, true); | |
636 | if (ret < 0) { | |
637 | mutex_unlock(&data->mutex); | |
638 | return ret; | |
639 | } | |
640 | ret = bmg160_set_bw(data, val); | |
641 | if (ret < 0) { | |
642 | bmg160_set_power_state(data, false); | |
643 | mutex_unlock(&data->mutex); | |
644 | return ret; | |
645 | } | |
646 | ret = bmg160_set_power_state(data, false); | |
647 | mutex_unlock(&data->mutex); | |
648 | return ret; | |
bf61f5d2 ST |
649 | case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: |
650 | if (val2) | |
651 | return -EINVAL; | |
652 | ||
653 | mutex_lock(&data->mutex); | |
654 | ret = bmg160_set_power_state(data, true); | |
655 | if (ret < 0) { | |
656 | bmg160_set_power_state(data, false); | |
657 | mutex_unlock(&data->mutex); | |
658 | return ret; | |
659 | } | |
660 | ret = bmg160_set_filter(data, val); | |
661 | if (ret < 0) { | |
662 | bmg160_set_power_state(data, false); | |
663 | mutex_unlock(&data->mutex); | |
664 | return ret; | |
665 | } | |
666 | ret = bmg160_set_power_state(data, false); | |
667 | mutex_unlock(&data->mutex); | |
668 | return ret; | |
22b46c45 SP |
669 | case IIO_CHAN_INFO_SCALE: |
670 | if (val) | |
671 | return -EINVAL; | |
672 | ||
673 | mutex_lock(&data->mutex); | |
674 | /* Refer to comments above for the suspend mode ops */ | |
675 | ret = bmg160_set_power_state(data, true); | |
676 | if (ret < 0) { | |
677 | mutex_unlock(&data->mutex); | |
678 | return ret; | |
679 | } | |
680 | ret = bmg160_set_scale(data, val2); | |
681 | if (ret < 0) { | |
682 | bmg160_set_power_state(data, false); | |
683 | mutex_unlock(&data->mutex); | |
684 | return ret; | |
685 | } | |
686 | ret = bmg160_set_power_state(data, false); | |
687 | mutex_unlock(&data->mutex); | |
688 | return ret; | |
689 | default: | |
690 | return -EINVAL; | |
691 | } | |
692 | ||
693 | return -EINVAL; | |
694 | } | |
695 | ||
696 | static int bmg160_read_event(struct iio_dev *indio_dev, | |
697 | const struct iio_chan_spec *chan, | |
698 | enum iio_event_type type, | |
699 | enum iio_event_direction dir, | |
700 | enum iio_event_info info, | |
701 | int *val, int *val2) | |
702 | { | |
703 | struct bmg160_data *data = iio_priv(indio_dev); | |
704 | ||
705 | *val2 = 0; | |
706 | switch (info) { | |
707 | case IIO_EV_INFO_VALUE: | |
708 | *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; | |
709 | break; | |
710 | default: | |
711 | return -EINVAL; | |
712 | } | |
713 | ||
714 | return IIO_VAL_INT; | |
715 | } | |
716 | ||
717 | static int bmg160_write_event(struct iio_dev *indio_dev, | |
718 | const struct iio_chan_spec *chan, | |
719 | enum iio_event_type type, | |
720 | enum iio_event_direction dir, | |
721 | enum iio_event_info info, | |
722 | int val, int val2) | |
723 | { | |
724 | struct bmg160_data *data = iio_priv(indio_dev); | |
725 | ||
726 | switch (info) { | |
727 | case IIO_EV_INFO_VALUE: | |
728 | if (data->ev_enable_state) | |
729 | return -EBUSY; | |
730 | data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; | |
731 | data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); | |
732 | break; | |
733 | default: | |
734 | return -EINVAL; | |
735 | } | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
740 | static int bmg160_read_event_config(struct iio_dev *indio_dev, | |
741 | const struct iio_chan_spec *chan, | |
742 | enum iio_event_type type, | |
743 | enum iio_event_direction dir) | |
744 | { | |
745 | ||
746 | struct bmg160_data *data = iio_priv(indio_dev); | |
747 | ||
748 | return data->ev_enable_state; | |
749 | } | |
750 | ||
751 | static int bmg160_write_event_config(struct iio_dev *indio_dev, | |
752 | const struct iio_chan_spec *chan, | |
753 | enum iio_event_type type, | |
754 | enum iio_event_direction dir, | |
755 | int state) | |
756 | { | |
757 | struct bmg160_data *data = iio_priv(indio_dev); | |
758 | int ret; | |
759 | ||
760 | if (state && data->ev_enable_state) | |
761 | return 0; | |
762 | ||
763 | mutex_lock(&data->mutex); | |
764 | ||
765 | if (!state && data->motion_trigger_on) { | |
766 | data->ev_enable_state = 0; | |
767 | mutex_unlock(&data->mutex); | |
768 | return 0; | |
769 | } | |
770 | /* | |
771 | * We will expect the enable and disable to do operation in | |
772 | * in reverse order. This will happen here anyway as our | |
773 | * resume operation uses sync mode runtime pm calls, the | |
774 | * suspend operation will be delayed by autosuspend delay | |
775 | * So the disable operation will still happen in reverse of | |
776 | * enable operation. When runtime pm is disabled the mode | |
777 | * is always on so sequence doesn't matter | |
778 | */ | |
779 | ret = bmg160_set_power_state(data, state); | |
780 | if (ret < 0) { | |
781 | mutex_unlock(&data->mutex); | |
782 | return ret; | |
783 | } | |
784 | ||
785 | ret = bmg160_setup_any_motion_interrupt(data, state); | |
786 | if (ret < 0) { | |
10bef289 | 787 | bmg160_set_power_state(data, false); |
22b46c45 SP |
788 | mutex_unlock(&data->mutex); |
789 | return ret; | |
790 | } | |
791 | ||
792 | data->ev_enable_state = state; | |
793 | mutex_unlock(&data->mutex); | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
22b46c45 SP |
798 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); |
799 | ||
800 | static IIO_CONST_ATTR(in_anglvel_scale_available, | |
801 | "0.001065 0.000532 0.000266 0.000133 0.000066"); | |
802 | ||
803 | static struct attribute *bmg160_attributes[] = { | |
804 | &iio_const_attr_sampling_frequency_available.dev_attr.attr, | |
805 | &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, | |
806 | NULL, | |
807 | }; | |
808 | ||
809 | static const struct attribute_group bmg160_attrs_group = { | |
810 | .attrs = bmg160_attributes, | |
811 | }; | |
812 | ||
813 | static const struct iio_event_spec bmg160_event = { | |
814 | .type = IIO_EV_TYPE_ROC, | |
6896ab3a | 815 | .dir = IIO_EV_DIR_EITHER, |
22b46c45 SP |
816 | .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | |
817 | BIT(IIO_EV_INFO_ENABLE) | |
818 | }; | |
819 | ||
820 | #define BMG160_CHANNEL(_axis) { \ | |
821 | .type = IIO_ANGL_VEL, \ | |
822 | .modified = 1, \ | |
823 | .channel2 = IIO_MOD_##_axis, \ | |
824 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
825 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ | |
bf61f5d2 ST |
826 | BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ |
827 | BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ | |
22b46c45 SP |
828 | .scan_index = AXIS_##_axis, \ |
829 | .scan_type = { \ | |
830 | .sign = 's', \ | |
831 | .realbits = 16, \ | |
832 | .storagebits = 16, \ | |
7e3d1eb1 | 833 | .endianness = IIO_LE, \ |
22b46c45 SP |
834 | }, \ |
835 | .event_spec = &bmg160_event, \ | |
836 | .num_event_specs = 1 \ | |
837 | } | |
838 | ||
839 | static const struct iio_chan_spec bmg160_channels[] = { | |
840 | { | |
841 | .type = IIO_TEMP, | |
842 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | | |
843 | BIT(IIO_CHAN_INFO_SCALE) | | |
844 | BIT(IIO_CHAN_INFO_OFFSET), | |
845 | .scan_index = -1, | |
846 | }, | |
847 | BMG160_CHANNEL(X), | |
848 | BMG160_CHANNEL(Y), | |
849 | BMG160_CHANNEL(Z), | |
850 | IIO_CHAN_SOFT_TIMESTAMP(3), | |
851 | }; | |
852 | ||
853 | static const struct iio_info bmg160_info = { | |
854 | .attrs = &bmg160_attrs_group, | |
855 | .read_raw = bmg160_read_raw, | |
856 | .write_raw = bmg160_write_raw, | |
857 | .read_event_value = bmg160_read_event, | |
858 | .write_event_value = bmg160_write_event, | |
859 | .write_event_config = bmg160_write_event_config, | |
860 | .read_event_config = bmg160_read_event_config, | |
22b46c45 SP |
861 | }; |
862 | ||
ee8c5419 IT |
863 | static const unsigned long bmg160_accel_scan_masks[] = { |
864 | BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), | |
865 | 0}; | |
866 | ||
22b46c45 SP |
867 | static irqreturn_t bmg160_trigger_handler(int irq, void *p) |
868 | { | |
869 | struct iio_poll_func *pf = p; | |
870 | struct iio_dev *indio_dev = pf->indio_dev; | |
871 | struct bmg160_data *data = iio_priv(indio_dev); | |
7e3d1eb1 | 872 | int ret; |
22b46c45 SP |
873 | |
874 | mutex_lock(&data->mutex); | |
7e3d1eb1 IT |
875 | ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L, |
876 | data->buffer, AXIS_MAX * 2); | |
22b46c45 | 877 | mutex_unlock(&data->mutex); |
7e3d1eb1 IT |
878 | if (ret < 0) |
879 | goto err; | |
22b46c45 SP |
880 | |
881 | iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, | |
eb219101 | 882 | pf->timestamp); |
22b46c45 SP |
883 | err: |
884 | iio_trigger_notify_done(indio_dev->trig); | |
885 | ||
886 | return IRQ_HANDLED; | |
887 | } | |
888 | ||
889 | static int bmg160_trig_try_reen(struct iio_trigger *trig) | |
890 | { | |
891 | struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); | |
892 | struct bmg160_data *data = iio_priv(indio_dev); | |
dc2c5715 | 893 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 SP |
894 | int ret; |
895 | ||
896 | /* new data interrupts don't need ack */ | |
897 | if (data->dready_trigger_on) | |
898 | return 0; | |
899 | ||
900 | /* Set latched mode interrupt and clear any latched interrupt */ | |
c6c9e995 MP |
901 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
902 | BMG160_INT_MODE_LATCH_INT | | |
903 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 904 | if (ret < 0) { |
dc2c5715 | 905 | dev_err(dev, "Error writing reg_rst_latch\n"); |
22b46c45 SP |
906 | return ret; |
907 | } | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, | |
913 | bool state) | |
914 | { | |
915 | struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); | |
916 | struct bmg160_data *data = iio_priv(indio_dev); | |
917 | int ret; | |
918 | ||
919 | mutex_lock(&data->mutex); | |
920 | ||
921 | if (!state && data->ev_enable_state && data->motion_trigger_on) { | |
922 | data->motion_trigger_on = false; | |
923 | mutex_unlock(&data->mutex); | |
924 | return 0; | |
925 | } | |
926 | ||
927 | /* | |
928 | * Refer to comment in bmg160_write_event_config for | |
929 | * enable/disable operation order | |
930 | */ | |
931 | ret = bmg160_set_power_state(data, state); | |
932 | if (ret < 0) { | |
933 | mutex_unlock(&data->mutex); | |
934 | return ret; | |
935 | } | |
936 | if (data->motion_trig == trig) | |
937 | ret = bmg160_setup_any_motion_interrupt(data, state); | |
938 | else | |
939 | ret = bmg160_setup_new_data_interrupt(data, state); | |
940 | if (ret < 0) { | |
10bef289 | 941 | bmg160_set_power_state(data, false); |
22b46c45 SP |
942 | mutex_unlock(&data->mutex); |
943 | return ret; | |
944 | } | |
945 | if (data->motion_trig == trig) | |
946 | data->motion_trigger_on = state; | |
947 | else | |
948 | data->dready_trigger_on = state; | |
949 | ||
950 | mutex_unlock(&data->mutex); | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | static const struct iio_trigger_ops bmg160_trigger_ops = { | |
956 | .set_trigger_state = bmg160_data_rdy_trigger_set_state, | |
957 | .try_reenable = bmg160_trig_try_reen, | |
22b46c45 SP |
958 | }; |
959 | ||
960 | static irqreturn_t bmg160_event_handler(int irq, void *private) | |
961 | { | |
962 | struct iio_dev *indio_dev = private; | |
963 | struct bmg160_data *data = iio_priv(indio_dev); | |
dc2c5715 | 964 | struct device *dev = regmap_get_device(data->regmap); |
22b46c45 SP |
965 | int ret; |
966 | int dir; | |
c6c9e995 | 967 | unsigned int val; |
22b46c45 | 968 | |
c6c9e995 | 969 | ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); |
22b46c45 | 970 | if (ret < 0) { |
dc2c5715 | 971 | dev_err(dev, "Error reading reg_int_status2\n"); |
22b46c45 SP |
972 | goto ack_intr_status; |
973 | } | |
974 | ||
c6c9e995 | 975 | if (val & 0x08) |
22b46c45 SP |
976 | dir = IIO_EV_DIR_RISING; |
977 | else | |
978 | dir = IIO_EV_DIR_FALLING; | |
979 | ||
c6c9e995 | 980 | if (val & BMG160_ANY_MOTION_BIT_X) |
22b46c45 | 981 | iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, |
bc2b7dab GB |
982 | 0, |
983 | IIO_MOD_X, | |
984 | IIO_EV_TYPE_ROC, | |
985 | dir), | |
986 | iio_get_time_ns(indio_dev)); | |
c6c9e995 | 987 | if (val & BMG160_ANY_MOTION_BIT_Y) |
cb80f6a3 | 988 | iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, |
bc2b7dab GB |
989 | 0, |
990 | IIO_MOD_Y, | |
991 | IIO_EV_TYPE_ROC, | |
992 | dir), | |
993 | iio_get_time_ns(indio_dev)); | |
c6c9e995 | 994 | if (val & BMG160_ANY_MOTION_BIT_Z) |
cb80f6a3 | 995 | iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, |
bc2b7dab GB |
996 | 0, |
997 | IIO_MOD_Z, | |
998 | IIO_EV_TYPE_ROC, | |
999 | dir), | |
1000 | iio_get_time_ns(indio_dev)); | |
22b46c45 SP |
1001 | |
1002 | ack_intr_status: | |
1003 | if (!data->dready_trigger_on) { | |
c6c9e995 MP |
1004 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
1005 | BMG160_INT_MODE_LATCH_INT | | |
1006 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 1007 | if (ret < 0) |
dc2c5715 | 1008 | dev_err(dev, "Error writing reg_rst_latch\n"); |
22b46c45 SP |
1009 | } |
1010 | ||
1011 | return IRQ_HANDLED; | |
1012 | } | |
1013 | ||
1014 | static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) | |
1015 | { | |
1016 | struct iio_dev *indio_dev = private; | |
1017 | struct bmg160_data *data = iio_priv(indio_dev); | |
1018 | ||
22b46c45 SP |
1019 | if (data->dready_trigger_on) |
1020 | iio_trigger_poll(data->dready_trig); | |
1021 | else if (data->motion_trigger_on) | |
1022 | iio_trigger_poll(data->motion_trig); | |
1023 | ||
1024 | if (data->ev_enable_state) | |
1025 | return IRQ_WAKE_THREAD; | |
1026 | else | |
1027 | return IRQ_HANDLED; | |
1028 | ||
1029 | } | |
1030 | ||
00e0c8e8 VD |
1031 | static int bmg160_buffer_preenable(struct iio_dev *indio_dev) |
1032 | { | |
1033 | struct bmg160_data *data = iio_priv(indio_dev); | |
1034 | ||
1035 | return bmg160_set_power_state(data, true); | |
1036 | } | |
1037 | ||
1038 | static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) | |
1039 | { | |
1040 | struct bmg160_data *data = iio_priv(indio_dev); | |
1041 | ||
1042 | return bmg160_set_power_state(data, false); | |
1043 | } | |
1044 | ||
1045 | static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { | |
1046 | .preenable = bmg160_buffer_preenable, | |
1047 | .postenable = iio_triggered_buffer_postenable, | |
1048 | .predisable = iio_triggered_buffer_predisable, | |
1049 | .postdisable = bmg160_buffer_postdisable, | |
1050 | }; | |
1051 | ||
3a0888ed IT |
1052 | static const char *bmg160_match_acpi_device(struct device *dev) |
1053 | { | |
1054 | const struct acpi_device_id *id; | |
1055 | ||
1056 | id = acpi_match_device(dev->driver->acpi_match_table, dev); | |
1057 | if (!id) | |
1058 | return NULL; | |
1059 | ||
1060 | return dev_name(dev); | |
1061 | } | |
1062 | ||
13426454 MP |
1063 | int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq, |
1064 | const char *name) | |
22b46c45 SP |
1065 | { |
1066 | struct bmg160_data *data; | |
1067 | struct iio_dev *indio_dev; | |
1068 | int ret; | |
1069 | ||
13426454 | 1070 | indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); |
22b46c45 SP |
1071 | if (!indio_dev) |
1072 | return -ENOMEM; | |
1073 | ||
1074 | data = iio_priv(indio_dev); | |
5d889abb | 1075 | dev_set_drvdata(dev, indio_dev); |
13426454 MP |
1076 | data->irq = irq; |
1077 | data->regmap = regmap; | |
22b46c45 SP |
1078 | |
1079 | ret = bmg160_chip_init(data); | |
1080 | if (ret < 0) | |
1081 | return ret; | |
1082 | ||
1083 | mutex_init(&data->mutex); | |
1084 | ||
5d889abb MP |
1085 | if (ACPI_HANDLE(dev)) |
1086 | name = bmg160_match_acpi_device(dev); | |
3a0888ed | 1087 | |
5d889abb | 1088 | indio_dev->dev.parent = dev; |
22b46c45 SP |
1089 | indio_dev->channels = bmg160_channels; |
1090 | indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); | |
3a0888ed | 1091 | indio_dev->name = name; |
ee8c5419 | 1092 | indio_dev->available_scan_masks = bmg160_accel_scan_masks; |
22b46c45 SP |
1093 | indio_dev->modes = INDIO_DIRECT_MODE; |
1094 | indio_dev->info = &bmg160_info; | |
1095 | ||
5d889abb MP |
1096 | if (data->irq > 0) { |
1097 | ret = devm_request_threaded_irq(dev, | |
1098 | data->irq, | |
22b46c45 SP |
1099 | bmg160_data_rdy_trig_poll, |
1100 | bmg160_event_handler, | |
1101 | IRQF_TRIGGER_RISING, | |
1102 | BMG160_IRQ_NAME, | |
1103 | indio_dev); | |
1104 | if (ret) | |
1105 | return ret; | |
1106 | ||
5d889abb | 1107 | data->dready_trig = devm_iio_trigger_alloc(dev, |
22b46c45 SP |
1108 | "%s-dev%d", |
1109 | indio_dev->name, | |
1110 | indio_dev->id); | |
1111 | if (!data->dready_trig) | |
1112 | return -ENOMEM; | |
1113 | ||
5d889abb | 1114 | data->motion_trig = devm_iio_trigger_alloc(dev, |
22b46c45 SP |
1115 | "%s-any-motion-dev%d", |
1116 | indio_dev->name, | |
1117 | indio_dev->id); | |
1118 | if (!data->motion_trig) | |
1119 | return -ENOMEM; | |
1120 | ||
5d889abb | 1121 | data->dready_trig->dev.parent = dev; |
22b46c45 SP |
1122 | data->dready_trig->ops = &bmg160_trigger_ops; |
1123 | iio_trigger_set_drvdata(data->dready_trig, indio_dev); | |
1124 | ret = iio_trigger_register(data->dready_trig); | |
1125 | if (ret) | |
1126 | return ret; | |
1127 | ||
5d889abb | 1128 | data->motion_trig->dev.parent = dev; |
22b46c45 SP |
1129 | data->motion_trig->ops = &bmg160_trigger_ops; |
1130 | iio_trigger_set_drvdata(data->motion_trig, indio_dev); | |
1131 | ret = iio_trigger_register(data->motion_trig); | |
1132 | if (ret) { | |
1133 | data->motion_trig = NULL; | |
1134 | goto err_trigger_unregister; | |
1135 | } | |
00e0c8e8 | 1136 | } |
22b46c45 | 1137 | |
00e0c8e8 VD |
1138 | ret = iio_triggered_buffer_setup(indio_dev, |
1139 | iio_pollfunc_store_time, | |
1140 | bmg160_trigger_handler, | |
1141 | &bmg160_buffer_setup_ops); | |
1142 | if (ret < 0) { | |
5d889abb | 1143 | dev_err(dev, |
00e0c8e8 VD |
1144 | "iio triggered buffer setup failed\n"); |
1145 | goto err_trigger_unregister; | |
22b46c45 SP |
1146 | } |
1147 | ||
5d889abb | 1148 | ret = pm_runtime_set_active(dev); |
22b46c45 | 1149 | if (ret) |
7d0ead5c | 1150 | goto err_buffer_cleanup; |
22b46c45 | 1151 | |
5d889abb MP |
1152 | pm_runtime_enable(dev); |
1153 | pm_runtime_set_autosuspend_delay(dev, | |
22b46c45 | 1154 | BMG160_AUTO_SUSPEND_DELAY_MS); |
5d889abb | 1155 | pm_runtime_use_autosuspend(dev); |
22b46c45 | 1156 | |
7d0ead5c AR |
1157 | ret = iio_device_register(indio_dev); |
1158 | if (ret < 0) { | |
1159 | dev_err(dev, "unable to register iio device\n"); | |
1160 | goto err_buffer_cleanup; | |
1161 | } | |
1162 | ||
22b46c45 SP |
1163 | return 0; |
1164 | ||
22b46c45 | 1165 | err_buffer_cleanup: |
00e0c8e8 | 1166 | iio_triggered_buffer_cleanup(indio_dev); |
22b46c45 SP |
1167 | err_trigger_unregister: |
1168 | if (data->dready_trig) | |
1169 | iio_trigger_unregister(data->dready_trig); | |
1170 | if (data->motion_trig) | |
1171 | iio_trigger_unregister(data->motion_trig); | |
1172 | ||
1173 | return ret; | |
1174 | } | |
13426454 | 1175 | EXPORT_SYMBOL_GPL(bmg160_core_probe); |
22b46c45 | 1176 | |
13426454 | 1177 | void bmg160_core_remove(struct device *dev) |
22b46c45 | 1178 | { |
13426454 | 1179 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 SP |
1180 | struct bmg160_data *data = iio_priv(indio_dev); |
1181 | ||
7d0ead5c AR |
1182 | iio_device_unregister(indio_dev); |
1183 | ||
13426454 MP |
1184 | pm_runtime_disable(dev); |
1185 | pm_runtime_set_suspended(dev); | |
1186 | pm_runtime_put_noidle(dev); | |
22b46c45 | 1187 | |
00e0c8e8 | 1188 | iio_triggered_buffer_cleanup(indio_dev); |
22b46c45 SP |
1189 | |
1190 | if (data->dready_trig) { | |
22b46c45 SP |
1191 | iio_trigger_unregister(data->dready_trig); |
1192 | iio_trigger_unregister(data->motion_trig); | |
1193 | } | |
1194 | ||
1195 | mutex_lock(&data->mutex); | |
1196 | bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); | |
1197 | mutex_unlock(&data->mutex); | |
22b46c45 | 1198 | } |
13426454 | 1199 | EXPORT_SYMBOL_GPL(bmg160_core_remove); |
22b46c45 SP |
1200 | |
1201 | #ifdef CONFIG_PM_SLEEP | |
1202 | static int bmg160_suspend(struct device *dev) | |
1203 | { | |
ebc6eb59 | 1204 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 SP |
1205 | struct bmg160_data *data = iio_priv(indio_dev); |
1206 | ||
1207 | mutex_lock(&data->mutex); | |
1208 | bmg160_set_mode(data, BMG160_MODE_SUSPEND); | |
1209 | mutex_unlock(&data->mutex); | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | static int bmg160_resume(struct device *dev) | |
1215 | { | |
ebc6eb59 | 1216 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 SP |
1217 | struct bmg160_data *data = iio_priv(indio_dev); |
1218 | ||
1219 | mutex_lock(&data->mutex); | |
1220 | if (data->dready_trigger_on || data->motion_trigger_on || | |
1221 | data->ev_enable_state) | |
1222 | bmg160_set_mode(data, BMG160_MODE_NORMAL); | |
1223 | mutex_unlock(&data->mutex); | |
1224 | ||
1225 | return 0; | |
1226 | } | |
1227 | #endif | |
1228 | ||
6f0a13f2 | 1229 | #ifdef CONFIG_PM |
22b46c45 SP |
1230 | static int bmg160_runtime_suspend(struct device *dev) |
1231 | { | |
ebc6eb59 | 1232 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 | 1233 | struct bmg160_data *data = iio_priv(indio_dev); |
10bef289 | 1234 | int ret; |
22b46c45 | 1235 | |
10bef289 SP |
1236 | ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); |
1237 | if (ret < 0) { | |
dc2c5715 | 1238 | dev_err(dev, "set mode failed\n"); |
10bef289 SP |
1239 | return -EAGAIN; |
1240 | } | |
1241 | ||
1242 | return 0; | |
22b46c45 SP |
1243 | } |
1244 | ||
1245 | static int bmg160_runtime_resume(struct device *dev) | |
1246 | { | |
ebc6eb59 | 1247 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 SP |
1248 | struct bmg160_data *data = iio_priv(indio_dev); |
1249 | int ret; | |
1250 | ||
1251 | ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); | |
1252 | if (ret < 0) | |
1253 | return ret; | |
1254 | ||
1255 | msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | #endif | |
1260 | ||
13426454 | 1261 | const struct dev_pm_ops bmg160_pm_ops = { |
22b46c45 SP |
1262 | SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) |
1263 | SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, | |
1264 | bmg160_runtime_resume, NULL) | |
1265 | }; | |
13426454 | 1266 | EXPORT_SYMBOL_GPL(bmg160_pm_ops); |
22b46c45 SP |
1267 | |
1268 | MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); | |
1269 | MODULE_LICENSE("GPL v2"); | |
1270 | MODULE_DESCRIPTION("BMG160 Gyro driver"); |