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iio: magn: bmc150: Fix buffer alignment in iio_push_to_buffers_with_timestamp()
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2025cf9e 1// SPDX-License-Identifier: GPL-2.0-only
c91746a2
IT
2/*
3 * Bosch BMC150 three-axis magnetic field sensor driver
4 *
5 * Copyright (c) 2015, Intel Corporation.
6 *
7 * This code is based on bmm050_api.c authored by contact@bosch.sensortec.com:
8 *
9 * (C) Copyright 2011~2014 Bosch Sensortec GmbH All Rights Reserved
c91746a2
IT
10 */
11
12#include <linux/module.h>
13#include <linux/i2c.h>
14#include <linux/interrupt.h>
15#include <linux/delay.h>
16#include <linux/slab.h>
17#include <linux/acpi.h>
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18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
20#include <linux/iio/iio.h>
21#include <linux/iio/sysfs.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/events.h>
24#include <linux/iio/trigger.h>
25#include <linux/iio/trigger_consumer.h>
26#include <linux/iio/triggered_buffer.h>
27#include <linux/regmap.h>
28
761b7910
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29#include "bmc150_magn.h"
30
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31#define BMC150_MAGN_DRV_NAME "bmc150_magn"
32#define BMC150_MAGN_IRQ_NAME "bmc150_magn_event"
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33
34#define BMC150_MAGN_REG_CHIP_ID 0x40
35#define BMC150_MAGN_CHIP_ID_VAL 0x32
36
37#define BMC150_MAGN_REG_X_L 0x42
38#define BMC150_MAGN_REG_X_M 0x43
39#define BMC150_MAGN_REG_Y_L 0x44
40#define BMC150_MAGN_REG_Y_M 0x45
41#define BMC150_MAGN_SHIFT_XY_L 3
42#define BMC150_MAGN_REG_Z_L 0x46
43#define BMC150_MAGN_REG_Z_M 0x47
44#define BMC150_MAGN_SHIFT_Z_L 1
45#define BMC150_MAGN_REG_RHALL_L 0x48
46#define BMC150_MAGN_REG_RHALL_M 0x49
47#define BMC150_MAGN_SHIFT_RHALL_L 2
48
49#define BMC150_MAGN_REG_INT_STATUS 0x4A
50
51#define BMC150_MAGN_REG_POWER 0x4B
52#define BMC150_MAGN_MASK_POWER_CTL BIT(0)
53
54#define BMC150_MAGN_REG_OPMODE_ODR 0x4C
55#define BMC150_MAGN_MASK_OPMODE GENMASK(2, 1)
56#define BMC150_MAGN_SHIFT_OPMODE 1
57#define BMC150_MAGN_MODE_NORMAL 0x00
58#define BMC150_MAGN_MODE_FORCED 0x01
59#define BMC150_MAGN_MODE_SLEEP 0x03
60#define BMC150_MAGN_MASK_ODR GENMASK(5, 3)
61#define BMC150_MAGN_SHIFT_ODR 3
62
63#define BMC150_MAGN_REG_INT 0x4D
64
65#define BMC150_MAGN_REG_INT_DRDY 0x4E
66#define BMC150_MAGN_MASK_DRDY_EN BIT(7)
67#define BMC150_MAGN_SHIFT_DRDY_EN 7
68#define BMC150_MAGN_MASK_DRDY_INT3 BIT(6)
69#define BMC150_MAGN_MASK_DRDY_Z_EN BIT(5)
70#define BMC150_MAGN_MASK_DRDY_Y_EN BIT(4)
71#define BMC150_MAGN_MASK_DRDY_X_EN BIT(3)
72#define BMC150_MAGN_MASK_DRDY_DR_POLARITY BIT(2)
73#define BMC150_MAGN_MASK_DRDY_LATCHING BIT(1)
74#define BMC150_MAGN_MASK_DRDY_INT3_POLARITY BIT(0)
75
76#define BMC150_MAGN_REG_LOW_THRESH 0x4F
77#define BMC150_MAGN_REG_HIGH_THRESH 0x50
78#define BMC150_MAGN_REG_REP_XY 0x51
79#define BMC150_MAGN_REG_REP_Z 0x52
1506f3cd 80#define BMC150_MAGN_REG_REP_DATAMASK GENMASK(7, 0)
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81
82#define BMC150_MAGN_REG_TRIM_START 0x5D
83#define BMC150_MAGN_REG_TRIM_END 0x71
84
85#define BMC150_MAGN_XY_OVERFLOW_VAL -4096
86#define BMC150_MAGN_Z_OVERFLOW_VAL -16384
87
88/* Time from SUSPEND to SLEEP */
89#define BMC150_MAGN_START_UP_TIME_MS 3
90
91#define BMC150_MAGN_AUTO_SUSPEND_DELAY_MS 2000
92
93#define BMC150_MAGN_REGVAL_TO_REPXY(regval) (((regval) * 2) + 1)
94#define BMC150_MAGN_REGVAL_TO_REPZ(regval) ((regval) + 1)
95#define BMC150_MAGN_REPXY_TO_REGVAL(rep) (((rep) - 1) / 2)
96#define BMC150_MAGN_REPZ_TO_REGVAL(rep) ((rep) - 1)
97
98enum bmc150_magn_axis {
99 AXIS_X,
100 AXIS_Y,
101 AXIS_Z,
102 RHALL,
103 AXIS_XYZ_MAX = RHALL,
104 AXIS_XYZR_MAX,
105};
106
107enum bmc150_magn_power_modes {
108 BMC150_MAGN_POWER_MODE_SUSPEND,
109 BMC150_MAGN_POWER_MODE_SLEEP,
110 BMC150_MAGN_POWER_MODE_NORMAL,
111};
112
113struct bmc150_magn_trim_regs {
114 s8 x1;
115 s8 y1;
116 __le16 reserved1;
117 u8 reserved2;
118 __le16 z4;
119 s8 x2;
120 s8 y2;
121 __le16 reserved3;
122 __le16 z2;
123 __le16 z1;
124 __le16 xyz1;
125 __le16 z3;
126 s8 xy2;
127 u8 xy1;
128} __packed;
129
130struct bmc150_magn_data {
761b7910 131 struct device *dev;
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132 /*
133 * 1. Protect this structure.
134 * 2. Serialize sequences that power on/off the device and access HW.
135 */
136 struct mutex mutex;
137 struct regmap *regmap;
d9842c77 138 struct iio_mount_matrix orientation;
c9129e32
JC
139 /* Ensure timestamp is naturally aligned */
140 struct {
141 s32 chans[3];
142 s64 timestamp __aligned(8);
143 } scan;
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144 struct iio_trigger *dready_trig;
145 bool dready_trigger_on;
5990dc97 146 int max_odr;
761b7910 147 int irq;
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148};
149
150static const struct {
151 int freq;
152 u8 reg_val;
153} bmc150_magn_samp_freq_table[] = { {2, 0x01},
154 {6, 0x02},
155 {8, 0x03},
156 {10, 0x00},
157 {15, 0x04},
158 {20, 0x05},
159 {25, 0x06},
160 {30, 0x07} };
161
162enum bmc150_magn_presets {
163 LOW_POWER_PRESET,
164 REGULAR_PRESET,
165 ENHANCED_REGULAR_PRESET,
166 HIGH_ACCURACY_PRESET
167};
168
169static const struct bmc150_magn_preset {
170 u8 rep_xy;
171 u8 rep_z;
172 u8 odr;
173} bmc150_magn_presets_table[] = {
174 [LOW_POWER_PRESET] = {3, 3, 10},
175 [REGULAR_PRESET] = {9, 15, 10},
176 [ENHANCED_REGULAR_PRESET] = {15, 27, 10},
177 [HIGH_ACCURACY_PRESET] = {47, 83, 20},
178};
179
180#define BMC150_MAGN_DEFAULT_PRESET REGULAR_PRESET
181
182static bool bmc150_magn_is_writeable_reg(struct device *dev, unsigned int reg)
183{
184 switch (reg) {
185 case BMC150_MAGN_REG_POWER:
186 case BMC150_MAGN_REG_OPMODE_ODR:
187 case BMC150_MAGN_REG_INT:
188 case BMC150_MAGN_REG_INT_DRDY:
189 case BMC150_MAGN_REG_LOW_THRESH:
190 case BMC150_MAGN_REG_HIGH_THRESH:
191 case BMC150_MAGN_REG_REP_XY:
192 case BMC150_MAGN_REG_REP_Z:
193 return true;
194 default:
195 return false;
b3b3ef6a 196 }
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197}
198
199static bool bmc150_magn_is_volatile_reg(struct device *dev, unsigned int reg)
200{
201 switch (reg) {
202 case BMC150_MAGN_REG_X_L:
203 case BMC150_MAGN_REG_X_M:
204 case BMC150_MAGN_REG_Y_L:
205 case BMC150_MAGN_REG_Y_M:
206 case BMC150_MAGN_REG_Z_L:
207 case BMC150_MAGN_REG_Z_M:
208 case BMC150_MAGN_REG_RHALL_L:
209 case BMC150_MAGN_REG_RHALL_M:
210 case BMC150_MAGN_REG_INT_STATUS:
211 return true;
212 default:
213 return false;
214 }
215}
216
761b7910 217const struct regmap_config bmc150_magn_regmap_config = {
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218 .reg_bits = 8,
219 .val_bits = 8,
220
221 .max_register = BMC150_MAGN_REG_TRIM_END,
222 .cache_type = REGCACHE_RBTREE,
223
224 .writeable_reg = bmc150_magn_is_writeable_reg,
225 .volatile_reg = bmc150_magn_is_volatile_reg,
226};
761b7910 227EXPORT_SYMBOL(bmc150_magn_regmap_config);
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228
229static int bmc150_magn_set_power_mode(struct bmc150_magn_data *data,
230 enum bmc150_magn_power_modes mode,
231 bool state)
232{
233 int ret;
234
235 switch (mode) {
236 case BMC150_MAGN_POWER_MODE_SUSPEND:
237 ret = regmap_update_bits(data->regmap, BMC150_MAGN_REG_POWER,
238 BMC150_MAGN_MASK_POWER_CTL, !state);
239 if (ret < 0)
240 return ret;
241 usleep_range(BMC150_MAGN_START_UP_TIME_MS * 1000, 20000);
242 return 0;
243 case BMC150_MAGN_POWER_MODE_SLEEP:
244 return regmap_update_bits(data->regmap,
245 BMC150_MAGN_REG_OPMODE_ODR,
246 BMC150_MAGN_MASK_OPMODE,
247 BMC150_MAGN_MODE_SLEEP <<
248 BMC150_MAGN_SHIFT_OPMODE);
249 case BMC150_MAGN_POWER_MODE_NORMAL:
250 return regmap_update_bits(data->regmap,
251 BMC150_MAGN_REG_OPMODE_ODR,
252 BMC150_MAGN_MASK_OPMODE,
253 BMC150_MAGN_MODE_NORMAL <<
254 BMC150_MAGN_SHIFT_OPMODE);
255 }
256
257 return -EINVAL;
258}
259
260static int bmc150_magn_set_power_state(struct bmc150_magn_data *data, bool on)
261{
262#ifdef CONFIG_PM
263 int ret;
264
265 if (on) {
761b7910 266 ret = pm_runtime_get_sync(data->dev);
c91746a2 267 } else {
761b7910
DB
268 pm_runtime_mark_last_busy(data->dev);
269 ret = pm_runtime_put_autosuspend(data->dev);
c91746a2
IT
270 }
271
272 if (ret < 0) {
761b7910 273 dev_err(data->dev,
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274 "failed to change power state to %d\n", on);
275 if (on)
761b7910 276 pm_runtime_put_noidle(data->dev);
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277
278 return ret;
279 }
280#endif
281
282 return 0;
283}
284
285static int bmc150_magn_get_odr(struct bmc150_magn_data *data, int *val)
286{
287 int ret, reg_val;
288 u8 i, odr_val;
289
290 ret = regmap_read(data->regmap, BMC150_MAGN_REG_OPMODE_ODR, &reg_val);
291 if (ret < 0)
292 return ret;
293 odr_val = (reg_val & BMC150_MAGN_MASK_ODR) >> BMC150_MAGN_SHIFT_ODR;
294
295 for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++)
296 if (bmc150_magn_samp_freq_table[i].reg_val == odr_val) {
297 *val = bmc150_magn_samp_freq_table[i].freq;
298 return 0;
299 }
300
301 return -EINVAL;
302}
303
304static int bmc150_magn_set_odr(struct bmc150_magn_data *data, int val)
305{
306 int ret;
307 u8 i;
308
309 for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++) {
310 if (bmc150_magn_samp_freq_table[i].freq == val) {
311 ret = regmap_update_bits(data->regmap,
312 BMC150_MAGN_REG_OPMODE_ODR,
313 BMC150_MAGN_MASK_ODR,
314 bmc150_magn_samp_freq_table[i].
315 reg_val <<
316 BMC150_MAGN_SHIFT_ODR);
317 if (ret < 0)
318 return ret;
319 return 0;
320 }
321 }
322
323 return -EINVAL;
324}
325
5990dc97
IT
326static int bmc150_magn_set_max_odr(struct bmc150_magn_data *data, int rep_xy,
327 int rep_z, int odr)
328{
329 int ret, reg_val, max_odr;
330
331 if (rep_xy <= 0) {
332 ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_XY,
333 &reg_val);
334 if (ret < 0)
335 return ret;
336 rep_xy = BMC150_MAGN_REGVAL_TO_REPXY(reg_val);
337 }
338 if (rep_z <= 0) {
339 ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_Z,
340 &reg_val);
341 if (ret < 0)
342 return ret;
343 rep_z = BMC150_MAGN_REGVAL_TO_REPZ(reg_val);
344 }
345 if (odr <= 0) {
346 ret = bmc150_magn_get_odr(data, &odr);
347 if (ret < 0)
348 return ret;
349 }
350 /* the maximum selectable read-out frequency from datasheet */
351 max_odr = 1000000 / (145 * rep_xy + 500 * rep_z + 980);
352 if (odr > max_odr) {
761b7910 353 dev_err(data->dev,
5990dc97
IT
354 "Can't set oversampling with sampling freq %d\n",
355 odr);
356 return -EINVAL;
357 }
358 data->max_odr = max_odr;
359
360 return 0;
361}
362
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IT
363static s32 bmc150_magn_compensate_x(struct bmc150_magn_trim_regs *tregs, s16 x,
364 u16 rhall)
365{
366 s16 val;
367 u16 xyz1 = le16_to_cpu(tregs->xyz1);
368
369 if (x == BMC150_MAGN_XY_OVERFLOW_VAL)
370 return S32_MIN;
371
372 if (!rhall)
373 rhall = xyz1;
374
375 val = ((s16)(((u16)((((s32)xyz1) << 14) / rhall)) - ((u16)0x4000)));
376 val = ((s16)((((s32)x) * ((((((((s32)tregs->xy2) * ((((s32)val) *
377 ((s32)val)) >> 7)) + (((s32)val) *
378 ((s32)(((s16)tregs->xy1) << 7)))) >> 9) + ((s32)0x100000)) *
379 ((s32)(((s16)tregs->x2) + ((s16)0xA0)))) >> 12)) >> 13)) +
380 (((s16)tregs->x1) << 3);
381
382 return (s32)val;
383}
384
385static s32 bmc150_magn_compensate_y(struct bmc150_magn_trim_regs *tregs, s16 y,
386 u16 rhall)
387{
388 s16 val;
389 u16 xyz1 = le16_to_cpu(tregs->xyz1);
390
391 if (y == BMC150_MAGN_XY_OVERFLOW_VAL)
392 return S32_MIN;
393
394 if (!rhall)
395 rhall = xyz1;
396
397 val = ((s16)(((u16)((((s32)xyz1) << 14) / rhall)) - ((u16)0x4000)));
398 val = ((s16)((((s32)y) * ((((((((s32)tregs->xy2) * ((((s32)val) *
399 ((s32)val)) >> 7)) + (((s32)val) *
400 ((s32)(((s16)tregs->xy1) << 7)))) >> 9) + ((s32)0x100000)) *
401 ((s32)(((s16)tregs->y2) + ((s16)0xA0)))) >> 12)) >> 13)) +
402 (((s16)tregs->y1) << 3);
403
404 return (s32)val;
405}
406
407static s32 bmc150_magn_compensate_z(struct bmc150_magn_trim_regs *tregs, s16 z,
408 u16 rhall)
409{
410 s32 val;
411 u16 xyz1 = le16_to_cpu(tregs->xyz1);
412 u16 z1 = le16_to_cpu(tregs->z1);
413 s16 z2 = le16_to_cpu(tregs->z2);
414 s16 z3 = le16_to_cpu(tregs->z3);
415 s16 z4 = le16_to_cpu(tregs->z4);
416
417 if (z == BMC150_MAGN_Z_OVERFLOW_VAL)
418 return S32_MIN;
419
420 val = (((((s32)(z - z4)) << 15) - ((((s32)z3) * ((s32)(((s16)rhall) -
421 ((s16)xyz1)))) >> 2)) / (z2 + ((s16)(((((s32)z1) *
422 ((((s16)rhall) << 1))) + (1 << 15)) >> 16))));
423
424 return val;
425}
426
427static int bmc150_magn_read_xyz(struct bmc150_magn_data *data, s32 *buffer)
428{
429 int ret;
430 __le16 values[AXIS_XYZR_MAX];
431 s16 raw_x, raw_y, raw_z;
432 u16 rhall;
433 struct bmc150_magn_trim_regs tregs;
434
435 ret = regmap_bulk_read(data->regmap, BMC150_MAGN_REG_X_L,
436 values, sizeof(values));
437 if (ret < 0)
438 return ret;
439
440 raw_x = (s16)le16_to_cpu(values[AXIS_X]) >> BMC150_MAGN_SHIFT_XY_L;
441 raw_y = (s16)le16_to_cpu(values[AXIS_Y]) >> BMC150_MAGN_SHIFT_XY_L;
442 raw_z = (s16)le16_to_cpu(values[AXIS_Z]) >> BMC150_MAGN_SHIFT_Z_L;
443 rhall = le16_to_cpu(values[RHALL]) >> BMC150_MAGN_SHIFT_RHALL_L;
444
445 ret = regmap_bulk_read(data->regmap, BMC150_MAGN_REG_TRIM_START,
446 &tregs, sizeof(tregs));
447 if (ret < 0)
448 return ret;
449
450 buffer[AXIS_X] = bmc150_magn_compensate_x(&tregs, raw_x, rhall);
451 buffer[AXIS_Y] = bmc150_magn_compensate_y(&tregs, raw_y, rhall);
452 buffer[AXIS_Z] = bmc150_magn_compensate_z(&tregs, raw_z, rhall);
453
454 return 0;
455}
456
457static int bmc150_magn_read_raw(struct iio_dev *indio_dev,
458 struct iio_chan_spec const *chan,
459 int *val, int *val2, long mask)
460{
461 struct bmc150_magn_data *data = iio_priv(indio_dev);
5990dc97 462 int ret, tmp;
c91746a2
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463 s32 values[AXIS_XYZ_MAX];
464
465 switch (mask) {
466 case IIO_CHAN_INFO_RAW:
467 if (iio_buffer_enabled(indio_dev))
468 return -EBUSY;
469 mutex_lock(&data->mutex);
470
471 ret = bmc150_magn_set_power_state(data, true);
472 if (ret < 0) {
473 mutex_unlock(&data->mutex);
474 return ret;
475 }
476
477 ret = bmc150_magn_read_xyz(data, values);
478 if (ret < 0) {
479 bmc150_magn_set_power_state(data, false);
480 mutex_unlock(&data->mutex);
481 return ret;
482 }
483 *val = values[chan->scan_index];
484
485 ret = bmc150_magn_set_power_state(data, false);
486 if (ret < 0) {
487 mutex_unlock(&data->mutex);
488 return ret;
489 }
490
491 mutex_unlock(&data->mutex);
492 return IIO_VAL_INT;
493 case IIO_CHAN_INFO_SCALE:
494 /*
495 * The API/driver performs an off-chip temperature
496 * compensation and outputs x/y/z magnetic field data in
497 * 16 LSB/uT to the upper application layer.
498 */
499 *val = 0;
500 *val2 = 625;
501 return IIO_VAL_INT_PLUS_MICRO;
502 case IIO_CHAN_INFO_SAMP_FREQ:
503 ret = bmc150_magn_get_odr(data, val);
504 if (ret < 0)
505 return ret;
506 return IIO_VAL_INT;
5990dc97
IT
507 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
508 switch (chan->channel2) {
509 case IIO_MOD_X:
510 case IIO_MOD_Y:
511 ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_XY,
512 &tmp);
513 if (ret < 0)
514 return ret;
515 *val = BMC150_MAGN_REGVAL_TO_REPXY(tmp);
516 return IIO_VAL_INT;
517 case IIO_MOD_Z:
518 ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_Z,
519 &tmp);
520 if (ret < 0)
521 return ret;
522 *val = BMC150_MAGN_REGVAL_TO_REPZ(tmp);
523 return IIO_VAL_INT;
524 default:
525 return -EINVAL;
526 }
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IT
527 default:
528 return -EINVAL;
529 }
530}
531
532static int bmc150_magn_write_raw(struct iio_dev *indio_dev,
533 struct iio_chan_spec const *chan,
534 int val, int val2, long mask)
535{
536 struct bmc150_magn_data *data = iio_priv(indio_dev);
537 int ret;
538
539 switch (mask) {
540 case IIO_CHAN_INFO_SAMP_FREQ:
5990dc97
IT
541 if (val > data->max_odr)
542 return -EINVAL;
c91746a2
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543 mutex_lock(&data->mutex);
544 ret = bmc150_magn_set_odr(data, val);
545 mutex_unlock(&data->mutex);
546 return ret;
5990dc97
IT
547 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
548 switch (chan->channel2) {
549 case IIO_MOD_X:
550 case IIO_MOD_Y:
551 if (val < 1 || val > 511)
552 return -EINVAL;
553 mutex_lock(&data->mutex);
554 ret = bmc150_magn_set_max_odr(data, val, 0, 0);
555 if (ret < 0) {
556 mutex_unlock(&data->mutex);
557 return ret;
558 }
559 ret = regmap_update_bits(data->regmap,
560 BMC150_MAGN_REG_REP_XY,
1506f3cd 561 BMC150_MAGN_REG_REP_DATAMASK,
5990dc97
IT
562 BMC150_MAGN_REPXY_TO_REGVAL
563 (val));
564 mutex_unlock(&data->mutex);
565 return ret;
566 case IIO_MOD_Z:
567 if (val < 1 || val > 256)
568 return -EINVAL;
569 mutex_lock(&data->mutex);
570 ret = bmc150_magn_set_max_odr(data, 0, val, 0);
571 if (ret < 0) {
572 mutex_unlock(&data->mutex);
573 return ret;
574 }
575 ret = regmap_update_bits(data->regmap,
576 BMC150_MAGN_REG_REP_Z,
1506f3cd 577 BMC150_MAGN_REG_REP_DATAMASK,
5990dc97
IT
578 BMC150_MAGN_REPZ_TO_REGVAL
579 (val));
580 mutex_unlock(&data->mutex);
581 return ret;
582 default:
583 return -EINVAL;
584 }
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IT
585 default:
586 return -EINVAL;
587 }
588}
589
5990dc97
IT
590static ssize_t bmc150_magn_show_samp_freq_avail(struct device *dev,
591 struct device_attribute *attr,
592 char *buf)
593{
594 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
595 struct bmc150_magn_data *data = iio_priv(indio_dev);
596 size_t len = 0;
597 u8 i;
598
599 for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++) {
600 if (bmc150_magn_samp_freq_table[i].freq > data->max_odr)
601 break;
602 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ",
603 bmc150_magn_samp_freq_table[i].freq);
604 }
605 /* replace last space with a newline */
606 buf[len - 1] = '\n';
607
608 return len;
609}
610
d9842c77
NS
611static const struct iio_mount_matrix *
612bmc150_magn_get_mount_matrix(const struct iio_dev *indio_dev,
613 const struct iio_chan_spec *chan)
614{
615 struct bmc150_magn_data *data = iio_priv(indio_dev);
616
617 return &data->orientation;
618}
619
620static const struct iio_chan_spec_ext_info bmc150_magn_ext_info[] = {
621 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_magn_get_mount_matrix),
622 { }
623};
624
5990dc97 625static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(bmc150_magn_show_samp_freq_avail);
c91746a2
IT
626
627static struct attribute *bmc150_magn_attributes[] = {
5990dc97 628 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
c91746a2
IT
629 NULL,
630};
631
632static const struct attribute_group bmc150_magn_attrs_group = {
633 .attrs = bmc150_magn_attributes,
634};
635
636#define BMC150_MAGN_CHANNEL(_axis) { \
637 .type = IIO_MAGN, \
638 .modified = 1, \
639 .channel2 = IIO_MOD_##_axis, \
5990dc97
IT
640 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
641 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
c91746a2
IT
642 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
643 BIT(IIO_CHAN_INFO_SCALE), \
644 .scan_index = AXIS_##_axis, \
645 .scan_type = { \
646 .sign = 's', \
647 .realbits = 32, \
648 .storagebits = 32, \
649 .endianness = IIO_LE \
650 }, \
d9842c77 651 .ext_info = bmc150_magn_ext_info, \
c91746a2
IT
652}
653
654static const struct iio_chan_spec bmc150_magn_channels[] = {
655 BMC150_MAGN_CHANNEL(X),
656 BMC150_MAGN_CHANNEL(Y),
657 BMC150_MAGN_CHANNEL(Z),
658 IIO_CHAN_SOFT_TIMESTAMP(3),
659};
660
661static const struct iio_info bmc150_magn_info = {
662 .attrs = &bmc150_magn_attrs_group,
663 .read_raw = bmc150_magn_read_raw,
664 .write_raw = bmc150_magn_write_raw,
c91746a2
IT
665};
666
47764c79
HK
667static const unsigned long bmc150_magn_scan_masks[] = {
668 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
669 0};
c91746a2
IT
670
671static irqreturn_t bmc150_magn_trigger_handler(int irq, void *p)
672{
673 struct iio_poll_func *pf = p;
674 struct iio_dev *indio_dev = pf->indio_dev;
675 struct bmc150_magn_data *data = iio_priv(indio_dev);
676 int ret;
677
678 mutex_lock(&data->mutex);
c9129e32 679 ret = bmc150_magn_read_xyz(data, data->scan.chans);
c91746a2
IT
680 if (ret < 0)
681 goto err;
682
c9129e32 683 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
c91746a2
IT
684 pf->timestamp);
685
686err:
3021678a 687 mutex_unlock(&data->mutex);
9d174b49 688 iio_trigger_notify_done(indio_dev->trig);
c91746a2
IT
689
690 return IRQ_HANDLED;
691}
692
693static int bmc150_magn_init(struct bmc150_magn_data *data)
694{
695 int ret, chip_id;
696 struct bmc150_magn_preset preset;
697
698 ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND,
699 false);
700 if (ret < 0) {
761b7910 701 dev_err(data->dev,
c91746a2
IT
702 "Failed to bring up device from suspend mode\n");
703 return ret;
704 }
705
706 ret = regmap_read(data->regmap, BMC150_MAGN_REG_CHIP_ID, &chip_id);
707 if (ret < 0) {
761b7910 708 dev_err(data->dev, "Failed reading chip id\n");
c91746a2
IT
709 goto err_poweroff;
710 }
711 if (chip_id != BMC150_MAGN_CHIP_ID_VAL) {
761b7910 712 dev_err(data->dev, "Invalid chip id 0x%x\n", chip_id);
c91746a2
IT
713 ret = -ENODEV;
714 goto err_poweroff;
715 }
761b7910 716 dev_dbg(data->dev, "Chip id %x\n", chip_id);
c91746a2
IT
717
718 preset = bmc150_magn_presets_table[BMC150_MAGN_DEFAULT_PRESET];
719 ret = bmc150_magn_set_odr(data, preset.odr);
720 if (ret < 0) {
761b7910 721 dev_err(data->dev, "Failed to set ODR to %d\n",
c91746a2
IT
722 preset.odr);
723 goto err_poweroff;
724 }
725
726 ret = regmap_write(data->regmap, BMC150_MAGN_REG_REP_XY,
727 BMC150_MAGN_REPXY_TO_REGVAL(preset.rep_xy));
728 if (ret < 0) {
761b7910 729 dev_err(data->dev, "Failed to set REP XY to %d\n",
c91746a2
IT
730 preset.rep_xy);
731 goto err_poweroff;
732 }
733
734 ret = regmap_write(data->regmap, BMC150_MAGN_REG_REP_Z,
735 BMC150_MAGN_REPZ_TO_REGVAL(preset.rep_z));
736 if (ret < 0) {
761b7910 737 dev_err(data->dev, "Failed to set REP Z to %d\n",
c91746a2
IT
738 preset.rep_z);
739 goto err_poweroff;
740 }
741
5990dc97
IT
742 ret = bmc150_magn_set_max_odr(data, preset.rep_xy, preset.rep_z,
743 preset.odr);
744 if (ret < 0)
745 goto err_poweroff;
746
c91746a2
IT
747 ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
748 true);
749 if (ret < 0) {
761b7910 750 dev_err(data->dev, "Failed to power on device\n");
c91746a2
IT
751 goto err_poweroff;
752 }
753
754 return 0;
755
756err_poweroff:
757 bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
758 return ret;
759}
760
761static int bmc150_magn_reset_intr(struct bmc150_magn_data *data)
762{
763 int tmp;
764
765 /*
766 * Data Ready (DRDY) is always cleared after
767 * readout of data registers ends.
768 */
769 return regmap_read(data->regmap, BMC150_MAGN_REG_X_L, &tmp);
770}
771
eca8523a 772static void bmc150_magn_trig_reen(struct iio_trigger *trig)
c91746a2
IT
773{
774 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
775 struct bmc150_magn_data *data = iio_priv(indio_dev);
776 int ret;
777
778 if (!data->dready_trigger_on)
eca8523a 779 return;
c91746a2
IT
780
781 mutex_lock(&data->mutex);
782 ret = bmc150_magn_reset_intr(data);
783 mutex_unlock(&data->mutex);
eca8523a
JC
784 if (ret)
785 dev_err(data->dev, "Failed to reset interrupt\n");
c91746a2
IT
786}
787
788static int bmc150_magn_data_rdy_trigger_set_state(struct iio_trigger *trig,
789 bool state)
790{
791 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
792 struct bmc150_magn_data *data = iio_priv(indio_dev);
793 int ret = 0;
794
795 mutex_lock(&data->mutex);
796 if (state == data->dready_trigger_on)
797 goto err_unlock;
798
c91746a2
IT
799 ret = regmap_update_bits(data->regmap, BMC150_MAGN_REG_INT_DRDY,
800 BMC150_MAGN_MASK_DRDY_EN,
801 state << BMC150_MAGN_SHIFT_DRDY_EN);
802 if (ret < 0)
5ab744d0 803 goto err_unlock;
c91746a2
IT
804
805 data->dready_trigger_on = state;
806
807 if (state) {
808 ret = bmc150_magn_reset_intr(data);
809 if (ret < 0)
5ab744d0 810 goto err_unlock;
c91746a2
IT
811 }
812 mutex_unlock(&data->mutex);
813
814 return 0;
815
c91746a2
IT
816err_unlock:
817 mutex_unlock(&data->mutex);
818 return ret;
819}
820
821static const struct iio_trigger_ops bmc150_magn_trigger_ops = {
822 .set_trigger_state = bmc150_magn_data_rdy_trigger_set_state,
eca8523a 823 .reenable = bmc150_magn_trig_reen,
c91746a2
IT
824};
825
9d174b49
VD
826static int bmc150_magn_buffer_preenable(struct iio_dev *indio_dev)
827{
828 struct bmc150_magn_data *data = iio_priv(indio_dev);
829
830 return bmc150_magn_set_power_state(data, true);
831}
832
833static int bmc150_magn_buffer_postdisable(struct iio_dev *indio_dev)
834{
835 struct bmc150_magn_data *data = iio_priv(indio_dev);
836
837 return bmc150_magn_set_power_state(data, false);
838}
839
840static const struct iio_buffer_setup_ops bmc150_magn_buffer_setup_ops = {
841 .preenable = bmc150_magn_buffer_preenable,
9d174b49
VD
842 .postdisable = bmc150_magn_buffer_postdisable,
843};
844
c91746a2
IT
845static const char *bmc150_magn_match_acpi_device(struct device *dev)
846{
847 const struct acpi_device_id *id;
848
849 id = acpi_match_device(dev->driver->acpi_match_table, dev);
850 if (!id)
851 return NULL;
852
853 return dev_name(dev);
854}
855
761b7910
DB
856int bmc150_magn_probe(struct device *dev, struct regmap *regmap,
857 int irq, const char *name)
c91746a2
IT
858{
859 struct bmc150_magn_data *data;
860 struct iio_dev *indio_dev;
c91746a2
IT
861 int ret;
862
761b7910 863 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
c91746a2
IT
864 if (!indio_dev)
865 return -ENOMEM;
866
867 data = iio_priv(indio_dev);
761b7910
DB
868 dev_set_drvdata(dev, indio_dev);
869 data->regmap = regmap;
870 data->irq = irq;
871 data->dev = dev;
c91746a2 872
d9842c77
NS
873 ret = iio_read_mount_matrix(dev, "mount-matrix",
874 &data->orientation);
875 if (ret)
876 return ret;
877
761b7910
DB
878 if (!name && ACPI_HANDLE(dev))
879 name = bmc150_magn_match_acpi_device(dev);
c91746a2
IT
880
881 mutex_init(&data->mutex);
c91746a2
IT
882
883 ret = bmc150_magn_init(data);
884 if (ret < 0)
885 return ret;
886
c91746a2
IT
887 indio_dev->channels = bmc150_magn_channels;
888 indio_dev->num_channels = ARRAY_SIZE(bmc150_magn_channels);
889 indio_dev->available_scan_masks = bmc150_magn_scan_masks;
890 indio_dev->name = name;
891 indio_dev->modes = INDIO_DIRECT_MODE;
892 indio_dev->info = &bmc150_magn_info;
893
761b7910
DB
894 if (irq > 0) {
895 data->dready_trig = devm_iio_trigger_alloc(dev,
c91746a2
IT
896 "%s-dev%d",
897 indio_dev->name,
898 indio_dev->id);
899 if (!data->dready_trig) {
900 ret = -ENOMEM;
761b7910 901 dev_err(dev, "iio trigger alloc failed\n");
c91746a2
IT
902 goto err_poweroff;
903 }
904
761b7910 905 data->dready_trig->dev.parent = dev;
c91746a2
IT
906 data->dready_trig->ops = &bmc150_magn_trigger_ops;
907 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
908 ret = iio_trigger_register(data->dready_trig);
909 if (ret) {
761b7910 910 dev_err(dev, "iio trigger register failed\n");
c91746a2
IT
911 goto err_poweroff;
912 }
913
761b7910 914 ret = request_threaded_irq(irq,
c91746a2
IT
915 iio_trigger_generic_data_rdy_poll,
916 NULL,
917 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
918 BMC150_MAGN_IRQ_NAME,
919 data->dready_trig);
920 if (ret < 0) {
761b7910 921 dev_err(dev, "request irq %d failed\n", irq);
9d174b49 922 goto err_trigger_unregister;
c91746a2
IT
923 }
924 }
925
9d174b49
VD
926 ret = iio_triggered_buffer_setup(indio_dev,
927 iio_pollfunc_store_time,
928 bmc150_magn_trigger_handler,
929 &bmc150_magn_buffer_setup_ops);
930 if (ret < 0) {
761b7910 931 dev_err(dev, "iio triggered buffer setup failed\n");
9d174b49
VD
932 goto err_free_irq;
933 }
934
761b7910 935 ret = pm_runtime_set_active(dev);
c91746a2 936 if (ret)
7d0ead5c 937 goto err_buffer_cleanup;
c91746a2 938
761b7910
DB
939 pm_runtime_enable(dev);
940 pm_runtime_set_autosuspend_delay(dev,
c91746a2 941 BMC150_MAGN_AUTO_SUSPEND_DELAY_MS);
761b7910 942 pm_runtime_use_autosuspend(dev);
c91746a2 943
7d0ead5c
AR
944 ret = iio_device_register(indio_dev);
945 if (ret < 0) {
761b7910 946 dev_err(dev, "unable to register iio device\n");
7d0ead5c
AR
947 goto err_buffer_cleanup;
948 }
c91746a2 949
761b7910 950 dev_dbg(dev, "Registered device %s\n", name);
c91746a2
IT
951 return 0;
952
9d174b49
VD
953err_buffer_cleanup:
954 iio_triggered_buffer_cleanup(indio_dev);
c91746a2 955err_free_irq:
761b7910
DB
956 if (irq > 0)
957 free_irq(irq, data->dready_trig);
c91746a2
IT
958err_trigger_unregister:
959 if (data->dready_trig)
960 iio_trigger_unregister(data->dready_trig);
961err_poweroff:
962 bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
963 return ret;
964}
761b7910 965EXPORT_SYMBOL(bmc150_magn_probe);
c91746a2 966
761b7910 967int bmc150_magn_remove(struct device *dev)
c91746a2 968{
761b7910 969 struct iio_dev *indio_dev = dev_get_drvdata(dev);
c91746a2
IT
970 struct bmc150_magn_data *data = iio_priv(indio_dev);
971
7d0ead5c
AR
972 iio_device_unregister(indio_dev);
973
761b7910
DB
974 pm_runtime_disable(dev);
975 pm_runtime_set_suspended(dev);
976 pm_runtime_put_noidle(dev);
c91746a2 977
9d174b49 978 iio_triggered_buffer_cleanup(indio_dev);
c91746a2 979
761b7910
DB
980 if (data->irq > 0)
981 free_irq(data->irq, data->dready_trig);
c91746a2 982
9d174b49 983 if (data->dready_trig)
c91746a2 984 iio_trigger_unregister(data->dready_trig);
c91746a2
IT
985
986 mutex_lock(&data->mutex);
987 bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
988 mutex_unlock(&data->mutex);
989
990 return 0;
991}
761b7910 992EXPORT_SYMBOL(bmc150_magn_remove);
c91746a2
IT
993
994#ifdef CONFIG_PM
995static int bmc150_magn_runtime_suspend(struct device *dev)
996{
761b7910 997 struct iio_dev *indio_dev = dev_get_drvdata(dev);
c91746a2
IT
998 struct bmc150_magn_data *data = iio_priv(indio_dev);
999 int ret;
1000
1001 mutex_lock(&data->mutex);
1002 ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SLEEP,
1003 true);
1004 mutex_unlock(&data->mutex);
1005 if (ret < 0) {
761b7910 1006 dev_err(dev, "powering off device failed\n");
c91746a2
IT
1007 return ret;
1008 }
1009 return 0;
1010}
1011
019cc46d
IT
1012/*
1013 * Should be called with data->mutex held.
1014 */
c91746a2
IT
1015static int bmc150_magn_runtime_resume(struct device *dev)
1016{
761b7910 1017 struct iio_dev *indio_dev = dev_get_drvdata(dev);
c91746a2
IT
1018 struct bmc150_magn_data *data = iio_priv(indio_dev);
1019
1020 return bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
1021 true);
1022}
1023#endif
1024
1025#ifdef CONFIG_PM_SLEEP
1026static int bmc150_magn_suspend(struct device *dev)
1027{
761b7910 1028 struct iio_dev *indio_dev = dev_get_drvdata(dev);
c91746a2
IT
1029 struct bmc150_magn_data *data = iio_priv(indio_dev);
1030 int ret;
1031
1032 mutex_lock(&data->mutex);
1033 ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SLEEP,
1034 true);
1035 mutex_unlock(&data->mutex);
1036
1037 return ret;
1038}
1039
1040static int bmc150_magn_resume(struct device *dev)
1041{
761b7910 1042 struct iio_dev *indio_dev = dev_get_drvdata(dev);
c91746a2
IT
1043 struct bmc150_magn_data *data = iio_priv(indio_dev);
1044 int ret;
1045
1046 mutex_lock(&data->mutex);
1047 ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
1048 true);
1049 mutex_unlock(&data->mutex);
1050
1051 return ret;
1052}
1053#endif
1054
761b7910 1055const struct dev_pm_ops bmc150_magn_pm_ops = {
c91746a2
IT
1056 SET_SYSTEM_SLEEP_PM_OPS(bmc150_magn_suspend, bmc150_magn_resume)
1057 SET_RUNTIME_PM_OPS(bmc150_magn_runtime_suspend,
1058 bmc150_magn_runtime_resume, NULL)
1059};
761b7910 1060EXPORT_SYMBOL(bmc150_magn_pm_ops);
c91746a2
IT
1061
1062MODULE_AUTHOR("Irina Tirdea <irina.tirdea@intel.com>");
1063MODULE_LICENSE("GPL v2");
761b7910 1064MODULE_DESCRIPTION("BMC150 magnetometer core driver");